2 * sata_qstor.c - Pacific Digital Corporation QStor SATA
4 * Maintained by: Mark Lord <mlord@pobox.com>
6 * Copyright 2005 Pacific Digital Corporation.
7 * (OSL/GPL code release authorized by Jalil Fadavi).
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; see the file COPYING. If not, write to
22 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 * libata documentation is available via 'make {ps|pdf}docs',
26 * as Documentation/DocBook/libata.*
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/init.h>
34 #include <linux/blkdev.h>
35 #include <linux/delay.h>
36 #include <linux/interrupt.h>
37 #include <linux/sched.h>
38 #include <linux/device.h>
39 #include <scsi/scsi_host.h>
41 #include <linux/libata.h>
43 #define DRV_NAME "sata_qstor"
44 #define DRV_VERSION "0.04"
48 QS_MAX_PRD
= LIBATA_MAX_PRD
,
50 QS_CPB_BYTES
= (1 << QS_CPB_ORDER
),
51 QS_PRD_BYTES
= QS_MAX_PRD
* 16,
52 QS_PKT_BYTES
= QS_CPB_BYTES
+ QS_PRD_BYTES
,
54 /* global register offsets */
55 QS_HCF_CNFG3
= 0x0003, /* host configuration offset */
56 QS_HID_HPHY
= 0x0004, /* host physical interface info */
57 QS_HCT_CTRL
= 0x00e4, /* global interrupt mask offset */
58 QS_HST_SFF
= 0x0100, /* host status fifo offset */
59 QS_HVS_SERD3
= 0x0393, /* PHY enable offset */
61 /* global control bits */
62 QS_HPHY_64BIT
= (1 << 1), /* 64-bit bus detected */
63 QS_CNFG3_GSRST
= 0x01, /* global chip reset */
64 QS_SERD3_PHY_ENA
= 0xf0, /* PHY detection ENAble*/
66 /* per-channel register offsets */
67 QS_CCF_CPBA
= 0x0710, /* chan CPB base address */
68 QS_CCF_CSEP
= 0x0718, /* chan CPB separation factor */
69 QS_CFC_HUFT
= 0x0800, /* host upstream fifo threshold */
70 QS_CFC_HDFT
= 0x0804, /* host downstream fifo threshold */
71 QS_CFC_DUFT
= 0x0808, /* dev upstream fifo threshold */
72 QS_CFC_DDFT
= 0x080c, /* dev downstream fifo threshold */
73 QS_CCT_CTR0
= 0x0900, /* chan control-0 offset */
74 QS_CCT_CTR1
= 0x0901, /* chan control-1 offset */
75 QS_CCT_CFF
= 0x0a00, /* chan command fifo offset */
77 /* channel control bits */
78 QS_CTR0_REG
= (1 << 1), /* register mode (vs. pkt mode) */
79 QS_CTR0_CLER
= (1 << 2), /* clear channel errors */
80 QS_CTR1_RDEV
= (1 << 1), /* sata phy/comms reset */
81 QS_CTR1_RCHN
= (1 << 4), /* reset channel logic */
82 QS_CCF_RUN_PKT
= 0x107, /* RUN a new dma PKT */
84 /* pkt sub-field headers */
85 QS_HCB_HDR
= 0x01, /* Host Control Block header */
86 QS_DCB_HDR
= 0x02, /* Device Control Block header */
88 /* pkt HCB flag bits */
89 QS_HF_DIRO
= (1 << 0), /* data DIRection Out */
90 QS_HF_DAT
= (1 << 3), /* DATa pkt */
91 QS_HF_IEN
= (1 << 4), /* Interrupt ENable */
92 QS_HF_VLD
= (1 << 5), /* VaLiD pkt */
94 /* pkt DCB flag bits */
95 QS_DF_PORD
= (1 << 2), /* Pio OR Dma */
96 QS_DF_ELBA
= (1 << 3), /* Extended LBA (lba48) */
99 board_2068_idx
= 0, /* QStor 4-port SATA/RAID */
103 QS_DMA_BOUNDARY
= ~0UL
106 typedef enum { qs_state_idle
, qs_state_pkt
, qs_state_mmio
} qs_state_t
;
108 struct qs_port_priv
{
114 static u32
qs_scr_read (struct ata_port
*ap
, unsigned int sc_reg
);
115 static void qs_scr_write (struct ata_port
*ap
, unsigned int sc_reg
, u32 val
);
116 static int qs_ata_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
117 static irqreturn_t
qs_intr (int irq
, void *dev_instance
, struct pt_regs
*regs
);
118 static int qs_port_start(struct ata_port
*ap
);
119 static void qs_host_stop(struct ata_host_set
*host_set
);
120 static void qs_port_stop(struct ata_port
*ap
);
121 static void qs_phy_reset(struct ata_port
*ap
);
122 static void qs_qc_prep(struct ata_queued_cmd
*qc
);
123 static int qs_qc_issue(struct ata_queued_cmd
*qc
);
124 static int qs_check_atapi_dma(struct ata_queued_cmd
*qc
);
125 static void qs_bmdma_stop(struct ata_queued_cmd
*qc
);
126 static u8
qs_bmdma_status(struct ata_port
*ap
);
127 static void qs_irq_clear(struct ata_port
*ap
);
128 static void qs_eng_timeout(struct ata_port
*ap
);
130 static struct scsi_host_template qs_ata_sht
= {
131 .module
= THIS_MODULE
,
133 .ioctl
= ata_scsi_ioctl
,
134 .queuecommand
= ata_scsi_queuecmd
,
135 .eh_strategy_handler
= ata_scsi_error
,
136 .can_queue
= ATA_DEF_QUEUE
,
137 .this_id
= ATA_SHT_THIS_ID
,
138 .sg_tablesize
= QS_MAX_PRD
,
139 .max_sectors
= ATA_MAX_SECTORS
,
140 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
141 .emulated
= ATA_SHT_EMULATED
,
142 //FIXME .use_clustering = ATA_SHT_USE_CLUSTERING,
143 .use_clustering
= ENABLE_CLUSTERING
,
144 .proc_name
= DRV_NAME
,
145 .dma_boundary
= QS_DMA_BOUNDARY
,
146 .slave_configure
= ata_scsi_slave_config
,
147 .bios_param
= ata_std_bios_param
,
150 static const struct ata_port_operations qs_ata_ops
= {
151 .port_disable
= ata_port_disable
,
152 .tf_load
= ata_tf_load
,
153 .tf_read
= ata_tf_read
,
154 .check_status
= ata_check_status
,
155 .check_atapi_dma
= qs_check_atapi_dma
,
156 .exec_command
= ata_exec_command
,
157 .dev_select
= ata_std_dev_select
,
158 .phy_reset
= qs_phy_reset
,
159 .qc_prep
= qs_qc_prep
,
160 .qc_issue
= qs_qc_issue
,
161 .eng_timeout
= qs_eng_timeout
,
162 .irq_handler
= qs_intr
,
163 .irq_clear
= qs_irq_clear
,
164 .scr_read
= qs_scr_read
,
165 .scr_write
= qs_scr_write
,
166 .port_start
= qs_port_start
,
167 .port_stop
= qs_port_stop
,
168 .host_stop
= qs_host_stop
,
169 .bmdma_stop
= qs_bmdma_stop
,
170 .bmdma_status
= qs_bmdma_status
,
173 static struct ata_port_info qs_port_info
[] = {
177 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
178 ATA_FLAG_SATA_RESET
|
179 //FIXME ATA_FLAG_SRST |
180 ATA_FLAG_MMIO
| ATA_FLAG_PIO_POLLING
,
181 .pio_mask
= 0x10, /* pio4 */
182 .udma_mask
= 0x7f, /* udma0-6 */
183 .port_ops
= &qs_ata_ops
,
187 static struct pci_device_id qs_ata_pci_tbl
[] = {
188 { PCI_VENDOR_ID_PDC
, 0x2068, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
191 { } /* terminate list */
194 static struct pci_driver qs_ata_pci_driver
= {
196 .id_table
= qs_ata_pci_tbl
,
197 .probe
= qs_ata_init_one
,
198 .remove
= ata_pci_remove_one
,
201 static int qs_check_atapi_dma(struct ata_queued_cmd
*qc
)
203 return 1; /* ATAPI DMA not supported */
206 static void qs_bmdma_stop(struct ata_queued_cmd
*qc
)
211 static u8
qs_bmdma_status(struct ata_port
*ap
)
216 static void qs_irq_clear(struct ata_port
*ap
)
221 static inline void qs_enter_reg_mode(struct ata_port
*ap
)
223 u8 __iomem
*chan
= ap
->host_set
->mmio_base
+ (ap
->port_no
* 0x4000);
225 writeb(QS_CTR0_REG
, chan
+ QS_CCT_CTR0
);
226 readb(chan
+ QS_CCT_CTR0
); /* flush */
229 static inline void qs_reset_channel_logic(struct ata_port
*ap
)
231 u8 __iomem
*chan
= ap
->host_set
->mmio_base
+ (ap
->port_no
* 0x4000);
233 writeb(QS_CTR1_RCHN
, chan
+ QS_CCT_CTR1
);
234 readb(chan
+ QS_CCT_CTR0
); /* flush */
235 qs_enter_reg_mode(ap
);
238 static void qs_phy_reset(struct ata_port
*ap
)
240 struct qs_port_priv
*pp
= ap
->private_data
;
242 pp
->state
= qs_state_idle
;
243 qs_reset_channel_logic(ap
);
247 static void qs_eng_timeout(struct ata_port
*ap
)
249 struct qs_port_priv
*pp
= ap
->private_data
;
251 if (pp
->state
!= qs_state_idle
) /* healthy paranoia */
252 pp
->state
= qs_state_mmio
;
253 qs_reset_channel_logic(ap
);
257 static u32
qs_scr_read (struct ata_port
*ap
, unsigned int sc_reg
)
259 if (sc_reg
> SCR_CONTROL
)
261 return readl((void __iomem
*)(ap
->ioaddr
.scr_addr
+ (sc_reg
* 8)));
264 static void qs_scr_write (struct ata_port
*ap
, unsigned int sc_reg
, u32 val
)
266 if (sc_reg
> SCR_CONTROL
)
268 writel(val
, (void __iomem
*)(ap
->ioaddr
.scr_addr
+ (sc_reg
* 8)));
271 static void qs_fill_sg(struct ata_queued_cmd
*qc
)
273 struct scatterlist
*sg
;
274 struct ata_port
*ap
= qc
->ap
;
275 struct qs_port_priv
*pp
= ap
->private_data
;
277 u8
*prd
= pp
->pkt
+ QS_CPB_BYTES
;
279 assert(qc
->__sg
!= NULL
);
280 assert(qc
->n_elem
> 0);
283 ata_for_each_sg(sg
, qc
) {
287 addr
= sg_dma_address(sg
);
288 *(__le64
*)prd
= cpu_to_le64(addr
);
291 len
= sg_dma_len(sg
);
292 *(__le32
*)prd
= cpu_to_le32(len
);
295 VPRINTK("PRD[%u] = (0x%llX, 0x%X)\n", nelem
,
296 (unsigned long long)addr
, len
);
301 static void qs_qc_prep(struct ata_queued_cmd
*qc
)
303 struct qs_port_priv
*pp
= qc
->ap
->private_data
;
304 u8 dflags
= QS_DF_PORD
, *buf
= pp
->pkt
;
305 u8 hflags
= QS_HF_DAT
| QS_HF_IEN
| QS_HF_VLD
;
310 qs_enter_reg_mode(qc
->ap
);
311 if (qc
->tf
.protocol
!= ATA_PROT_DMA
) {
318 if ((qc
->tf
.flags
& ATA_TFLAG_WRITE
))
319 hflags
|= QS_HF_DIRO
;
320 if ((qc
->tf
.flags
& ATA_TFLAG_LBA48
))
321 dflags
|= QS_DF_ELBA
;
323 /* host control block (HCB) */
324 buf
[ 0] = QS_HCB_HDR
;
326 *(__le32
*)(&buf
[ 4]) = cpu_to_le32(qc
->nsect
* ATA_SECT_SIZE
);
327 *(__le32
*)(&buf
[ 8]) = cpu_to_le32(qc
->n_elem
);
328 addr
= ((u64
)pp
->pkt_dma
) + QS_CPB_BYTES
;
329 *(__le64
*)(&buf
[16]) = cpu_to_le64(addr
);
331 /* device control block (DCB) */
332 buf
[24] = QS_DCB_HDR
;
335 /* frame information structure (FIS) */
336 ata_tf_to_fis(&qc
->tf
, &buf
[32], 0);
339 static inline void qs_packet_start(struct ata_queued_cmd
*qc
)
341 struct ata_port
*ap
= qc
->ap
;
342 u8 __iomem
*chan
= ap
->host_set
->mmio_base
+ (ap
->port_no
* 0x4000);
344 VPRINTK("ENTER, ap %p\n", ap
);
346 writeb(QS_CTR0_CLER
, chan
+ QS_CCT_CTR0
);
347 wmb(); /* flush PRDs and pkt to memory */
348 writel(QS_CCF_RUN_PKT
, chan
+ QS_CCT_CFF
);
349 readl(chan
+ QS_CCT_CFF
); /* flush */
352 static int qs_qc_issue(struct ata_queued_cmd
*qc
)
354 struct qs_port_priv
*pp
= qc
->ap
->private_data
;
356 switch (qc
->tf
.protocol
) {
359 pp
->state
= qs_state_pkt
;
363 case ATA_PROT_ATAPI_DMA
:
371 pp
->state
= qs_state_mmio
;
372 return ata_qc_issue_prot(qc
);
375 static inline unsigned int qs_intr_pkt(struct ata_host_set
*host_set
)
377 unsigned int handled
= 0;
379 u8 __iomem
*mmio_base
= host_set
->mmio_base
;
382 u32 sff0
= readl(mmio_base
+ QS_HST_SFF
);
383 u32 sff1
= readl(mmio_base
+ QS_HST_SFF
+ 4);
384 u8 sEVLD
= (sff1
>> 30) & 0x01; /* valid flag */
385 sFFE
= sff1
>> 31; /* empty flag */
388 u8 sDST
= sff0
>> 16; /* dev status */
389 u8 sHST
= sff1
& 0x3f; /* host status */
390 unsigned int port_no
= (sff1
>> 8) & 0x03;
391 struct ata_port
*ap
= host_set
->ports
[port_no
];
393 DPRINTK("SFF=%08x%08x: sCHAN=%u sHST=%d sDST=%02x\n",
394 sff1
, sff0
, port_no
, sHST
, sDST
);
396 if (ap
&& !(ap
->flags
& ATA_FLAG_PORT_DISABLED
)) {
397 struct ata_queued_cmd
*qc
;
398 struct qs_port_priv
*pp
= ap
->private_data
;
399 if (!pp
|| pp
->state
!= qs_state_pkt
)
401 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
402 if (qc
&& (!(qc
->tf
.flags
& ATA_TFLAG_POLLING
))) {
404 case 0: /* successful CPB */
405 case 3: /* device error */
406 pp
->state
= qs_state_idle
;
407 qs_enter_reg_mode(qc
->ap
);
421 static inline unsigned int qs_intr_mmio(struct ata_host_set
*host_set
)
423 unsigned int handled
= 0, port_no
;
425 for (port_no
= 0; port_no
< host_set
->n_ports
; ++port_no
) {
427 ap
= host_set
->ports
[port_no
];
429 !(ap
->flags
& ATA_FLAG_PORT_DISABLED
)) {
430 struct ata_queued_cmd
*qc
;
431 struct qs_port_priv
*pp
= ap
->private_data
;
432 if (!pp
|| pp
->state
!= qs_state_mmio
)
434 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
435 if (qc
&& (!(qc
->tf
.flags
& ATA_TFLAG_POLLING
))) {
437 /* check main status, clearing INTRQ */
438 u8 status
= ata_check_status(ap
);
439 if ((status
& ATA_BUSY
))
441 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
442 ap
->id
, qc
->tf
.protocol
, status
);
444 /* complete taskfile transaction */
445 pp
->state
= qs_state_idle
;
446 ata_qc_complete(qc
, ac_err_mask(status
));
454 static irqreturn_t
qs_intr(int irq
, void *dev_instance
, struct pt_regs
*regs
)
456 struct ata_host_set
*host_set
= dev_instance
;
457 unsigned int handled
= 0;
461 spin_lock(&host_set
->lock
);
462 handled
= qs_intr_pkt(host_set
) | qs_intr_mmio(host_set
);
463 spin_unlock(&host_set
->lock
);
467 return IRQ_RETVAL(handled
);
470 static void qs_ata_setup_port(struct ata_ioports
*port
, unsigned long base
)
473 port
->data_addr
= base
+ 0x400;
475 port
->feature_addr
= base
+ 0x408; /* hob_feature = 0x409 */
476 port
->nsect_addr
= base
+ 0x410; /* hob_nsect = 0x411 */
477 port
->lbal_addr
= base
+ 0x418; /* hob_lbal = 0x419 */
478 port
->lbam_addr
= base
+ 0x420; /* hob_lbam = 0x421 */
479 port
->lbah_addr
= base
+ 0x428; /* hob_lbah = 0x429 */
480 port
->device_addr
= base
+ 0x430;
482 port
->command_addr
= base
+ 0x438;
483 port
->altstatus_addr
=
484 port
->ctl_addr
= base
+ 0x440;
485 port
->scr_addr
= base
+ 0xc00;
488 static int qs_port_start(struct ata_port
*ap
)
490 struct device
*dev
= ap
->host_set
->dev
;
491 struct qs_port_priv
*pp
;
492 void __iomem
*mmio_base
= ap
->host_set
->mmio_base
;
493 void __iomem
*chan
= mmio_base
+ (ap
->port_no
* 0x4000);
497 rc
= ata_port_start(ap
);
500 qs_enter_reg_mode(ap
);
501 pp
= kzalloc(sizeof(*pp
), GFP_KERNEL
);
506 pp
->pkt
= dma_alloc_coherent(dev
, QS_PKT_BYTES
, &pp
->pkt_dma
,
512 memset(pp
->pkt
, 0, QS_PKT_BYTES
);
513 ap
->private_data
= pp
;
515 addr
= (u64
)pp
->pkt_dma
;
516 writel((u32
) addr
, chan
+ QS_CCF_CPBA
);
517 writel((u32
)(addr
>> 32), chan
+ QS_CCF_CPBA
+ 4);
527 static void qs_port_stop(struct ata_port
*ap
)
529 struct device
*dev
= ap
->host_set
->dev
;
530 struct qs_port_priv
*pp
= ap
->private_data
;
533 ap
->private_data
= NULL
;
535 dma_free_coherent(dev
, QS_PKT_BYTES
, pp
->pkt
,
542 static void qs_host_stop(struct ata_host_set
*host_set
)
544 void __iomem
*mmio_base
= host_set
->mmio_base
;
545 struct pci_dev
*pdev
= to_pci_dev(host_set
->dev
);
547 writeb(0, mmio_base
+ QS_HCT_CTRL
); /* disable host interrupts */
548 writeb(QS_CNFG3_GSRST
, mmio_base
+ QS_HCF_CNFG3
); /* global reset */
550 pci_iounmap(pdev
, mmio_base
);
553 static void qs_host_init(unsigned int chip_id
, struct ata_probe_ent
*pe
)
555 void __iomem
*mmio_base
= pe
->mmio_base
;
556 unsigned int port_no
;
558 writeb(0, mmio_base
+ QS_HCT_CTRL
); /* disable host interrupts */
559 writeb(QS_CNFG3_GSRST
, mmio_base
+ QS_HCF_CNFG3
); /* global reset */
561 /* reset each channel in turn */
562 for (port_no
= 0; port_no
< pe
->n_ports
; ++port_no
) {
563 u8 __iomem
*chan
= mmio_base
+ (port_no
* 0x4000);
564 writeb(QS_CTR1_RDEV
|QS_CTR1_RCHN
, chan
+ QS_CCT_CTR1
);
565 writeb(QS_CTR0_REG
, chan
+ QS_CCT_CTR0
);
566 readb(chan
+ QS_CCT_CTR0
); /* flush */
568 writeb(QS_SERD3_PHY_ENA
, mmio_base
+ QS_HVS_SERD3
); /* enable phy */
570 for (port_no
= 0; port_no
< pe
->n_ports
; ++port_no
) {
571 u8 __iomem
*chan
= mmio_base
+ (port_no
* 0x4000);
572 /* set FIFO depths to same settings as Windows driver */
573 writew(32, chan
+ QS_CFC_HUFT
);
574 writew(32, chan
+ QS_CFC_HDFT
);
575 writew(10, chan
+ QS_CFC_DUFT
);
576 writew( 8, chan
+ QS_CFC_DDFT
);
577 /* set CPB size in bytes, as a power of two */
578 writeb(QS_CPB_ORDER
, chan
+ QS_CCF_CSEP
);
580 writeb(1, mmio_base
+ QS_HCT_CTRL
); /* enable host interrupts */
584 * The QStor understands 64-bit buses, and uses 64-bit fields
585 * for DMA pointers regardless of bus width. We just have to
586 * make sure our DMA masks are set appropriately for whatever
587 * bridge lies between us and the QStor, and then the DMA mapping
588 * code will ensure we only ever "see" appropriate buffer addresses.
589 * If we're 32-bit limited somewhere, then our 64-bit fields will
590 * just end up with zeros in the upper 32-bits, without any special
591 * logic required outside of this routine (below).
593 static int qs_set_dma_masks(struct pci_dev
*pdev
, void __iomem
*mmio_base
)
595 u32 bus_info
= readl(mmio_base
+ QS_HID_HPHY
);
596 int rc
, have_64bit_bus
= (bus_info
& QS_HPHY_64BIT
);
598 if (have_64bit_bus
&&
599 !pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
600 rc
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
602 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
604 dev_printk(KERN_ERR
, &pdev
->dev
,
605 "64-bit DMA enable failed\n");
610 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
612 dev_printk(KERN_ERR
, &pdev
->dev
,
613 "32-bit DMA enable failed\n");
616 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
618 dev_printk(KERN_ERR
, &pdev
->dev
,
619 "32-bit consistent DMA enable failed\n");
626 static int qs_ata_init_one(struct pci_dev
*pdev
,
627 const struct pci_device_id
*ent
)
629 static int printed_version
;
630 struct ata_probe_ent
*probe_ent
= NULL
;
631 void __iomem
*mmio_base
;
632 unsigned int board_idx
= (unsigned int) ent
->driver_data
;
635 if (!printed_version
++)
636 dev_printk(KERN_DEBUG
, &pdev
->dev
, "version " DRV_VERSION
"\n");
638 rc
= pci_enable_device(pdev
);
642 rc
= pci_request_regions(pdev
, DRV_NAME
);
646 if ((pci_resource_flags(pdev
, 4) & IORESOURCE_MEM
) == 0) {
648 goto err_out_regions
;
651 mmio_base
= pci_iomap(pdev
, 4, 0);
652 if (mmio_base
== NULL
) {
654 goto err_out_regions
;
657 rc
= qs_set_dma_masks(pdev
, mmio_base
);
659 goto err_out_iounmap
;
661 probe_ent
= kmalloc(sizeof(*probe_ent
), GFP_KERNEL
);
662 if (probe_ent
== NULL
) {
664 goto err_out_iounmap
;
667 memset(probe_ent
, 0, sizeof(*probe_ent
));
668 probe_ent
->dev
= pci_dev_to_dev(pdev
);
669 INIT_LIST_HEAD(&probe_ent
->node
);
671 probe_ent
->sht
= qs_port_info
[board_idx
].sht
;
672 probe_ent
->host_flags
= qs_port_info
[board_idx
].host_flags
;
673 probe_ent
->pio_mask
= qs_port_info
[board_idx
].pio_mask
;
674 probe_ent
->mwdma_mask
= qs_port_info
[board_idx
].mwdma_mask
;
675 probe_ent
->udma_mask
= qs_port_info
[board_idx
].udma_mask
;
676 probe_ent
->port_ops
= qs_port_info
[board_idx
].port_ops
;
678 probe_ent
->irq
= pdev
->irq
;
679 probe_ent
->irq_flags
= SA_SHIRQ
;
680 probe_ent
->mmio_base
= mmio_base
;
681 probe_ent
->n_ports
= QS_PORTS
;
683 for (port_no
= 0; port_no
< probe_ent
->n_ports
; ++port_no
) {
684 unsigned long chan
= (unsigned long)mmio_base
+
686 qs_ata_setup_port(&probe_ent
->port
[port_no
], chan
);
689 pci_set_master(pdev
);
691 /* initialize adapter */
692 qs_host_init(board_idx
, probe_ent
);
694 rc
= ata_device_add(probe_ent
);
697 goto err_out_iounmap
;
701 pci_iounmap(pdev
, mmio_base
);
703 pci_release_regions(pdev
);
705 pci_disable_device(pdev
);
709 static int __init
qs_ata_init(void)
711 return pci_module_init(&qs_ata_pci_driver
);
714 static void __exit
qs_ata_exit(void)
716 pci_unregister_driver(&qs_ata_pci_driver
);
719 MODULE_AUTHOR("Mark Lord");
720 MODULE_DESCRIPTION("Pacific Digital Corporation QStor SATA low-level driver");
721 MODULE_LICENSE("GPL");
722 MODULE_DEVICE_TABLE(pci
, qs_ata_pci_tbl
);
723 MODULE_VERSION(DRV_VERSION
);
725 module_init(qs_ata_init
);
726 module_exit(qs_ata_exit
);