2 * sata_sis.c - Silicon Integrated Systems SATA
4 * Maintained by: Uwe Koziolek
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004 Uwe Koziolek
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * Hardware documentation available under NDA.
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/device.h>
41 #include <scsi/scsi_host.h>
42 #include <linux/libata.h>
45 #define DRV_NAME "sata_sis"
46 #define DRV_VERSION "0.8"
52 /* PCI configuration registers */
53 SIS_GENCTL
= 0x54, /* IDE General Control register */
54 SIS_SCR_BASE
= 0xc0, /* sata0 phy SCR registers */
55 SIS180_SATA1_OFS
= 0x10, /* offset from sata0->sata1 phy regs */
56 SIS182_SATA1_OFS
= 0x20, /* offset from sata0->sata1 phy regs */
57 SIS_PMR
= 0x90, /* port mapping register */
58 SIS_PMR_COMBINED
= 0x30,
61 SIS_FLAG_CFGSCR
= (1 << 30), /* host flag: SCRs via PCI cfg */
63 GENCTL_IOMAPPED_SCR
= (1 << 26), /* if set, SCRs are in IO space */
66 static int sis_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
67 static int sis_scr_read (struct ata_port
*ap
, unsigned int sc_reg
, u32
*val
);
68 static int sis_scr_write (struct ata_port
*ap
, unsigned int sc_reg
, u32 val
);
70 static const struct pci_device_id sis_pci_tbl
[] = {
71 { PCI_VDEVICE(SI
, 0x0180), sis_180
}, /* SiS 964/180 */
72 { PCI_VDEVICE(SI
, 0x0181), sis_180
}, /* SiS 964/180 */
73 { PCI_VDEVICE(SI
, 0x0182), sis_180
}, /* SiS 965/965L */
74 { PCI_VDEVICE(SI
, 0x0183), sis_180
}, /* SiS 965/965L */
75 { PCI_VDEVICE(SI
, 0x1182), sis_180
}, /* SiS 966/680 */
76 { PCI_VDEVICE(SI
, 0x1183), sis_180
}, /* SiS 966/966L/968/680 */
78 { } /* terminate list */
81 static struct pci_driver sis_pci_driver
= {
83 .id_table
= sis_pci_tbl
,
84 .probe
= sis_init_one
,
85 .remove
= ata_pci_remove_one
,
88 static struct scsi_host_template sis_sht
= {
89 .module
= THIS_MODULE
,
91 .ioctl
= ata_scsi_ioctl
,
92 .queuecommand
= ata_scsi_queuecmd
,
93 .can_queue
= ATA_DEF_QUEUE
,
94 .this_id
= ATA_SHT_THIS_ID
,
95 .sg_tablesize
= ATA_MAX_PRD
,
96 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
97 .emulated
= ATA_SHT_EMULATED
,
98 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
99 .proc_name
= DRV_NAME
,
100 .dma_boundary
= ATA_DMA_BOUNDARY
,
101 .slave_configure
= ata_scsi_slave_config
,
102 .slave_destroy
= ata_scsi_slave_destroy
,
103 .bios_param
= ata_std_bios_param
,
106 static const struct ata_port_operations sis_ops
= {
107 .port_disable
= ata_port_disable
,
108 .tf_load
= ata_tf_load
,
109 .tf_read
= ata_tf_read
,
110 .check_status
= ata_check_status
,
111 .exec_command
= ata_exec_command
,
112 .dev_select
= ata_std_dev_select
,
113 .bmdma_setup
= ata_bmdma_setup
,
114 .bmdma_start
= ata_bmdma_start
,
115 .bmdma_stop
= ata_bmdma_stop
,
116 .bmdma_status
= ata_bmdma_status
,
117 .qc_prep
= ata_qc_prep
,
118 .qc_issue
= ata_qc_issue_prot
,
119 .data_xfer
= ata_data_xfer
,
120 .freeze
= ata_bmdma_freeze
,
121 .thaw
= ata_bmdma_thaw
,
122 .error_handler
= ata_bmdma_error_handler
,
123 .post_internal_cmd
= ata_bmdma_post_internal_cmd
,
124 .irq_clear
= ata_bmdma_irq_clear
,
125 .irq_on
= ata_irq_on
,
126 .irq_ack
= ata_irq_ack
,
127 .scr_read
= sis_scr_read
,
128 .scr_write
= sis_scr_write
,
129 .port_start
= ata_port_start
,
132 static const struct ata_port_info sis_port_info
= {
133 .flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
,
136 .udma_mask
= ATA_UDMA6
,
137 .port_ops
= &sis_ops
,
140 MODULE_AUTHOR("Uwe Koziolek");
141 MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
142 MODULE_LICENSE("GPL");
143 MODULE_DEVICE_TABLE(pci
, sis_pci_tbl
);
144 MODULE_VERSION(DRV_VERSION
);
146 static unsigned int get_scr_cfg_addr(struct ata_port
*ap
, unsigned int sc_reg
)
148 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
149 unsigned int addr
= SIS_SCR_BASE
+ (4 * sc_reg
);
153 switch (pdev
->device
) {
156 pci_read_config_byte(pdev
, SIS_PMR
, &pmr
);
157 if ((pmr
& SIS_PMR_COMBINED
) == 0)
158 addr
+= SIS180_SATA1_OFS
;
164 addr
+= SIS182_SATA1_OFS
;
171 static u32
sis_scr_cfg_read (struct ata_port
*ap
, unsigned int sc_reg
)
173 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
174 unsigned int cfg_addr
= get_scr_cfg_addr(ap
, sc_reg
);
178 if (sc_reg
== SCR_ERROR
) /* doesn't exist in PCI cfg space */
181 pci_read_config_byte(pdev
, SIS_PMR
, &pmr
);
183 pci_read_config_dword(pdev
, cfg_addr
, &val
);
185 if ((pdev
->device
== 0x0182) || (pdev
->device
== 0x0183) ||
186 (pdev
->device
== 0x1182) || (pmr
& SIS_PMR_COMBINED
))
187 pci_read_config_dword(pdev
, cfg_addr
+0x10, &val2
);
189 return (val
|val2
) & 0xfffffffb; /* avoid problems with powerdowned ports */
192 static void sis_scr_cfg_write (struct ata_port
*ap
, unsigned int sc_reg
, u32 val
)
194 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
195 unsigned int cfg_addr
= get_scr_cfg_addr(ap
, sc_reg
);
198 if (sc_reg
== SCR_ERROR
) /* doesn't exist in PCI cfg space */
201 pci_read_config_byte(pdev
, SIS_PMR
, &pmr
);
203 pci_write_config_dword(pdev
, cfg_addr
, val
);
205 if ((pdev
->device
== 0x0182) || (pdev
->device
== 0x0183) ||
206 (pdev
->device
== 0x1182) || (pmr
& SIS_PMR_COMBINED
))
207 pci_write_config_dword(pdev
, cfg_addr
+0x10, val
);
210 static int sis_scr_read(struct ata_port
*ap
, unsigned int sc_reg
, u32
*val
)
212 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
215 if (sc_reg
> SCR_CONTROL
)
218 if (ap
->flags
& SIS_FLAG_CFGSCR
)
219 return sis_scr_cfg_read(ap
, sc_reg
);
221 pci_read_config_byte(pdev
, SIS_PMR
, &pmr
);
223 *val
= ioread32(ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
225 if ((pdev
->device
== 0x0182) || (pdev
->device
== 0x0183) ||
226 (pdev
->device
== 0x1182) || (pmr
& SIS_PMR_COMBINED
))
227 *val
|= ioread32(ap
->ioaddr
.scr_addr
+ (sc_reg
* 4) + 0x10);
234 static int sis_scr_write(struct ata_port
*ap
, unsigned int sc_reg
, u32 val
)
236 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
239 if (sc_reg
> SCR_CONTROL
)
242 pci_read_config_byte(pdev
, SIS_PMR
, &pmr
);
244 if (ap
->flags
& SIS_FLAG_CFGSCR
)
245 sis_scr_cfg_write(ap
, sc_reg
, val
);
247 iowrite32(val
, ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
248 if ((pdev
->device
== 0x0182) || (pdev
->device
== 0x0183) ||
249 (pdev
->device
== 0x1182) || (pmr
& SIS_PMR_COMBINED
))
250 iowrite32(val
, ap
->ioaddr
.scr_addr
+ (sc_reg
* 4)+0x10);
255 static int sis_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
257 static int printed_version
;
258 struct ata_port_info pi
= sis_port_info
;
259 const struct ata_port_info
*ppi
[] = { &pi
, &pi
};
260 struct ata_host
*host
;
263 u8 port2_start
= 0x20;
266 if (!printed_version
++)
267 dev_printk(KERN_INFO
, &pdev
->dev
, "version " DRV_VERSION
"\n");
269 rc
= pcim_enable_device(pdev
);
273 /* check and see if the SCRs are in IO space or PCI cfg space */
274 pci_read_config_dword(pdev
, SIS_GENCTL
, &genctl
);
275 if ((genctl
& GENCTL_IOMAPPED_SCR
) == 0)
276 pi
.flags
|= SIS_FLAG_CFGSCR
;
278 /* if hardware thinks SCRs are in IO space, but there are
279 * no IO resources assigned, change to PCI cfg space.
281 if ((!(pi
.flags
& SIS_FLAG_CFGSCR
)) &&
282 ((pci_resource_start(pdev
, SIS_SCR_PCI_BAR
) == 0) ||
283 (pci_resource_len(pdev
, SIS_SCR_PCI_BAR
) < 128))) {
284 genctl
&= ~GENCTL_IOMAPPED_SCR
;
285 pci_write_config_dword(pdev
, SIS_GENCTL
, genctl
);
286 pi
.flags
|= SIS_FLAG_CFGSCR
;
289 pci_read_config_byte(pdev
, SIS_PMR
, &pmr
);
290 switch (ent
->device
) {
294 /* The PATA-handling is provided by pata_sis */
295 switch (pmr
& 0x30) {
297 ppi
[1] = &sis_info133_for_sata
;
301 ppi
[0] = &sis_info133_for_sata
;
304 if ((pmr
& SIS_PMR_COMBINED
) == 0) {
305 dev_printk(KERN_INFO
, &pdev
->dev
,
306 "Detected SiS 180/181/964 chipset in SATA mode\n");
309 dev_printk(KERN_INFO
, &pdev
->dev
,
310 "Detected SiS 180/181 chipset in combined mode\n");
312 pi
.flags
|= ATA_FLAG_SLAVE_POSS
;
318 pci_read_config_dword ( pdev
, 0x6C, &val
);
319 if (val
& (1L << 31)) {
320 dev_printk(KERN_INFO
, &pdev
->dev
, "Detected SiS 182/965 chipset\n");
321 pi
.flags
|= ATA_FLAG_SLAVE_POSS
;
323 dev_printk(KERN_INFO
, &pdev
->dev
, "Detected SiS 182/965L chipset\n");
328 dev_printk(KERN_INFO
, &pdev
->dev
, "Detected SiS 1182/966/680 SATA controller\n");
329 pi
.flags
|= ATA_FLAG_SLAVE_POSS
;
333 dev_printk(KERN_INFO
, &pdev
->dev
, "Detected SiS 1183/966/966L/968/680 controller in PATA mode\n");
334 ppi
[0] = &sis_info133_for_sata
;
335 ppi
[1] = &sis_info133_for_sata
;
339 rc
= ata_pci_prepare_sff_host(pdev
, ppi
, &host
);
343 if (!(pi
.flags
& SIS_FLAG_CFGSCR
)) {
346 rc
= pcim_iomap_regions(pdev
, 1 << SIS_SCR_PCI_BAR
, DRV_NAME
);
349 mmio
= host
->iomap
[SIS_SCR_PCI_BAR
];
351 host
->ports
[0]->ioaddr
.scr_addr
= mmio
;
352 host
->ports
[1]->ioaddr
.scr_addr
= mmio
+ port2_start
;
355 pci_set_master(pdev
);
357 return ata_host_activate(host
, pdev
->irq
, ata_interrupt
, IRQF_SHARED
,
361 static int __init
sis_init(void)
363 return pci_register_driver(&sis_pci_driver
);
366 static void __exit
sis_exit(void)
368 pci_unregister_driver(&sis_pci_driver
);
371 module_init(sis_init
);
372 module_exit(sis_exit
);