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[PATCH] Driver Core: remove driver model detach_state
[linux-2.6/verdex.git] / drivers / media / dvb / frontends / dib3000mc.c
blob888f10a5e96b28bc469c9d14c4b265b89a527dc0
1 /*
2 * Frontend driver for mobile DVB-T demodulator DiBcom 3000P/M-C
3 * DiBcom (http://www.dibcom.fr/)
4 *
5 * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@desy.de)
6 *
7 * based on GPL code from DiBCom, which has
8 *
9 * Copyright (C) 2004 Amaury Demol for DiBcom (ademol@dibcom.fr)
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation, version 2.
14 *
15 * Acknowledgements
16 *
17 * Amaury Demol (ademol@dibcom.fr) from DiBcom for providing specs and driver
18 * sources, on which this driver (and the dvb-dibusb) are based.
19 *
20 * see Documentation/dvb/README.dibusb for more information
21 *
22 */
23 #include <linux/config.h>
24 #include <linux/kernel.h>
25 #include <linux/version.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/init.h>
29 #include <linux/delay.h>
30
31 #include "dib3000-common.h"
32 #include "dib3000mc_priv.h"
33 #include "dib3000.h"
34
35 /* Version information */
36 #define DRIVER_VERSION "0.1"
37 #define DRIVER_DESC "DiBcom 3000M-C DVB-T demodulator"
38 #define DRIVER_AUTHOR "Patrick Boettcher, patrick.boettcher@desy.de"
39
40 #ifdef CONFIG_DVB_DIBCOM_DEBUG
41 static int debug;
42 module_param(debug, int, 0644);
43 MODULE_PARM_DESC(debug, "set debugging level (1=info,2=xfer,4=setfe,8=getfe,16=stat (|-able)).");
44 #endif
45 #define deb_info(args...) dprintk(0x01,args)
46 #define deb_xfer(args...) dprintk(0x02,args)
47 #define deb_setf(args...) dprintk(0x04,args)
48 #define deb_getf(args...) dprintk(0x08,args)
49 #define deb_stat(args...) dprintk(0x10,args)
50
51 static int dib3000mc_tuner_pass_ctrl(struct dvb_frontend *fe, int onoff, u8 pll_addr);
52
53 static int dib3000mc_set_impulse_noise(struct dib3000_state * state, int mode,
54 fe_transmit_mode_t transmission_mode, fe_bandwidth_t bandwidth)
55 {
56 switch (transmission_mode) {
57 case TRANSMISSION_MODE_2K:
58 wr_foreach(dib3000mc_reg_fft,dib3000mc_fft_modes[0]);
59 break;
60 case TRANSMISSION_MODE_8K:
61 wr_foreach(dib3000mc_reg_fft,dib3000mc_fft_modes[1]);
62 break;
63 default:
64 break;
65 }
66
67 switch (bandwidth) {
68 /* case BANDWIDTH_5_MHZ:
69 wr_foreach(dib3000mc_reg_impulse_noise,dib3000mc_impluse_noise[0]);
70 break; */
71 case BANDWIDTH_6_MHZ:
72 wr_foreach(dib3000mc_reg_impulse_noise,dib3000mc_impluse_noise[1]);
73 break;
74 case BANDWIDTH_7_MHZ:
75 wr_foreach(dib3000mc_reg_impulse_noise,dib3000mc_impluse_noise[2]);
76 break;
77 case BANDWIDTH_8_MHZ:
78 wr_foreach(dib3000mc_reg_impulse_noise,dib3000mc_impluse_noise[3]);
79 break;
80 default:
81 break;
82 }
83
84 switch (mode) {
85 case 0: /* no impulse */ /* fall through */
86 wr_foreach(dib3000mc_reg_imp_noise_ctl,dib3000mc_imp_noise_ctl[0]);
87 break;
88 case 1: /* new algo */
89 wr_foreach(dib3000mc_reg_imp_noise_ctl,dib3000mc_imp_noise_ctl[1]);
90 set_or(DIB3000MC_REG_IMP_NOISE_55,DIB3000MC_IMP_NEW_ALGO(0)); /* gives 1<<10 */
91 break;
92 default: /* old algo */
93 wr_foreach(dib3000mc_reg_imp_noise_ctl,dib3000mc_imp_noise_ctl[3]);
94 break;
95 }
96 return 0;
97 }
98
99 static int dib3000mc_set_timing(struct dib3000_state *state, int upd_offset,
100 fe_transmit_mode_t fft, fe_bandwidth_t bw)
101 {
102 u16 timf_msb,timf_lsb;
103 s32 tim_offset,tim_sgn;
104 u64 comp1,comp2,comp=0;
105
106 switch (bw) {
107 case BANDWIDTH_8_MHZ: comp = DIB3000MC_CLOCK_REF*8; break;
108 case BANDWIDTH_7_MHZ: comp = DIB3000MC_CLOCK_REF*7; break;
109 case BANDWIDTH_6_MHZ: comp = DIB3000MC_CLOCK_REF*6; break;
110 default: err("unknown bandwidth (%d)",bw); break;
111 }
112 timf_msb = (comp >> 16) & 0xff;
113 timf_lsb = (comp & 0xffff);
114
115 // Update the timing offset ;
116 if (upd_offset > 0) {
117 if (!state->timing_offset_comp_done) {
118 msleep(200);
119 state->timing_offset_comp_done = 1;
120 }
121 tim_offset = rd(DIB3000MC_REG_TIMING_OFFS_MSB);
122 if ((tim_offset & 0x2000) == 0x2000)
123 tim_offset |= 0xC000;
124 if (fft == TRANSMISSION_MODE_2K)
125 tim_offset <<= 2;
126 state->timing_offset += tim_offset;
127 }
128
129 tim_offset = state->timing_offset;
130 if (tim_offset < 0) {
131 tim_sgn = 1;
132 tim_offset = -tim_offset;
133 } else
134 tim_sgn = 0;
135
136 comp1 = (u32)tim_offset * (u32)timf_lsb ;
137 comp2 = (u32)tim_offset * (u32)timf_msb ;
138 comp = ((comp1 >> 16) + comp2) >> 7;
139
140 if (tim_sgn == 0)
141 comp = (u32)(timf_msb << 16) + (u32) timf_lsb + comp;
142 else
143 comp = (u32)(timf_msb << 16) + (u32) timf_lsb - comp ;
144
145 timf_msb = (comp >> 16) & 0xff;
146 timf_lsb = comp & 0xffff;
147
148 wr(DIB3000MC_REG_TIMING_FREQ_MSB,timf_msb);
149 wr(DIB3000MC_REG_TIMING_FREQ_LSB,timf_lsb);
150 return 0;
151 }
152
153 static int dib3000mc_init_auto_scan(struct dib3000_state *state, fe_bandwidth_t bw, int boost)
154 {
155 if (boost) {
156 wr(DIB3000MC_REG_SCAN_BOOST,DIB3000MC_SCAN_BOOST_ON);
157 } else {
158 wr(DIB3000MC_REG_SCAN_BOOST,DIB3000MC_SCAN_BOOST_OFF);
159 }
160 switch (bw) {
161 case BANDWIDTH_8_MHZ:
162 wr_foreach(dib3000mc_reg_bandwidth,dib3000mc_bandwidth_8mhz);
163 break;
164 case BANDWIDTH_7_MHZ:
165 wr_foreach(dib3000mc_reg_bandwidth,dib3000mc_bandwidth_7mhz);
166 break;
167 case BANDWIDTH_6_MHZ:
168 wr_foreach(dib3000mc_reg_bandwidth,dib3000mc_bandwidth_6mhz);
169 break;
170 /* case BANDWIDTH_5_MHZ:
171 wr_foreach(dib3000mc_reg_bandwidth,dib3000mc_bandwidth_5mhz);
172 break;*/
173 case BANDWIDTH_AUTO:
174 return -EOPNOTSUPP;
175 default:
176 err("unknown bandwidth value (%d).",bw);
177 return -EINVAL;
178 }
179 if (boost) {
180 u32 timeout = (rd(DIB3000MC_REG_BW_TIMOUT_MSB) << 16) +
181 rd(DIB3000MC_REG_BW_TIMOUT_LSB);
182 timeout *= 85; timeout >>= 7;
183 wr(DIB3000MC_REG_BW_TIMOUT_MSB,(timeout >> 16) & 0xffff);
184 wr(DIB3000MC_REG_BW_TIMOUT_LSB,timeout & 0xffff);
185 }
186 return 0;
187 }
188
189 static int dib3000mc_set_adp_cfg(struct dib3000_state *state, fe_modulation_t con)
190 {
191 switch (con) {
192 case QAM_64:
193 wr_foreach(dib3000mc_reg_adp_cfg,dib3000mc_adp_cfg[2]);
194 break;
195 case QAM_16:
196 wr_foreach(dib3000mc_reg_adp_cfg,dib3000mc_adp_cfg[1]);
197 break;
198 case QPSK:
199 wr_foreach(dib3000mc_reg_adp_cfg,dib3000mc_adp_cfg[0]);
200 break;
201 case QAM_AUTO:
202 break;
203 default:
204 warn("unkown constellation.");
205 break;
206 }
207 return 0;
208 }
209
210 static int dib3000mc_set_general_cfg(struct dib3000_state *state, struct dvb_frontend_parameters *fep, int *auto_val)
211 {
212 struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
213 fe_code_rate_t fe_cr = FEC_NONE;
214 u8 fft=0, guard=0, qam=0, alpha=0, sel_hp=0, cr=0, hrch=0;
215 int seq;
216
217 switch (ofdm->transmission_mode) {
218 case TRANSMISSION_MODE_2K: fft = DIB3000_TRANSMISSION_MODE_2K; break;
219 case TRANSMISSION_MODE_8K: fft = DIB3000_TRANSMISSION_MODE_8K; break;
220 case TRANSMISSION_MODE_AUTO: break;
221 default: return -EINVAL;
222 }
223 switch (ofdm->guard_interval) {
224 case GUARD_INTERVAL_1_32: guard = DIB3000_GUARD_TIME_1_32; break;
225 case GUARD_INTERVAL_1_16: guard = DIB3000_GUARD_TIME_1_16; break;
226 case GUARD_INTERVAL_1_8: guard = DIB3000_GUARD_TIME_1_8; break;
227 case GUARD_INTERVAL_1_4: guard = DIB3000_GUARD_TIME_1_4; break;
228 case GUARD_INTERVAL_AUTO: break;
229 default: return -EINVAL;
230 }
231 switch (ofdm->constellation) {
232 case QPSK: qam = DIB3000_CONSTELLATION_QPSK; break;
233 case QAM_16: qam = DIB3000_CONSTELLATION_16QAM; break;
234 case QAM_64: qam = DIB3000_CONSTELLATION_64QAM; break;
235 case QAM_AUTO: break;
236 default: return -EINVAL;
237 }
238 switch (ofdm->hierarchy_information) {
239 case HIERARCHY_NONE: /* fall through */
240 case HIERARCHY_1: alpha = DIB3000_ALPHA_1; break;
241 case HIERARCHY_2: alpha = DIB3000_ALPHA_2; break;
242 case HIERARCHY_4: alpha = DIB3000_ALPHA_4; break;
243 case HIERARCHY_AUTO: break;
244 default: return -EINVAL;
245 }
246 if (ofdm->hierarchy_information == HIERARCHY_NONE) {
247 hrch = DIB3000_HRCH_OFF;
248 sel_hp = DIB3000_SELECT_HP;
249 fe_cr = ofdm->code_rate_HP;
250 } else if (ofdm->hierarchy_information != HIERARCHY_AUTO) {
251 hrch = DIB3000_HRCH_ON;
252 sel_hp = DIB3000_SELECT_LP;
253 fe_cr = ofdm->code_rate_LP;
254 }
255 switch (fe_cr) {
256 case FEC_1_2: cr = DIB3000_FEC_1_2; break;
257 case FEC_2_3: cr = DIB3000_FEC_2_3; break;
258 case FEC_3_4: cr = DIB3000_FEC_3_4; break;
259 case FEC_5_6: cr = DIB3000_FEC_5_6; break;
260 case FEC_7_8: cr = DIB3000_FEC_7_8; break;
261 case FEC_NONE: break;
262 case FEC_AUTO: break;
263 default: return -EINVAL;
264 }
265
266 wr(DIB3000MC_REG_DEMOD_PARM,DIB3000MC_DEMOD_PARM(alpha,qam,guard,fft));
267 wr(DIB3000MC_REG_HRCH_PARM,DIB3000MC_HRCH_PARM(sel_hp,cr,hrch));
268
269 switch (fep->inversion) {
270 case INVERSION_OFF:
271 wr(DIB3000MC_REG_SET_DDS_FREQ_MSB,DIB3000MC_DDS_FREQ_MSB_INV_OFF);
272 break;
273 case INVERSION_AUTO: /* fall through */
274 case INVERSION_ON:
275 wr(DIB3000MC_REG_SET_DDS_FREQ_MSB,DIB3000MC_DDS_FREQ_MSB_INV_ON);
276 break;
277 default:
278 return -EINVAL;
279 }
280
281 seq = dib3000_seq
282 [ofdm->transmission_mode == TRANSMISSION_MODE_AUTO]
283 [ofdm->guard_interval == GUARD_INTERVAL_AUTO]
284 [fep->inversion == INVERSION_AUTO];
285
286 deb_setf("seq? %d\n", seq);
287 wr(DIB3000MC_REG_SEQ_TPS,DIB3000MC_SEQ_TPS(seq,1));
288 *auto_val = ofdm->constellation == QAM_AUTO ||
289 ofdm->hierarchy_information == HIERARCHY_AUTO ||
290 ofdm->guard_interval == GUARD_INTERVAL_AUTO ||
291 ofdm->transmission_mode == TRANSMISSION_MODE_AUTO ||
292 fe_cr == FEC_AUTO ||
293 fep->inversion == INVERSION_AUTO;
294 return 0;
295 }
296
297 static int dib3000mc_get_frontend(struct dvb_frontend* fe,
298 struct dvb_frontend_parameters *fep)
299 {
300 struct dib3000_state* state = fe->demodulator_priv;
301 struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
302 fe_code_rate_t *cr;
303 u16 tps_val,cr_val;
304 int inv_test1,inv_test2;
305 u32 dds_val, threshold = 0x1000000;
306
307 if (!(rd(DIB3000MC_REG_LOCK_507) & DIB3000MC_LOCK_507))
308 return 0;
309
310 dds_val = (rd(DIB3000MC_REG_DDS_FREQ_MSB) << 16) + rd(DIB3000MC_REG_DDS_FREQ_LSB);
311 deb_getf("DDS_FREQ: %6x\n",dds_val);
312 if (dds_val < threshold)
313 inv_test1 = 0;
314 else if (dds_val == threshold)
315 inv_test1 = 1;
316 else
317 inv_test1 = 2;
318
319 dds_val = (rd(DIB3000MC_REG_SET_DDS_FREQ_MSB) << 16) + rd(DIB3000MC_REG_SET_DDS_FREQ_LSB);
320 deb_getf("DDS_SET_FREQ: %6x\n",dds_val);
321 if (dds_val < threshold)
322 inv_test2 = 0;
323 else if (dds_val == threshold)
324 inv_test2 = 1;
325 else
326 inv_test2 = 2;
327
328 fep->inversion =
329 ((inv_test2 == 2) && (inv_test1==1 || inv_test1==0)) ||
330 ((inv_test2 == 0) && (inv_test1==1 || inv_test1==2)) ?
331 INVERSION_ON : INVERSION_OFF;
332
333 deb_getf("inversion %d %d, %d\n", inv_test2, inv_test1, fep->inversion);
334
335 fep->frequency = state->last_tuned_freq;
336 fep->u.ofdm.bandwidth= state->last_tuned_bw;
337
338 tps_val = rd(DIB3000MC_REG_TUNING_PARM);
339
340 switch (DIB3000MC_TP_QAM(tps_val)) {
341 case DIB3000_CONSTELLATION_QPSK:
342 deb_getf("QPSK ");
343 ofdm->constellation = QPSK;
344 break;
345 case DIB3000_CONSTELLATION_16QAM:
346 deb_getf("QAM16 ");
347 ofdm->constellation = QAM_16;
348 break;
349 case DIB3000_CONSTELLATION_64QAM:
350 deb_getf("QAM64 ");
351 ofdm->constellation = QAM_64;
352 break;
353 default:
354 err("Unexpected constellation returned by TPS (%d)", tps_val);
355 break;
356 }
357
358 if (DIB3000MC_TP_HRCH(tps_val)) {
359 deb_getf("HRCH ON ");
360 cr = &ofdm->code_rate_LP;
361 ofdm->code_rate_HP = FEC_NONE;
362 switch (DIB3000MC_TP_ALPHA(tps_val)) {
363 case DIB3000_ALPHA_0:
364 deb_getf("HIERARCHY_NONE ");
365 ofdm->hierarchy_information = HIERARCHY_NONE;
366 break;
367 case DIB3000_ALPHA_1:
368 deb_getf("HIERARCHY_1 ");
369 ofdm->hierarchy_information = HIERARCHY_1;
370 break;
371 case DIB3000_ALPHA_2:
372 deb_getf("HIERARCHY_2 ");
373 ofdm->hierarchy_information = HIERARCHY_2;
374 break;
375 case DIB3000_ALPHA_4:
376 deb_getf("HIERARCHY_4 ");
377 ofdm->hierarchy_information = HIERARCHY_4;
378 break;
379 default:
380 err("Unexpected ALPHA value returned by TPS (%d)", tps_val);
381 break;
382 }
383 cr_val = DIB3000MC_TP_FEC_CR_LP(tps_val);
384 } else {
385 deb_getf("HRCH OFF ");
386 cr = &ofdm->code_rate_HP;
387 ofdm->code_rate_LP = FEC_NONE;
388 ofdm->hierarchy_information = HIERARCHY_NONE;
389 cr_val = DIB3000MC_TP_FEC_CR_HP(tps_val);
390 }
391
392 switch (cr_val) {
393 case DIB3000_FEC_1_2:
394 deb_getf("FEC_1_2 ");
395 *cr = FEC_1_2;
396 break;
397 case DIB3000_FEC_2_3:
398 deb_getf("FEC_2_3 ");
399 *cr = FEC_2_3;
400 break;
401 case DIB3000_FEC_3_4:
402 deb_getf("FEC_3_4 ");
403 *cr = FEC_3_4;
404 break;
405 case DIB3000_FEC_5_6:
406 deb_getf("FEC_5_6 ");
407 *cr = FEC_4_5;
408 break;
409 case DIB3000_FEC_7_8:
410 deb_getf("FEC_7_8 ");
411 *cr = FEC_7_8;
412 break;
413 default:
414 err("Unexpected FEC returned by TPS (%d)", tps_val);
415 break;
416 }
417
418 switch (DIB3000MC_TP_GUARD(tps_val)) {
419 case DIB3000_GUARD_TIME_1_32:
420 deb_getf("GUARD_INTERVAL_1_32 ");
421 ofdm->guard_interval = GUARD_INTERVAL_1_32;
422 break;
423 case DIB3000_GUARD_TIME_1_16:
424 deb_getf("GUARD_INTERVAL_1_16 ");
425 ofdm->guard_interval = GUARD_INTERVAL_1_16;
426 break;
427 case DIB3000_GUARD_TIME_1_8:
428 deb_getf("GUARD_INTERVAL_1_8 ");
429 ofdm->guard_interval = GUARD_INTERVAL_1_8;
430 break;
431 case DIB3000_GUARD_TIME_1_4:
432 deb_getf("GUARD_INTERVAL_1_4 ");
433 ofdm->guard_interval = GUARD_INTERVAL_1_4;
434 break;
435 default:
436 err("Unexpected Guard Time returned by TPS (%d)", tps_val);
437 break;
438 }
439
440 switch (DIB3000MC_TP_FFT(tps_val)) {
441 case DIB3000_TRANSMISSION_MODE_2K:
442 deb_getf("TRANSMISSION_MODE_2K ");
443 ofdm->transmission_mode = TRANSMISSION_MODE_2K;
444 break;
445 case DIB3000_TRANSMISSION_MODE_8K:
446 deb_getf("TRANSMISSION_MODE_8K ");
447 ofdm->transmission_mode = TRANSMISSION_MODE_8K;
448 break;
449 default:
450 err("unexpected transmission mode return by TPS (%d)", tps_val);
451 break;
452 }
453 deb_getf("\n");
454
455 return 0;
456 }
457
458 static int dib3000mc_set_frontend(struct dvb_frontend* fe,
459 struct dvb_frontend_parameters *fep, int tuner)
460 {
461 struct dib3000_state* state = fe->demodulator_priv;
462 struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
463 int search_state,auto_val;
464 u16 val;
465
466 if (tuner && state->config.pll_addr && state->config.pll_set) { /* initial call from dvb */
467 dib3000mc_tuner_pass_ctrl(fe,1,state->config.pll_addr(fe));
468 state->config.pll_set(fe,fep,NULL);
469 dib3000mc_tuner_pass_ctrl(fe,0,state->config.pll_addr(fe));
470
471 state->last_tuned_freq = fep->frequency;
472 // if (!scanboost) {
473 dib3000mc_set_timing(state,0,ofdm->transmission_mode,ofdm->bandwidth);
474 dib3000mc_init_auto_scan(state, ofdm->bandwidth, 0);
475 state->last_tuned_bw = ofdm->bandwidth;
476
477 wr_foreach(dib3000mc_reg_agc_bandwidth,dib3000mc_agc_bandwidth);
478 wr(DIB3000MC_REG_RESTART,DIB3000MC_RESTART_AGC);
479 wr(DIB3000MC_REG_RESTART,DIB3000MC_RESTART_OFF);
480
481 /* Default cfg isi offset adp */
482 wr_foreach(dib3000mc_reg_offset,dib3000mc_offset[0]);
483
484 wr(DIB3000MC_REG_ISI,DIB3000MC_ISI_DEFAULT | DIB3000MC_ISI_INHIBIT);
485 dib3000mc_set_adp_cfg(state,ofdm->constellation);
486 wr(DIB3000MC_REG_UNK_133,DIB3000MC_UNK_133);
487
488 wr_foreach(dib3000mc_reg_bandwidth_general,dib3000mc_bandwidth_general);
489 /* power smoothing */
490 if (ofdm->bandwidth != BANDWIDTH_8_MHZ) {
491 wr_foreach(dib3000mc_reg_bw,dib3000mc_bw[0]);
492 } else {
493 wr_foreach(dib3000mc_reg_bw,dib3000mc_bw[3]);
494 }
495 auto_val = 0;
496 dib3000mc_set_general_cfg(state,fep,&auto_val);
497 dib3000mc_set_impulse_noise(state,0,ofdm->constellation,ofdm->bandwidth);
498
499 val = rd(DIB3000MC_REG_DEMOD_PARM);
500 wr(DIB3000MC_REG_DEMOD_PARM,val|DIB3000MC_DEMOD_RST_DEMOD_ON);
501 wr(DIB3000MC_REG_DEMOD_PARM,val);
502 // }
503 msleep(70);
504
505 /* something has to be auto searched */
506 if (auto_val) {
507 int as_count=0;
508
509 deb_setf("autosearch enabled.\n");
510
511 val = rd(DIB3000MC_REG_DEMOD_PARM);
512 wr(DIB3000MC_REG_DEMOD_PARM,val | DIB3000MC_DEMOD_RST_AUTO_SRCH_ON);
513 wr(DIB3000MC_REG_DEMOD_PARM,val);
514
515 while ((search_state = dib3000_search_status(
516 rd(DIB3000MC_REG_AS_IRQ),1)) < 0 && as_count++ < 100)
517 msleep(10);
518
519 deb_info("search_state after autosearch %d after %d checks\n",search_state,as_count);
520
521 if (search_state == 1) {
522 struct dvb_frontend_parameters feps;
523 if (dib3000mc_get_frontend(fe, &feps) == 0) {
524 deb_setf("reading tuning data from frontend succeeded.\n");
525 return dib3000mc_set_frontend(fe, &feps, 0);
526 }
527 }
528 } else {
529 dib3000mc_set_impulse_noise(state,0,ofdm->transmission_mode,ofdm->bandwidth);
530 wr(DIB3000MC_REG_ISI,DIB3000MC_ISI_DEFAULT|DIB3000MC_ISI_ACTIVATE);
531 dib3000mc_set_adp_cfg(state,ofdm->constellation);
532
533 /* set_offset_cfg */
534 wr_foreach(dib3000mc_reg_offset,
535 dib3000mc_offset[(ofdm->transmission_mode == TRANSMISSION_MODE_8K)+1]);
536 }
537 } else { /* second call, after autosearch (fka: set_WithKnownParams) */
538 // dib3000mc_set_timing(state,1,ofdm->transmission_mode,ofdm->bandwidth);
539
540 auto_val = 0;
541 dib3000mc_set_general_cfg(state,fep,&auto_val);
542 if (auto_val)
543 deb_info("auto_val is true, even though an auto search was already performed.\n");
544
545 dib3000mc_set_impulse_noise(state,0,ofdm->constellation,ofdm->bandwidth);
546
547 val = rd(DIB3000MC_REG_DEMOD_PARM);
548 wr(DIB3000MC_REG_DEMOD_PARM,val | DIB3000MC_DEMOD_RST_AUTO_SRCH_ON);
549 wr(DIB3000MC_REG_DEMOD_PARM,val);
550
551 msleep(30);
552
553 wr(DIB3000MC_REG_ISI,DIB3000MC_ISI_DEFAULT|DIB3000MC_ISI_ACTIVATE);
554 dib3000mc_set_adp_cfg(state,ofdm->constellation);
555 wr_foreach(dib3000mc_reg_offset,
556 dib3000mc_offset[(ofdm->transmission_mode == TRANSMISSION_MODE_8K)+1]);
557
558
559 }
560 return 0;
561 }
562
563 static int dib3000mc_fe_init(struct dvb_frontend* fe, int mobile_mode)
564 {
565 struct dib3000_state *state;
566
567 deb_info("init start\n");
568
569 state = fe->demodulator_priv;
570 state->timing_offset = 0;
571 state->timing_offset_comp_done = 0;
572
573 wr(DIB3000MC_REG_RESTART,DIB3000MC_RESTART_CONFIG);
574 wr(DIB3000MC_REG_RESTART,DIB3000MC_RESTART_OFF);
575 wr(DIB3000MC_REG_CLK_CFG_1,DIB3000MC_CLK_CFG_1_POWER_UP);
576 wr(DIB3000MC_REG_CLK_CFG_2,DIB3000MC_CLK_CFG_2_PUP_MOBILE);
577 wr(DIB3000MC_REG_CLK_CFG_3,DIB3000MC_CLK_CFG_3_POWER_UP);
578 wr(DIB3000MC_REG_CLK_CFG_7,DIB3000MC_CLK_CFG_7_INIT);
579
580 wr(DIB3000MC_REG_RST_UNC,DIB3000MC_RST_UNC_OFF);
581 wr(DIB3000MC_REG_UNK_19,DIB3000MC_UNK_19);
582
583 wr(33,5);
584 wr(36,81);
585 wr(DIB3000MC_REG_UNK_88,DIB3000MC_UNK_88);
586
587 wr(DIB3000MC_REG_UNK_99,DIB3000MC_UNK_99);
588 wr(DIB3000MC_REG_UNK_111,DIB3000MC_UNK_111_PH_N_MODE_0); /* phase noise algo off */
589
590 /* mobile mode - portable reception */
591 wr_foreach(dib3000mc_reg_mobile_mode,dib3000mc_mobile_mode[1]);
592
593 /* TUNER_PANASONIC_ENV57H12D5: */
594 wr_foreach(dib3000mc_reg_agc_bandwidth,dib3000mc_agc_bandwidth);
595 wr_foreach(dib3000mc_reg_agc_bandwidth_general,dib3000mc_agc_bandwidth_general);
596 wr_foreach(dib3000mc_reg_agc,dib3000mc_agc_tuner[1]);
597
598 wr(DIB3000MC_REG_UNK_110,DIB3000MC_UNK_110);
599 wr(26,0x6680);
600 wr(DIB3000MC_REG_UNK_1,DIB3000MC_UNK_1);
601 wr(DIB3000MC_REG_UNK_2,DIB3000MC_UNK_2);
602 wr(DIB3000MC_REG_UNK_3,DIB3000MC_UNK_3);
603 wr(DIB3000MC_REG_SEQ_TPS,DIB3000MC_SEQ_TPS_DEFAULT);
604
605 wr_foreach(dib3000mc_reg_bandwidth,dib3000mc_bandwidth_8mhz);
606 wr_foreach(dib3000mc_reg_bandwidth_general,dib3000mc_bandwidth_general);
607
608 wr(DIB3000MC_REG_UNK_4,DIB3000MC_UNK_4);
609
610 wr(DIB3000MC_REG_SET_DDS_FREQ_MSB,DIB3000MC_DDS_FREQ_MSB_INV_OFF);
611 wr(DIB3000MC_REG_SET_DDS_FREQ_LSB,DIB3000MC_DDS_FREQ_LSB);
612
613 dib3000mc_set_timing(state,0,TRANSMISSION_MODE_8K,BANDWIDTH_8_MHZ);
614 // wr_foreach(dib3000mc_reg_timing_freq,dib3000mc_timing_freq[3]);
615
616 wr(DIB3000MC_REG_UNK_120,DIB3000MC_UNK_120);
617 wr(DIB3000MC_REG_UNK_134,DIB3000MC_UNK_134);
618 wr(DIB3000MC_REG_FEC_CFG,DIB3000MC_FEC_CFG);
619
620 wr(DIB3000MC_REG_DIVERSITY3,DIB3000MC_DIVERSITY3_IN_OFF);
621
622 dib3000mc_set_impulse_noise(state,0,TRANSMISSION_MODE_8K,BANDWIDTH_8_MHZ);
623
624 /* output mode control, just the MPEG2_SLAVE */
625 // set_or(DIB3000MC_REG_OUTMODE,DIB3000MC_OM_SLAVE);
626 wr(DIB3000MC_REG_OUTMODE,DIB3000MC_OM_SLAVE);
627 wr(DIB3000MC_REG_SMO_MODE,DIB3000MC_SMO_MODE_SLAVE);
628 wr(DIB3000MC_REG_FIFO_THRESHOLD,DIB3000MC_FIFO_THRESHOLD_SLAVE);
629 wr(DIB3000MC_REG_ELEC_OUT,DIB3000MC_ELEC_OUT_SLAVE);
630
631 /* MPEG2_PARALLEL_CONTINUOUS_CLOCK
632 wr(DIB3000MC_REG_OUTMODE,
633 DIB3000MC_SET_OUTMODE(DIB3000MC_OM_PAR_CONT_CLK,
634 rd(DIB3000MC_REG_OUTMODE)));
635
636 wr(DIB3000MC_REG_SMO_MODE,
637 DIB3000MC_SMO_MODE_DEFAULT |
638 DIB3000MC_SMO_MODE_188);
639
640 wr(DIB3000MC_REG_FIFO_THRESHOLD,DIB3000MC_FIFO_THRESHOLD_DEFAULT);
641 wr(DIB3000MC_REG_ELEC_OUT,DIB3000MC_ELEC_OUT_DIV_OUT_ON);
642 */
643
644 /* diversity */
645 wr(DIB3000MC_REG_DIVERSITY1,DIB3000MC_DIVERSITY1_DEFAULT);
646 wr(DIB3000MC_REG_DIVERSITY2,DIB3000MC_DIVERSITY2_DEFAULT);
647
648 set_and(DIB3000MC_REG_DIVERSITY3,DIB3000MC_DIVERSITY3_IN_OFF);
649
650 set_or(DIB3000MC_REG_CLK_CFG_7,DIB3000MC_CLK_CFG_7_DIV_IN_OFF);
651
652 /* if (state->config->pll_init) {
653 dib3000mc_tuner_pass_ctrl(fe,1,state->config.pll_addr(fe));
654 state->config->pll_init(fe,NULL);
655 dib3000mc_tuner_pass_ctrl(fe,0,state->config.pll_addr(fe));
656 }*/
657 deb_info("init end\n");
658 return 0;
659 }
660 static int dib3000mc_read_status(struct dvb_frontend* fe, fe_status_t *stat)
661 {
662 struct dib3000_state* state = fe->demodulator_priv;
663 u16 lock = rd(DIB3000MC_REG_LOCKING);
664
665 *stat = 0;
666 if (DIB3000MC_AGC_LOCK(lock))
667 *stat |= FE_HAS_SIGNAL;
668 if (DIB3000MC_CARRIER_LOCK(lock))
669 *stat |= FE_HAS_CARRIER;
670 if (DIB3000MC_TPS_LOCK(lock))
671 *stat |= FE_HAS_VITERBI;
672 if (DIB3000MC_MPEG_SYNC_LOCK(lock))
673 *stat |= (FE_HAS_SYNC | FE_HAS_LOCK);
674
675 deb_stat("actual status is %2x fifo_level: %x,244: %x, 206: %x, 207: %x, 1040: %x\n",*stat,rd(510),rd(244),rd(206),rd(207),rd(1040));
676
677 return 0;
678 }
679
680 static int dib3000mc_read_ber(struct dvb_frontend* fe, u32 *ber)
681 {
682 struct dib3000_state* state = fe->demodulator_priv;
683 *ber = ((rd(DIB3000MC_REG_BER_MSB) << 16) | rd(DIB3000MC_REG_BER_LSB));
684 return 0;
685 }
686
687 static int dib3000mc_read_unc_blocks(struct dvb_frontend* fe, u32 *unc)
688 {
689 struct dib3000_state* state = fe->demodulator_priv;
690
691 *unc = rd(DIB3000MC_REG_PACKET_ERROR_COUNT);
692 return 0;
693 }
694
695 /* see dib3000mb.c for calculation comments */
696 static int dib3000mc_read_signal_strength(struct dvb_frontend* fe, u16 *strength)
697 {
698 struct dib3000_state* state = fe->demodulator_priv;
699 u16 val = rd(DIB3000MC_REG_SIGNAL_NOISE_LSB);
700 *strength = (((val >> 6) & 0xff) << 8) + (val & 0x3f);
701
702 deb_stat("signal: mantisse = %d, exponent = %d\n",(*strength >> 8) & 0xff, *strength & 0xff);
703 return 0;
704 }
705
706 /* see dib3000mb.c for calculation comments */
707 static int dib3000mc_read_snr(struct dvb_frontend* fe, u16 *snr)
708 {
709 struct dib3000_state* state = fe->demodulator_priv;
710 u16 val = rd(DIB3000MC_REG_SIGNAL_NOISE_LSB),
711 val2 = rd(DIB3000MC_REG_SIGNAL_NOISE_MSB);
712 u16 sig,noise;
713
714 sig = (((val >> 6) & 0xff) << 8) + (val & 0x3f);
715 noise = (((val >> 4) & 0xff) << 8) + ((val & 0xf) << 2) + ((val2 >> 14) & 0x3);
716 if (noise == 0)
717 *snr = 0xffff;
718 else
719 *snr = (u16) sig/noise;
720
721 deb_stat("signal: mantisse = %d, exponent = %d\n",(sig >> 8) & 0xff, sig & 0xff);
722 deb_stat("noise: mantisse = %d, exponent = %d\n",(noise >> 8) & 0xff, noise & 0xff);
723 deb_stat("snr: %d\n",*snr);
724 return 0;
725 }
726
727 static int dib3000mc_sleep(struct dvb_frontend* fe)
728 {
729 struct dib3000_state* state = fe->demodulator_priv;
730
731 set_or(DIB3000MC_REG_CLK_CFG_7,DIB3000MC_CLK_CFG_7_PWR_DOWN);
732 wr(DIB3000MC_REG_CLK_CFG_1,DIB3000MC_CLK_CFG_1_POWER_DOWN);
733 wr(DIB3000MC_REG_CLK_CFG_2,DIB3000MC_CLK_CFG_2_POWER_DOWN);
734 wr(DIB3000MC_REG_CLK_CFG_3,DIB3000MC_CLK_CFG_3_POWER_DOWN);
735 return 0;
736 }
737
738 static int dib3000mc_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
739 {
740 tune->min_delay_ms = 2000;
741 tune->step_size = 166667;
742 tune->max_drift = 166667 * 2;
743
744 return 0;
745 }
746
747 static int dib3000mc_fe_init_nonmobile(struct dvb_frontend* fe)
748 {
749 return dib3000mc_fe_init(fe, 0);
750 }
751
752 static int dib3000mc_set_frontend_and_tuner(struct dvb_frontend* fe, struct dvb_frontend_parameters *fep)
753 {
754 return dib3000mc_set_frontend(fe, fep, 1);
755 }
756
757 static void dib3000mc_release(struct dvb_frontend* fe)
758 {
759 struct dib3000_state *state = fe->demodulator_priv;
760 kfree(state);
761 }
762
763 /* pid filter and transfer stuff */
764 static int dib3000mc_pid_control(struct dvb_frontend *fe,int index, int pid,int onoff)
765 {
766 struct dib3000_state *state = fe->demodulator_priv;
767 pid = (onoff ? pid | DIB3000_ACTIVATE_PID_FILTERING : 0);
768 wr(index+DIB3000MC_REG_FIRST_PID,pid);
769 return 0;
770 }
771
772 static int dib3000mc_fifo_control(struct dvb_frontend *fe, int onoff)
773 {
774 struct dib3000_state *state = fe->demodulator_priv;
775 u16 tmp = rd(DIB3000MC_REG_SMO_MODE);
776
777 deb_xfer("%s fifo\n",onoff ? "enabling" : "disabling");
778
779 if (onoff) {
780 deb_xfer("%d %x\n",tmp & DIB3000MC_SMO_MODE_FIFO_UNFLUSH,tmp & DIB3000MC_SMO_MODE_FIFO_UNFLUSH);
781 wr(DIB3000MC_REG_SMO_MODE,tmp & DIB3000MC_SMO_MODE_FIFO_UNFLUSH);
782 } else {
783 deb_xfer("%d %x\n",tmp | DIB3000MC_SMO_MODE_FIFO_FLUSH,tmp | DIB3000MC_SMO_MODE_FIFO_FLUSH);
784 wr(DIB3000MC_REG_SMO_MODE,tmp | DIB3000MC_SMO_MODE_FIFO_FLUSH);
785 }
786 return 0;
787 }
788
789 static int dib3000mc_pid_parse(struct dvb_frontend *fe, int onoff)
790 {
791 struct dib3000_state *state = fe->demodulator_priv;
792 u16 tmp = rd(DIB3000MC_REG_SMO_MODE);
793
794 deb_xfer("%s pid parsing\n",onoff ? "enabling" : "disabling");
795
796 if (onoff) {
797 wr(DIB3000MC_REG_SMO_MODE,tmp | DIB3000MC_SMO_MODE_PID_PARSE);
798 } else {
799 wr(DIB3000MC_REG_SMO_MODE,tmp & DIB3000MC_SMO_MODE_NO_PID_PARSE);
800 }
801 return 0;
802 }
803
804 static int dib3000mc_tuner_pass_ctrl(struct dvb_frontend *fe, int onoff, u8 pll_addr)
805 {
806 struct dib3000_state *state = fe->demodulator_priv;
807 if (onoff) {
808 wr(DIB3000MC_REG_TUNER, DIB3000_TUNER_WRITE_ENABLE(pll_addr));
809 } else {
810 wr(DIB3000MC_REG_TUNER, DIB3000_TUNER_WRITE_DISABLE(pll_addr));
811 }
812 return 0;
813 }
814
815 static int dib3000mc_demod_init(struct dib3000_state *state)
816 {
817 u16 default_addr = 0x0a;
818 /* first init */
819 if (state->config.demod_address != default_addr) {
820 deb_info("initializing the demod the first time. Setting demod addr to 0x%x\n",default_addr);
821 wr(DIB3000MC_REG_ELEC_OUT,DIB3000MC_ELEC_OUT_DIV_OUT_ON);
822 wr(DIB3000MC_REG_OUTMODE,DIB3000MC_OM_PAR_CONT_CLK);
823
824 wr(DIB3000MC_REG_RST_I2C_ADDR,
825 DIB3000MC_DEMOD_ADDR(default_addr) |
826 DIB3000MC_DEMOD_ADDR_ON);
827
828 state->config.demod_address = default_addr;
829
830 wr(DIB3000MC_REG_RST_I2C_ADDR,
831 DIB3000MC_DEMOD_ADDR(default_addr));
832 } else
833 deb_info("demod is already initialized. Demod addr: 0x%x\n",state->config.demod_address);
834 return 0;
835 }
836
837
838 static struct dvb_frontend_ops dib3000mc_ops;
839
840 struct dvb_frontend* dib3000mc_attach(const struct dib3000_config* config,
841 struct i2c_adapter* i2c, struct dib_fe_xfer_ops *xfer_ops)
842 {
843 struct dib3000_state* state = NULL;
844 u16 devid;
845
846 /* allocate memory for the internal state */
847 state = kmalloc(sizeof(struct dib3000_state), GFP_KERNEL);
848 if (state == NULL)
849 goto error;
850 memset(state,0,sizeof(struct dib3000_state));
851
852 /* setup the state */
853 state->i2c = i2c;
854 memcpy(&state->config,config,sizeof(struct dib3000_config));
855 memcpy(&state->ops, &dib3000mc_ops, sizeof(struct dvb_frontend_ops));
856
857 /* check for the correct demod */
858 if (rd(DIB3000_REG_MANUFACTOR_ID) != DIB3000_I2C_ID_DIBCOM)
859 goto error;
860
861 devid = rd(DIB3000_REG_DEVICE_ID);
862 if (devid != DIB3000MC_DEVICE_ID && devid != DIB3000P_DEVICE_ID)
863 goto error;
864
865 switch (devid) {
866 case DIB3000MC_DEVICE_ID:
867 info("Found a DiBcom 3000M-C, interesting...");
868 break;
869 case DIB3000P_DEVICE_ID:
870 info("Found a DiBcom 3000P.");
871 break;
872 }
873
874 /* create dvb_frontend */
875 state->frontend.ops = &state->ops;
876 state->frontend.demodulator_priv = state;
877
878 /* set the xfer operations */
879 xfer_ops->pid_parse = dib3000mc_pid_parse;
880 xfer_ops->fifo_ctrl = dib3000mc_fifo_control;
881 xfer_ops->pid_ctrl = dib3000mc_pid_control;
882 xfer_ops->tuner_pass_ctrl = dib3000mc_tuner_pass_ctrl;
883
884 dib3000mc_demod_init(state);
885
886 return &state->frontend;
887
888 error:
889 kfree(state);
890 return NULL;
891 }
892
893 static struct dvb_frontend_ops dib3000mc_ops = {
894
895 .info = {
896 .name = "DiBcom 3000P/M-C DVB-T",
897 .type = FE_OFDM,
898 .frequency_min = 44250000,
899 .frequency_max = 867250000,
900 .frequency_stepsize = 62500,
901 .caps = FE_CAN_INVERSION_AUTO |
902 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
903 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
904 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
905 FE_CAN_TRANSMISSION_MODE_AUTO |
906 FE_CAN_GUARD_INTERVAL_AUTO |
907 FE_CAN_RECOVER |
908 FE_CAN_HIERARCHY_AUTO,
909 },
910
911 .release = dib3000mc_release,
912
913 .init = dib3000mc_fe_init_nonmobile,
914 .sleep = dib3000mc_sleep,
915
916 .set_frontend = dib3000mc_set_frontend_and_tuner,
917 .get_frontend = dib3000mc_get_frontend,
918 .get_tune_settings = dib3000mc_fe_get_tune_settings,
919
920 .read_status = dib3000mc_read_status,
921 .read_ber = dib3000mc_read_ber,
922 .read_signal_strength = dib3000mc_read_signal_strength,
923 .read_snr = dib3000mc_read_snr,
924 .read_ucblocks = dib3000mc_read_unc_blocks,
925 };
926
927 MODULE_AUTHOR(DRIVER_AUTHOR);
928 MODULE_DESCRIPTION(DRIVER_DESC);
929 MODULE_LICENSE("GPL");
930
931 EXPORT_SYMBOL(dib3000mc_attach);
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