include/asm-i386/mach-bigsmp/mach_apic.h

   1 #ifndef __ASM_MACH_APIC_H
   2 #define __ASM_MACH_APIC_H
   3 #include <asm/smp.h>
   4
   5 #define SEQUENTIAL_APICID
   6 #ifdef SEQUENTIAL_APICID
   7 #define xapic_phys_to_log_apicid(phys_apic) ( (1ul << ((phys_apic) & 0x3)) |\
   8                 ((phys_apic<<2) & (~0xf)) )
   9 #elif CLUSTERED_APICID
  10 #define xapic_phys_to_log_apicid(phys_apic) ( (1ul << ((phys_apic) & 0x3)) |\
  11                 ((phys_apic) & (~0xf)) )
  12 #endif
  13
  14 #define NO_BALANCE_IRQ (1)
  15 #define esr_disable (1)
  16
  17 #define NO_IOAPIC_CHECK (0)
  18
  19 static inline int apic_id_registered(void)
  20 {
  21         return (1);
  22 }
  23
  24 #define APIC_DFR_VALUE  (APIC_DFR_CLUSTER)
  25 /* Round robin the irqs amoung the online cpus */
  26 static inline cpumask_t target_cpus(void)
  27 {
  28         static unsigned long cpu = NR_CPUS;
  29         do {
  30                 if (cpu >= NR_CPUS)
  31                         cpu = first_cpu(cpu_online_map);
  32                 else
  33                         cpu = next_cpu(cpu, cpu_online_map);
  34         } while (cpu >= NR_CPUS);
  35         return cpumask_of_cpu(cpu);
  36 }
  37 #define TARGET_CPUS     (target_cpus())
  38
  39 #define INT_DELIVERY_MODE dest_Fixed
  40 #define INT_DEST_MODE 1     /* logical delivery broadcast to all procs */
  41
  42 static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
  43 {
  44         return 0;
  45 }
  46
  47 /* we don't use the phys_cpu_present_map to indicate apicid presence */
  48 static inline unsigned long check_apicid_present(int bit)
  49 {
  50         return 1;
  51 }
  52
  53 #define apicid_cluster(apicid) (apicid & 0xF0)
  54
  55 static inline unsigned long calculate_ldr(unsigned long old)
  56 {
  57         unsigned long id;
  58         id = xapic_phys_to_log_apicid(hard_smp_processor_id());
  59         return ((old & ~APIC_LDR_MASK) | SET_APIC_LOGICAL_ID(id));
  60 }
  61
  62 /*
  63  * Set up the logical destination ID.
  64  *
  65  * Intel recommends to set DFR, LDR and TPR before enabling
  66  * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
  67  * document number 292116).  So here it goes...
  68  */
  69 static inline void init_apic_ldr(void)
  70 {
  71         unsigned long val;
  72
  73         apic_write_around(APIC_DFR, APIC_DFR_VALUE);
  74         val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
  75         val = calculate_ldr(val);
  76         apic_write_around(APIC_LDR, val);
  77 }
  78
  79 static inline void clustered_apic_check(void)
  80 {
  81         printk("Enabling APIC mode:  %s.  Using %d I/O APICs\n",
  82                 "Cluster", nr_ioapics);
  83 }
  84
  85 static inline int multi_timer_check(int apic, int irq)
  86 {
  87         return 0;
  88 }
  89
  90 static inline int apicid_to_node(int logical_apicid)
  91 {
  92         return 0;
  93 }
  94
  95 extern u8 bios_cpu_apicid[];
  96
  97 static inline int cpu_present_to_apicid(int mps_cpu)
  98 {
  99         if (mps_cpu < NR_CPUS)
 100                 return (int)bios_cpu_apicid[mps_cpu];
 101         else
 102                 return BAD_APICID;
 103 }
 104
 105 static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
 106 {
 107         return physid_mask_of_physid(phys_apicid);
 108 }
 109
 110 extern u8 cpu_2_logical_apicid[];
 111 /* Mapping from cpu number to logical apicid */
 112 static inline int cpu_to_logical_apicid(int cpu)
 113 {
 114        if (cpu >= NR_CPUS)
 115                return BAD_APICID;
 116        return (int)cpu_2_logical_apicid[cpu];
 117  }
 118
 119 static inline int mpc_apic_id(struct mpc_config_processor *m,
 120                         struct mpc_config_translation *translation_record)
 121 {
 122         printk("Processor #%d %ld:%ld APIC version %d\n",
 123                 m->mpc_apicid,
 124                 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
 125                 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
 126                 m->mpc_apicver);
 127         return m->mpc_apicid;
 128 }
 129
 130 static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
 131 {
 132         /* For clustered we don't have a good way to do this yet - hack */
 133         return physids_promote(0xFUL);
 134 }
 135
 136 #define WAKE_SECONDARY_VIA_INIT
 137
 138 static inline void setup_portio_remap(void)
 139 {
 140 }
 141
 142 static inline void enable_apic_mode(void)
 143 {
 144 }
 145
 146 static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
 147 {
 148         return (1);
 149 }
 150
 151 /* As we are using single CPU as destination, pick only one CPU here */
 152 static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
 153 {
 154         int cpu;
 155         int apicid;
 156
 157         cpu = first_cpu(cpumask);
 158         apicid = cpu_to_logical_apicid(cpu);
 159         return apicid;
 160 }
 161
 162 static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
 163 {
 164         return cpuid_apic >> index_msb;
 165 }
 166
 167 #endif /* __ASM_MACH_APIC_H */