1 /* $Id: spitfire.h,v 1.18 2001/11/29 16:42:10 kanoj Exp $
2 * spitfire.h: SpitFire/BlackBird/Cheetah inline MMU operations.
4 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
7 #ifndef _SPARC64_SPITFIRE_H
8 #define _SPARC64_SPITFIRE_H
12 /* The following register addresses are accessible via ASI_DMMU
13 * and ASI_IMMU, that is there is a distinct and unique copy of
14 * each these registers for each TLB.
16 #define TSB_TAG_TARGET 0x0000000000000000 /* All chips */
17 #define TLB_SFSR 0x0000000000000018 /* All chips */
18 #define TSB_REG 0x0000000000000028 /* All chips */
19 #define TLB_TAG_ACCESS 0x0000000000000030 /* All chips */
20 #define VIRT_WATCHPOINT 0x0000000000000038 /* All chips */
21 #define PHYS_WATCHPOINT 0x0000000000000040 /* All chips */
22 #define TSB_EXTENSION_P 0x0000000000000048 /* Ultra-III and later */
23 #define TSB_EXTENSION_S 0x0000000000000050 /* Ultra-III and later, D-TLB only */
24 #define TSB_EXTENSION_N 0x0000000000000058 /* Ultra-III and later */
25 #define TLB_TAG_ACCESS_EXT 0x0000000000000060 /* Ultra-III+ and later */
27 /* These registers only exist as one entity, and are accessed
30 #define PRIMARY_CONTEXT 0x0000000000000008
31 #define SECONDARY_CONTEXT 0x0000000000000010
32 #define DMMU_SFAR 0x0000000000000020
33 #define VIRT_WATCHPOINT 0x0000000000000038
34 #define PHYS_WATCHPOINT 0x0000000000000040
36 #define SPITFIRE_HIGHEST_LOCKED_TLBENT (64 - 1)
37 #define CHEETAH_HIGHEST_LOCKED_TLBENT (16 - 1)
39 #define L1DCACHE_SIZE 0x4000
43 enum ultra_tlb_layout
{
49 extern enum ultra_tlb_layout tlb_type
;
51 #define sparc64_highest_locked_tlbent() \
52 (tlb_type == spitfire ? \
53 SPITFIRE_HIGHEST_LOCKED_TLBENT : \
54 CHEETAH_HIGHEST_LOCKED_TLBENT)
56 static __inline__
unsigned long spitfire_get_isfsr(void)
60 __asm__
__volatile__("ldxa [%1] %2, %0"
62 : "r" (TLB_SFSR
), "i" (ASI_IMMU
));
66 static __inline__
unsigned long spitfire_get_dsfsr(void)
70 __asm__
__volatile__("ldxa [%1] %2, %0"
72 : "r" (TLB_SFSR
), "i" (ASI_DMMU
));
76 static __inline__
unsigned long spitfire_get_sfar(void)
80 __asm__
__volatile__("ldxa [%1] %2, %0"
82 : "r" (DMMU_SFAR
), "i" (ASI_DMMU
));
86 static __inline__
void spitfire_put_isfsr(unsigned long sfsr
)
88 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
91 : "r" (sfsr
), "r" (TLB_SFSR
), "i" (ASI_IMMU
));
94 static __inline__
void spitfire_put_dsfsr(unsigned long sfsr
)
96 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
99 : "r" (sfsr
), "r" (TLB_SFSR
), "i" (ASI_DMMU
));
102 /* The data cache is write through, so this just invalidates the
105 static __inline__
void spitfire_put_dcache_tag(unsigned long addr
, unsigned long tag
)
107 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
110 : "r" (tag
), "r" (addr
), "i" (ASI_DCACHE_TAG
));
111 __asm__
__volatile__ ("membar #Sync" : : : "memory");
114 /* The instruction cache lines are flushed with this, but note that
115 * this does not flush the pipeline. It is possible for a line to
116 * get flushed but stale instructions to still be in the pipeline,
117 * a flush instruction (to any address) is sufficient to handle
118 * this issue after the line is invalidated.
120 static __inline__
void spitfire_put_icache_tag(unsigned long addr
, unsigned long tag
)
122 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
125 : "r" (tag
), "r" (addr
), "i" (ASI_IC_TAG
));
128 static __inline__
unsigned long spitfire_get_dtlb_data(int entry
)
132 __asm__
__volatile__("ldxa [%1] %2, %0"
134 : "r" (entry
<< 3), "i" (ASI_DTLB_DATA_ACCESS
));
136 /* Clear TTE diag bits. */
137 data
&= ~0x0003fe0000000000UL
;
142 static __inline__
unsigned long spitfire_get_dtlb_tag(int entry
)
146 __asm__
__volatile__("ldxa [%1] %2, %0"
148 : "r" (entry
<< 3), "i" (ASI_DTLB_TAG_READ
));
152 static __inline__
void spitfire_put_dtlb_data(int entry
, unsigned long data
)
154 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
157 : "r" (data
), "r" (entry
<< 3),
158 "i" (ASI_DTLB_DATA_ACCESS
));
161 static __inline__
unsigned long spitfire_get_itlb_data(int entry
)
165 __asm__
__volatile__("ldxa [%1] %2, %0"
167 : "r" (entry
<< 3), "i" (ASI_ITLB_DATA_ACCESS
));
169 /* Clear TTE diag bits. */
170 data
&= ~0x0003fe0000000000UL
;
175 static __inline__
unsigned long spitfire_get_itlb_tag(int entry
)
179 __asm__
__volatile__("ldxa [%1] %2, %0"
181 : "r" (entry
<< 3), "i" (ASI_ITLB_TAG_READ
));
185 static __inline__
void spitfire_put_itlb_data(int entry
, unsigned long data
)
187 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
190 : "r" (data
), "r" (entry
<< 3),
191 "i" (ASI_ITLB_DATA_ACCESS
));
194 /* Spitfire hardware assisted TLB flushes. */
196 /* Context level flushes. */
197 static __inline__
void spitfire_flush_dtlb_primary_context(void)
199 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
202 : "r" (0x40), "i" (ASI_DMMU_DEMAP
));
205 static __inline__
void spitfire_flush_itlb_primary_context(void)
207 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
210 : "r" (0x40), "i" (ASI_IMMU_DEMAP
));
213 static __inline__
void spitfire_flush_dtlb_secondary_context(void)
215 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
218 : "r" (0x50), "i" (ASI_DMMU_DEMAP
));
221 static __inline__
void spitfire_flush_itlb_secondary_context(void)
223 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
226 : "r" (0x50), "i" (ASI_IMMU_DEMAP
));
229 static __inline__
void spitfire_flush_dtlb_nucleus_context(void)
231 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
234 : "r" (0x60), "i" (ASI_DMMU_DEMAP
));
237 static __inline__
void spitfire_flush_itlb_nucleus_context(void)
239 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
242 : "r" (0x60), "i" (ASI_IMMU_DEMAP
));
245 /* Page level flushes. */
246 static __inline__
void spitfire_flush_dtlb_primary_page(unsigned long page
)
248 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
251 : "r" (page
), "i" (ASI_DMMU_DEMAP
));
254 static __inline__
void spitfire_flush_itlb_primary_page(unsigned long page
)
256 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
259 : "r" (page
), "i" (ASI_IMMU_DEMAP
));
262 static __inline__
void spitfire_flush_dtlb_secondary_page(unsigned long page
)
264 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
267 : "r" (page
| 0x10), "i" (ASI_DMMU_DEMAP
));
270 static __inline__
void spitfire_flush_itlb_secondary_page(unsigned long page
)
272 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
275 : "r" (page
| 0x10), "i" (ASI_IMMU_DEMAP
));
278 static __inline__
void spitfire_flush_dtlb_nucleus_page(unsigned long page
)
280 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
283 : "r" (page
| 0x20), "i" (ASI_DMMU_DEMAP
));
286 static __inline__
void spitfire_flush_itlb_nucleus_page(unsigned long page
)
288 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
291 : "r" (page
| 0x20), "i" (ASI_IMMU_DEMAP
));
294 /* Cheetah has "all non-locked" tlb flushes. */
295 static __inline__
void cheetah_flush_dtlb_all(void)
297 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
300 : "r" (0x80), "i" (ASI_DMMU_DEMAP
));
303 static __inline__
void cheetah_flush_itlb_all(void)
305 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
308 : "r" (0x80), "i" (ASI_IMMU_DEMAP
));
311 /* Cheetah has a 4-tlb layout so direct access is a bit different.
312 * The first two TLBs are fully assosciative, hold 16 entries, and are
313 * used only for locked and >8K sized translations. One exists for
314 * data accesses and one for instruction accesses.
316 * The third TLB is for data accesses to 8K non-locked translations, is
317 * 2 way assosciative, and holds 512 entries. The fourth TLB is for
318 * instruction accesses to 8K non-locked translations, is 2 way
319 * assosciative, and holds 128 entries.
321 * Cheetah has some bug where bogus data can be returned from
322 * ASI_{D,I}TLB_DATA_ACCESS loads, doing the load twice fixes
323 * the problem for me. -DaveM
325 static __inline__
unsigned long cheetah_get_ldtlb_data(int entry
)
329 __asm__
__volatile__("ldxa [%1] %2, %%g0\n\t"
332 : "r" ((0 << 16) | (entry
<< 3)),
333 "i" (ASI_DTLB_DATA_ACCESS
));
338 static __inline__
unsigned long cheetah_get_litlb_data(int entry
)
342 __asm__
__volatile__("ldxa [%1] %2, %%g0\n\t"
345 : "r" ((0 << 16) | (entry
<< 3)),
346 "i" (ASI_ITLB_DATA_ACCESS
));
351 static __inline__
unsigned long cheetah_get_ldtlb_tag(int entry
)
355 __asm__
__volatile__("ldxa [%1] %2, %0"
357 : "r" ((0 << 16) | (entry
<< 3)),
358 "i" (ASI_DTLB_TAG_READ
));
363 static __inline__
unsigned long cheetah_get_litlb_tag(int entry
)
367 __asm__
__volatile__("ldxa [%1] %2, %0"
369 : "r" ((0 << 16) | (entry
<< 3)),
370 "i" (ASI_ITLB_TAG_READ
));
375 static __inline__
void cheetah_put_ldtlb_data(int entry
, unsigned long data
)
377 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
381 "r" ((0 << 16) | (entry
<< 3)),
382 "i" (ASI_DTLB_DATA_ACCESS
));
385 static __inline__
void cheetah_put_litlb_data(int entry
, unsigned long data
)
387 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
391 "r" ((0 << 16) | (entry
<< 3)),
392 "i" (ASI_ITLB_DATA_ACCESS
));
395 static __inline__
unsigned long cheetah_get_dtlb_data(int entry
, int tlb
)
399 __asm__
__volatile__("ldxa [%1] %2, %%g0\n\t"
402 : "r" ((tlb
<< 16) | (entry
<< 3)), "i" (ASI_DTLB_DATA_ACCESS
));
407 static __inline__
unsigned long cheetah_get_dtlb_tag(int entry
, int tlb
)
411 __asm__
__volatile__("ldxa [%1] %2, %0"
413 : "r" ((tlb
<< 16) | (entry
<< 3)), "i" (ASI_DTLB_TAG_READ
));
417 static __inline__
void cheetah_put_dtlb_data(int entry
, unsigned long data
, int tlb
)
419 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
423 "r" ((tlb
<< 16) | (entry
<< 3)),
424 "i" (ASI_DTLB_DATA_ACCESS
));
427 static __inline__
unsigned long cheetah_get_itlb_data(int entry
)
431 __asm__
__volatile__("ldxa [%1] %2, %%g0\n\t"
434 : "r" ((2 << 16) | (entry
<< 3)),
435 "i" (ASI_ITLB_DATA_ACCESS
));
440 static __inline__
unsigned long cheetah_get_itlb_tag(int entry
)
444 __asm__
__volatile__("ldxa [%1] %2, %0"
446 : "r" ((2 << 16) | (entry
<< 3)), "i" (ASI_ITLB_TAG_READ
));
450 static __inline__
void cheetah_put_itlb_data(int entry
, unsigned long data
)
452 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
455 : "r" (data
), "r" ((2 << 16) | (entry
<< 3)),
456 "i" (ASI_ITLB_DATA_ACCESS
));
459 #endif /* !(__ASSEMBLY__) */
461 #endif /* !(_SPARC64_SPITFIRE_H) */