arch/arm/mach-lh7a40x/irq-lh7a404.c

   1 /* arch/arm/mach-lh7a40x/irq-lh7a404.c
   2  *
   3  *  Copyright (C) 2004 Logic Product Development
   4  *
   5  *  This program is free software; you can redistribute it and/or
   6  *  modify it under the terms of the GNU General Public License
   7  *  version 2 as published by the Free Software Foundation.
   8  *
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/module.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/ptrace.h>
  15
  16 #include <asm/hardware.h>
  17 #include <asm/irq.h>
  18 #include <asm/mach/irq.h>
  19 #include <asm/arch/irqs.h>
  20
  21 #include "common.h"
  22
  23 #define USE_PRIORITIES
  24
  25 /* See Documentation/arm/Sharp-LH/VectoredInterruptController for more
  26  * information on using the vectored interrupt controller's
  27  * prioritizing feature. */
  28
  29 static unsigned char irq_pri_vic1[] = {
  30 #if defined (USE_PRIORITIES)
  31         IRQ_GPIO3INTR,                  /* CPLD */
  32         IRQ_DMAM2P4, IRQ_DMAM2P5,       /* AC97 */
  33 #endif
  34 };
  35 static unsigned char irq_pri_vic2[] = {
  36 #if defined (USE_PRIORITIES)
  37         IRQ_T3UI,                       /* Timer */
  38         IRQ_GPIO7INTR,                  /* CPLD */
  39         IRQ_UART1INTR, IRQ_UART2INTR, IRQ_UART3INTR,
  40         IRQ_LCDINTR,                    /* LCD */
  41         IRQ_TSCINTR,                    /* ADC/Touchscreen */
  42 #endif
  43 };
  44
  45   /* CPU IRQ handling */
  46
  47 static void lh7a404_vic1_mask_irq (u32 irq)
  48 {
  49         VIC1_INTENCLR = (1 << irq);
  50 }
  51
  52 static void lh7a404_vic1_unmask_irq (u32 irq)
  53 {
  54         VIC1_INTEN = (1 << irq);
  55 }
  56
  57 static void lh7a404_vic2_mask_irq (u32 irq)
  58 {
  59         VIC2_INTENCLR = (1 << (irq - 32));
  60 }
  61
  62 static void lh7a404_vic2_unmask_irq (u32 irq)
  63 {
  64         VIC2_INTEN = (1 << (irq - 32));
  65 }
  66
  67 static void lh7a404_vic1_ack_gpio_irq (u32 irq)
  68 {
  69         GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (irq));
  70         VIC1_INTENCLR = (1 << irq);
  71 }
  72
  73 static void lh7a404_vic2_ack_gpio_irq (u32 irq)
  74 {
  75         GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (irq));
  76         VIC2_INTENCLR = (1 << irq);
  77 }
  78
  79 static struct irqchip lh7a404_vic1_chip = {
  80         .ack    = lh7a404_vic1_mask_irq, /* Because level-triggered */
  81         .mask   = lh7a404_vic1_mask_irq,
  82         .unmask = lh7a404_vic1_unmask_irq,
  83 };
  84
  85 static struct irqchip lh7a404_vic2_chip = {
  86         .ack    = lh7a404_vic2_mask_irq, /* Because level-triggered */
  87         .mask   = lh7a404_vic2_mask_irq,
  88         .unmask = lh7a404_vic2_unmask_irq,
  89 };
  90
  91 static struct irqchip lh7a404_gpio_vic1_chip = {
  92         .ack    = lh7a404_vic1_ack_gpio_irq,
  93         .mask   = lh7a404_vic1_mask_irq,
  94         .unmask = lh7a404_vic1_unmask_irq,
  95 };
  96
  97 static struct irqchip lh7a404_gpio_vic2_chip = {
  98         .ack    = lh7a404_vic2_ack_gpio_irq,
  99         .mask   = lh7a404_vic2_mask_irq,
 100         .unmask = lh7a404_vic2_unmask_irq,
 101 };
 102
 103   /* IRQ initialization */
 104
 105 #if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
 106 extern void* branch_irq_lh7a400;
 107 #endif
 108
 109 void __init lh7a404_init_irq (void)
 110 {
 111         int irq;
 112
 113 #if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
 114 #define NOP 0xe1a00000                  /* mov r0, r0 */
 115         branch_irq_lh7a400 = NOP;
 116 #endif
 117
 118         VIC1_INTENCLR = 0xffffffff;
 119         VIC2_INTENCLR = 0xffffffff;
 120         VIC1_INTSEL = 0;                /* All IRQs */
 121         VIC2_INTSEL = 0;                /* All IRQs */
 122         VIC1_NVADDR = VA_VIC1DEFAULT;
 123         VIC2_NVADDR = VA_VIC2DEFAULT;
 124         VIC1_VECTADDR = 0;
 125         VIC2_VECTADDR = 0;
 126
 127         GPIO_GPIOFINTEN = 0x00;         /* Disable all GPIOF interrupts */
 128         barrier ();
 129
 130                 /* Install prioritized interrupts, if there are any. */
 131                 /* The | 0x20*/
 132         for (irq = 0; irq < 16; ++irq) {
 133                 (&VIC1_VAD0)[irq]
 134                         = (irq < ARRAY_SIZE (irq_pri_vic1))
 135                         ? (irq_pri_vic1[irq] | VA_VECTORED) : 0;
 136                 (&VIC1_VECTCNTL0)[irq]
 137                         = (irq < ARRAY_SIZE (irq_pri_vic1))
 138                         ? (irq_pri_vic1[irq] | VIC_CNTL_ENABLE) : 0;
 139                 (&VIC2_VAD0)[irq]
 140                         = (irq < ARRAY_SIZE (irq_pri_vic2))
 141                         ? (irq_pri_vic2[irq] | VA_VECTORED) : 0;
 142                 (&VIC2_VECTCNTL0)[irq]
 143                         = (irq < ARRAY_SIZE (irq_pri_vic2))
 144                         ? (irq_pri_vic2[irq] | VIC_CNTL_ENABLE) : 0;
 145         }
 146
 147         for (irq = 0; irq < NR_IRQS; ++irq) {
 148                 switch (irq) {
 149                 case IRQ_GPIO0INTR:
 150                 case IRQ_GPIO1INTR:
 151                 case IRQ_GPIO2INTR:
 152                 case IRQ_GPIO3INTR:
 153                 case IRQ_GPIO4INTR:
 154                 case IRQ_GPIO5INTR:
 155                 case IRQ_GPIO6INTR:
 156                 case IRQ_GPIO7INTR:
 157                         set_irq_chip (irq, irq < 32
 158                                       ? &lh7a404_gpio_vic1_chip
 159                                       : &lh7a404_gpio_vic2_chip);
 160                         set_irq_handler (irq, do_level_IRQ); /* OK default */
 161                         break;
 162                 default:
 163                         set_irq_chip (irq, irq < 32
 164                                       ? &lh7a404_vic1_chip
 165                                       : &lh7a404_vic2_chip);
 166                         set_irq_handler (irq, do_level_IRQ);
 167                 }
 168                 set_irq_flags (irq, IRQF_VALID);
 169         }
 170
 171         lh7a40x_init_board_irq ();
 172 }