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[PATCH] w1: Userspace communication protocol over connector.
[linux-2.6/verdex.git] / arch / sparc64 / kernel / pci_schizo.c
blobcc662e915d325dbbf2f11601d9f08bd2d560cd0d
1 /* $Id: pci_schizo.c,v 1.24 2002/01/23 11:27:32 davem Exp $
2 * pci_schizo.c: SCHIZO/TOMATILLO specific PCI controller support.
3 *
4 * Copyright (C) 2001, 2002, 2003 David S. Miller (davem@redhat.com)
5 */
6
7 #include <linux/kernel.h>
8 #include <linux/types.h>
9 #include <linux/pci.h>
10 #include <linux/init.h>
11 #include <linux/slab.h>
12 #include <linux/interrupt.h>
13
14 #include <asm/pbm.h>
15 #include <asm/iommu.h>
16 #include <asm/irq.h>
17 #include <asm/upa.h>
18 #include <asm/pstate.h>
19
20 #include "pci_impl.h"
21 #include "iommu_common.h"
22
23 /* All SCHIZO registers are 64-bits. The following accessor
24 * routines are how they are accessed. The REG parameter
25 * is a physical address.
26 */
27 #define schizo_read(__reg) \
28 ({ u64 __ret; \
29 __asm__ __volatile__("ldxa [%1] %2, %0" \
30 : "=r" (__ret) \
31 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
32 : "memory"); \
33 __ret; \
34 })
35 #define schizo_write(__reg, __val) \
36 __asm__ __volatile__("stxa %0, [%1] %2" \
37 : /* no outputs */ \
38 : "r" (__val), "r" (__reg), \
39 "i" (ASI_PHYS_BYPASS_EC_E) \
40 : "memory")
41
42 /* This is a convention that at least Excalibur and Merlin
43 * follow. I suppose the SCHIZO used in Starcat and friends
44 * will do similar.
45 *
46 * The only way I could see this changing is if the newlink
47 * block requires more space in Schizo's address space than
48 * they predicted, thus requiring an address space reorg when
49 * the newer Schizo is taped out.
50 */
51
52 /* Streaming buffer control register. */
53 #define SCHIZO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
54 #define SCHIZO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
55 #define SCHIZO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
56 #define SCHIZO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
57 #define SCHIZO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
58
59 /* IOMMU control register. */
60 #define SCHIZO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
61 #define SCHIZO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
62 #define SCHIZO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
63 #define SCHIZO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
64 #define SCHIZO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
65 #define SCHIZO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
66 #define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
67 #define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
68 #define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
69 #define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
70 #define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
71 #define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
72 #define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
73 #define SCHIZO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
74 #define SCHIZO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
75 #define SCHIZO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
76 #define SCHIZO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
77 #define SCHIZO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
78
79 /* Schizo config space address format is nearly identical to
80 * that of PSYCHO:
81 *
82 * 32 24 23 16 15 11 10 8 7 2 1 0
83 * ---------------------------------------------------------
84 * |0 0 0 0 0 0 0 0 0| bus | device | function | reg | 0 0 |
85 * ---------------------------------------------------------
86 */
87 #define SCHIZO_CONFIG_BASE(PBM) ((PBM)->config_space)
88 #define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \
89 (((unsigned long)(BUS) << 16) | \
90 ((unsigned long)(DEVFN) << 8) | \
91 ((unsigned long)(REG)))
92
93 static void *schizo_pci_config_mkaddr(struct pci_pbm_info *pbm,
94 unsigned char bus,
95 unsigned int devfn,
96 int where)
97 {
98 if (!pbm)
99 return NULL;
100 bus -= pbm->pci_first_busno;
101 return (void *)
102 (SCHIZO_CONFIG_BASE(pbm) |
103 SCHIZO_CONFIG_ENCODE(bus, devfn, where));
104 }
105
106 /* Just make sure the bus number is in range. */
107 static int schizo_out_of_range(struct pci_pbm_info *pbm,
108 unsigned char bus,
109 unsigned char devfn)
110 {
111 if (bus < pbm->pci_first_busno ||
112 bus > pbm->pci_last_busno)
113 return 1;
114 return 0;
115 }
116
117 /* SCHIZO PCI configuration space accessors. */
118
119 static int schizo_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
120 int where, int size, u32 *value)
121 {
122 struct pci_pbm_info *pbm = bus_dev->sysdata;
123 unsigned char bus = bus_dev->number;
124 u32 *addr;
125 u16 tmp16;
126 u8 tmp8;
127
128 switch (size) {
129 case 1:
130 *value = 0xff;
131 break;
132 case 2:
133 *value = 0xffff;
134 break;
135 case 4:
136 *value = 0xffffffff;
137 break;
138 }
139
140 addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where);
141 if (!addr)
142 return PCIBIOS_SUCCESSFUL;
143
144 if (schizo_out_of_range(pbm, bus, devfn))
145 return PCIBIOS_SUCCESSFUL;
146 switch (size) {
147 case 1:
148 pci_config_read8((u8 *)addr, &tmp8);
149 *value = tmp8;
150 break;
151
152 case 2:
153 if (where & 0x01) {
154 printk("pci_read_config_word: misaligned reg [%x]\n",
155 where);
156 return PCIBIOS_SUCCESSFUL;
157 }
158 pci_config_read16((u16 *)addr, &tmp16);
159 *value = tmp16;
160 break;
161
162 case 4:
163 if (where & 0x03) {
164 printk("pci_read_config_dword: misaligned reg [%x]\n",
165 where);
166 return PCIBIOS_SUCCESSFUL;
167 }
168 pci_config_read32(addr, value);
169 break;
170 }
171 return PCIBIOS_SUCCESSFUL;
172 }
173
174 static int schizo_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
175 int where, int size, u32 value)
176 {
177 struct pci_pbm_info *pbm = bus_dev->sysdata;
178 unsigned char bus = bus_dev->number;
179 u32 *addr;
180
181 addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where);
182 if (!addr)
183 return PCIBIOS_SUCCESSFUL;
184
185 if (schizo_out_of_range(pbm, bus, devfn))
186 return PCIBIOS_SUCCESSFUL;
187
188 switch (size) {
189 case 1:
190 pci_config_write8((u8 *)addr, value);
191 break;
192
193 case 2:
194 if (where & 0x01) {
195 printk("pci_write_config_word: misaligned reg [%x]\n",
196 where);
197 return PCIBIOS_SUCCESSFUL;
198 }
199 pci_config_write16((u16 *)addr, value);
200 break;
201
202 case 4:
203 if (where & 0x03) {
204 printk("pci_write_config_dword: misaligned reg [%x]\n",
205 where);
206 return PCIBIOS_SUCCESSFUL;
207 }
208
209 pci_config_write32(addr, value);
210 }
211 return PCIBIOS_SUCCESSFUL;
212 }
213
214 static struct pci_ops schizo_ops = {
215 .read = schizo_read_pci_cfg,
216 .write = schizo_write_pci_cfg,
217 };
218
219 /* SCHIZO interrupt mapping support. Unlike Psycho, for this controller the
220 * imap/iclr registers are per-PBM.
221 */
222 #define SCHIZO_IMAP_BASE 0x1000UL
223 #define SCHIZO_ICLR_BASE 0x1400UL
224
225 static unsigned long schizo_imap_offset(unsigned long ino)
226 {
227 return SCHIZO_IMAP_BASE + (ino * 8UL);
228 }
229
230 static unsigned long schizo_iclr_offset(unsigned long ino)
231 {
232 return SCHIZO_ICLR_BASE + (ino * 8UL);
233 }
234
235 static void tomatillo_wsync_handler(unsigned int ino, void *_arg1, void *_arg2)
236 {
237 unsigned long sync_reg = (unsigned long) _arg2;
238 u64 mask = 1UL << (ino & IMAP_INO);
239 u64 val;
240 int limit;
241
242 schizo_write(sync_reg, mask);
243
244 limit = 100000;
245 val = 0;
246 while (--limit) {
247 val = schizo_read(sync_reg);
248 if (!(val & mask))
249 break;
250 }
251 if (limit <= 0) {
252 printk("tomatillo_wsync_handler: DMA won't sync [%lx:%lx]\n",
253 val, mask);
254 }
255
256 if (_arg1) {
257 static unsigned char cacheline[64]
258 __attribute__ ((aligned (64)));
259
260 __asm__ __volatile__("rd %%fprs, %0\n\t"
261 "or %0, %4, %1\n\t"
262 "wr %1, 0x0, %%fprs\n\t"
263 "stda %%f0, [%5] %6\n\t"
264 "wr %0, 0x0, %%fprs\n\t"
265 "membar #Sync"
266 : "=&r" (mask), "=&r" (val)
267 : "0" (mask), "1" (val),
268 "i" (FPRS_FEF), "r" (&cacheline[0]),
269 "i" (ASI_BLK_COMMIT_P));
270 }
271 }
272
273 static unsigned long schizo_ino_to_iclr(struct pci_pbm_info *pbm,
274 unsigned int ino)
275 {
276 ino &= PCI_IRQ_INO;
277 return pbm->pbm_regs + schizo_iclr_offset(ino) + 4;
278 }
279
280 static unsigned long schizo_ino_to_imap(struct pci_pbm_info *pbm,
281 unsigned int ino)
282 {
283 ino &= PCI_IRQ_INO;
284 return pbm->pbm_regs + schizo_imap_offset(ino) + 4;
285 }
286
287 static unsigned int schizo_irq_build(struct pci_pbm_info *pbm,
288 struct pci_dev *pdev,
289 unsigned int ino)
290 {
291 unsigned long imap, iclr;
292 int ign_fixup;
293 int virt_irq;
294
295 ino &= PCI_IRQ_INO;
296
297 /* Now build the IRQ bucket. */
298 imap = schizo_ino_to_imap(pbm, ino);
299 iclr = schizo_ino_to_iclr(pbm, ino);
300
301 /* On Schizo, no inofixup occurs. This is because each
302 * INO has it's own IMAP register. On Psycho and Sabre
303 * there is only one IMAP register for each PCI slot even
304 * though four different INOs can be generated by each
305 * PCI slot.
306 *
307 * But, for JBUS variants (essentially, Tomatillo), we have
308 * to fixup the lowest bit of the interrupt group number.
309 */
310 ign_fixup = 0;
311 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
312 if (pbm->portid & 1)
313 ign_fixup = (1 << 6);
314 }
315
316 virt_irq = build_irq(ign_fixup, iclr, imap);
317
318 if (pdev && pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
319 irq_install_pre_handler(virt_irq,
320 tomatillo_wsync_handler,
321 ((pbm->chip_version <= 4) ?
322 (void *) 1 : (void *) 0),
323 (void *) pbm->sync_reg);
324 }
325
326 return virt_irq;
327 }
328
329 /* SCHIZO error handling support. */
330 enum schizo_error_type {
331 UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR
332 };
333
334 static DEFINE_SPINLOCK(stc_buf_lock);
335 static unsigned long stc_error_buf[128];
336 static unsigned long stc_tag_buf[16];
337 static unsigned long stc_line_buf[16];
338
339 #define SCHIZO_UE_INO 0x30 /* Uncorrectable ECC error */
340 #define SCHIZO_CE_INO 0x31 /* Correctable ECC error */
341 #define SCHIZO_PCIERR_A_INO 0x32 /* PBM A PCI bus error */
342 #define SCHIZO_PCIERR_B_INO 0x33 /* PBM B PCI bus error */
343 #define SCHIZO_SERR_INO 0x34 /* Safari interface error */
344
345 struct pci_pbm_info *pbm_for_ino(struct pci_controller_info *p, u32 ino)
346 {
347 ino &= IMAP_INO;
348 if (p->pbm_A.ino_bitmap & (1UL << ino))
349 return &p->pbm_A;
350 if (p->pbm_B.ino_bitmap & (1UL << ino))
351 return &p->pbm_B;
352
353 printk("PCI%d: No ino_bitmap entry for ino[%x], bitmaps "
354 "PBM_A[%016lx] PBM_B[%016lx]",
355 p->index, ino,
356 p->pbm_A.ino_bitmap,
357 p->pbm_B.ino_bitmap);
358 printk("PCI%d: Using PBM_A, report this problem immediately.\n",
359 p->index);
360
361 return &p->pbm_A;
362 }
363
364 static void schizo_clear_other_err_intr(struct pci_controller_info *p, int irq)
365 {
366 struct pci_pbm_info *pbm;
367 unsigned long iclr;
368
369 /* Do not clear the interrupt for the other PCI bus.
370 *
371 * This "ACK both PBM IRQs" only needs to be performed
372 * for chip-wide error interrupts.
373 */
374 if ((irq & IMAP_INO) == SCHIZO_PCIERR_A_INO ||
375 (irq & IMAP_INO) == SCHIZO_PCIERR_B_INO)
376 return;
377
378 pbm = pbm_for_ino(p, irq);
379 if (pbm == &p->pbm_A)
380 pbm = &p->pbm_B;
381 else
382 pbm = &p->pbm_A;
383
384 schizo_irq_build(pbm, NULL,
385 (pbm->portid << 6) | (irq & IMAP_INO));
386
387 iclr = schizo_ino_to_iclr(pbm,
388 (pbm->portid << 6) | (irq & IMAP_INO));
389 upa_writel(ICLR_IDLE, iclr);
390 }
391
392 #define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00 */
393 #define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80 */
394 #define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */
395
396 #define SCHIZO_STCERR_WRITE 0x2UL
397 #define SCHIZO_STCERR_READ 0x1UL
398
399 #define SCHIZO_STCTAG_PPN 0x3fffffff00000000UL
400 #define SCHIZO_STCTAG_VPN 0x00000000ffffe000UL
401 #define SCHIZO_STCTAG_VALID 0x8000000000000000UL
402 #define SCHIZO_STCTAG_READ 0x4000000000000000UL
403
404 #define SCHIZO_STCLINE_LINDX 0x0000000007800000UL
405 #define SCHIZO_STCLINE_SPTR 0x000000000007e000UL
406 #define SCHIZO_STCLINE_LADDR 0x0000000000001fc0UL
407 #define SCHIZO_STCLINE_EPTR 0x000000000000003fUL
408 #define SCHIZO_STCLINE_VALID 0x0000000000600000UL
409 #define SCHIZO_STCLINE_FOFN 0x0000000000180000UL
410
411 static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm,
412 enum schizo_error_type type)
413 {
414 struct pci_strbuf *strbuf = &pbm->stc;
415 unsigned long regbase = pbm->pbm_regs;
416 unsigned long err_base, tag_base, line_base;
417 u64 control;
418 int i;
419
420 err_base = regbase + SCHIZO_STC_ERR;
421 tag_base = regbase + SCHIZO_STC_TAG;
422 line_base = regbase + SCHIZO_STC_LINE;
423
424 spin_lock(&stc_buf_lock);
425
426 /* This is __REALLY__ dangerous. When we put the
427 * streaming buffer into diagnostic mode to probe
428 * it's tags and error status, we _must_ clear all
429 * of the line tag valid bits before re-enabling
430 * the streaming buffer. If any dirty data lives
431 * in the STC when we do this, we will end up
432 * invalidating it before it has a chance to reach
433 * main memory.
434 */
435 control = schizo_read(strbuf->strbuf_control);
436 schizo_write(strbuf->strbuf_control,
437 (control | SCHIZO_STRBUF_CTRL_DENAB));
438 for (i = 0; i < 128; i++) {
439 unsigned long val;
440
441 val = schizo_read(err_base + (i * 8UL));
442 schizo_write(err_base + (i * 8UL), 0UL);
443 stc_error_buf[i] = val;
444 }
445 for (i = 0; i < 16; i++) {
446 stc_tag_buf[i] = schizo_read(tag_base + (i * 8UL));
447 stc_line_buf[i] = schizo_read(line_base + (i * 8UL));
448 schizo_write(tag_base + (i * 8UL), 0UL);
449 schizo_write(line_base + (i * 8UL), 0UL);
450 }
451
452 /* OK, state is logged, exit diagnostic mode. */
453 schizo_write(strbuf->strbuf_control, control);
454
455 for (i = 0; i < 16; i++) {
456 int j, saw_error, first, last;
457
458 saw_error = 0;
459 first = i * 8;
460 last = first + 8;
461 for (j = first; j < last; j++) {
462 unsigned long errval = stc_error_buf[j];
463 if (errval != 0) {
464 saw_error++;
465 printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n",
466 pbm->name,
467 j,
468 (errval & SCHIZO_STCERR_WRITE) ? 1 : 0,
469 (errval & SCHIZO_STCERR_READ) ? 1 : 0);
470 }
471 }
472 if (saw_error != 0) {
473 unsigned long tagval = stc_tag_buf[i];
474 unsigned long lineval = stc_line_buf[i];
475 printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)R(%d)]\n",
476 pbm->name,
477 i,
478 ((tagval & SCHIZO_STCTAG_PPN) >> 19UL),
479 (tagval & SCHIZO_STCTAG_VPN),
480 ((tagval & SCHIZO_STCTAG_VALID) ? 1 : 0),
481 ((tagval & SCHIZO_STCTAG_READ) ? 1 : 0));
482
483 /* XXX Should spit out per-bank error information... -DaveM */
484 printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
485 "V(%d)FOFN(%d)]\n",
486 pbm->name,
487 i,
488 ((lineval & SCHIZO_STCLINE_LINDX) >> 23UL),
489 ((lineval & SCHIZO_STCLINE_SPTR) >> 13UL),
490 ((lineval & SCHIZO_STCLINE_LADDR) >> 6UL),
491 ((lineval & SCHIZO_STCLINE_EPTR) >> 0UL),
492 ((lineval & SCHIZO_STCLINE_VALID) ? 1 : 0),
493 ((lineval & SCHIZO_STCLINE_FOFN) ? 1 : 0));
494 }
495 }
496
497 spin_unlock(&stc_buf_lock);
498 }
499
500 /* IOMMU is per-PBM in Schizo, so interrogate both for anonymous
501 * controller level errors.
502 */
503
504 #define SCHIZO_IOMMU_TAG 0xa580UL
505 #define SCHIZO_IOMMU_DATA 0xa600UL
506
507 #define SCHIZO_IOMMU_TAG_CTXT 0x0000001ffe000000UL
508 #define SCHIZO_IOMMU_TAG_ERRSTS 0x0000000001800000UL
509 #define SCHIZO_IOMMU_TAG_ERR 0x0000000000400000UL
510 #define SCHIZO_IOMMU_TAG_WRITE 0x0000000000200000UL
511 #define SCHIZO_IOMMU_TAG_STREAM 0x0000000000100000UL
512 #define SCHIZO_IOMMU_TAG_SIZE 0x0000000000080000UL
513 #define SCHIZO_IOMMU_TAG_VPAGE 0x000000000007ffffUL
514
515 #define SCHIZO_IOMMU_DATA_VALID 0x0000000100000000UL
516 #define SCHIZO_IOMMU_DATA_CACHE 0x0000000040000000UL
517 #define SCHIZO_IOMMU_DATA_PPAGE 0x000000003fffffffUL
518
519 static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm,
520 enum schizo_error_type type)
521 {
522 struct pci_iommu *iommu = pbm->iommu;
523 unsigned long iommu_tag[16];
524 unsigned long iommu_data[16];
525 unsigned long flags;
526 u64 control;
527 int i;
528
529 spin_lock_irqsave(&iommu->lock, flags);
530 control = schizo_read(iommu->iommu_control);
531 if (control & SCHIZO_IOMMU_CTRL_XLTEERR) {
532 unsigned long base;
533 char *type_string;
534
535 /* Clear the error encountered bit. */
536 control &= ~SCHIZO_IOMMU_CTRL_XLTEERR;
537 schizo_write(iommu->iommu_control, control);
538
539 switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
540 case 0:
541 type_string = "Protection Error";
542 break;
543 case 1:
544 type_string = "Invalid Error";
545 break;
546 case 2:
547 type_string = "TimeOut Error";
548 break;
549 case 3:
550 default:
551 type_string = "ECC Error";
552 break;
553 };
554 printk("%s: IOMMU Error, type[%s]\n",
555 pbm->name, type_string);
556
557 /* Put the IOMMU into diagnostic mode and probe
558 * it's TLB for entries with error status.
559 *
560 * It is very possible for another DVMA to occur
561 * while we do this probe, and corrupt the system
562 * further. But we are so screwed at this point
563 * that we are likely to crash hard anyways, so
564 * get as much diagnostic information to the
565 * console as we can.
566 */
567 schizo_write(iommu->iommu_control,
568 control | SCHIZO_IOMMU_CTRL_DENAB);
569
570 base = pbm->pbm_regs;
571
572 for (i = 0; i < 16; i++) {
573 iommu_tag[i] =
574 schizo_read(base + SCHIZO_IOMMU_TAG + (i * 8UL));
575 iommu_data[i] =
576 schizo_read(base + SCHIZO_IOMMU_DATA + (i * 8UL));
577
578 /* Now clear out the entry. */
579 schizo_write(base + SCHIZO_IOMMU_TAG + (i * 8UL), 0);
580 schizo_write(base + SCHIZO_IOMMU_DATA + (i * 8UL), 0);
581 }
582
583 /* Leave diagnostic mode. */
584 schizo_write(iommu->iommu_control, control);
585
586 for (i = 0; i < 16; i++) {
587 unsigned long tag, data;
588
589 tag = iommu_tag[i];
590 if (!(tag & SCHIZO_IOMMU_TAG_ERR))
591 continue;
592
593 data = iommu_data[i];
594 switch((tag & SCHIZO_IOMMU_TAG_ERRSTS) >> 23UL) {
595 case 0:
596 type_string = "Protection Error";
597 break;
598 case 1:
599 type_string = "Invalid Error";
600 break;
601 case 2:
602 type_string = "TimeOut Error";
603 break;
604 case 3:
605 default:
606 type_string = "ECC Error";
607 break;
608 };
609 printk("%s: IOMMU TAG(%d)[error(%s) ctx(%x) wr(%d) str(%d) "
610 "sz(%dK) vpg(%08lx)]\n",
611 pbm->name, i, type_string,
612 (int)((tag & SCHIZO_IOMMU_TAG_CTXT) >> 25UL),
613 ((tag & SCHIZO_IOMMU_TAG_WRITE) ? 1 : 0),
614 ((tag & SCHIZO_IOMMU_TAG_STREAM) ? 1 : 0),
615 ((tag & SCHIZO_IOMMU_TAG_SIZE) ? 64 : 8),
616 (tag & SCHIZO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
617 printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
618 pbm->name, i,
619 ((data & SCHIZO_IOMMU_DATA_VALID) ? 1 : 0),
620 ((data & SCHIZO_IOMMU_DATA_CACHE) ? 1 : 0),
621 (data & SCHIZO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
622 }
623 }
624 if (pbm->stc.strbuf_enabled)
625 __schizo_check_stc_error_pbm(pbm, type);
626 spin_unlock_irqrestore(&iommu->lock, flags);
627 }
628
629 static void schizo_check_iommu_error(struct pci_controller_info *p,
630 enum schizo_error_type type)
631 {
632 schizo_check_iommu_error_pbm(&p->pbm_A, type);
633 schizo_check_iommu_error_pbm(&p->pbm_B, type);
634 }
635
636 /* Uncorrectable ECC error status gathering. */
637 #define SCHIZO_UE_AFSR 0x10030UL
638 #define SCHIZO_UE_AFAR 0x10038UL
639
640 #define SCHIZO_UEAFSR_PPIO 0x8000000000000000UL /* Safari */
641 #define SCHIZO_UEAFSR_PDRD 0x4000000000000000UL /* Safari/Tomatillo */
642 #define SCHIZO_UEAFSR_PDWR 0x2000000000000000UL /* Safari */
643 #define SCHIZO_UEAFSR_SPIO 0x1000000000000000UL /* Safari */
644 #define SCHIZO_UEAFSR_SDMA 0x0800000000000000UL /* Safari/Tomatillo */
645 #define SCHIZO_UEAFSR_ERRPNDG 0x0300000000000000UL /* Safari */
646 #define SCHIZO_UEAFSR_BMSK 0x000003ff00000000UL /* Safari */
647 #define SCHIZO_UEAFSR_QOFF 0x00000000c0000000UL /* Safari/Tomatillo */
648 #define SCHIZO_UEAFSR_AID 0x000000001f000000UL /* Safari/Tomatillo */
649 #define SCHIZO_UEAFSR_PARTIAL 0x0000000000800000UL /* Safari */
650 #define SCHIZO_UEAFSR_OWNEDIN 0x0000000000400000UL /* Safari */
651 #define SCHIZO_UEAFSR_MTAGSYND 0x00000000000f0000UL /* Safari */
652 #define SCHIZO_UEAFSR_MTAG 0x000000000000e000UL /* Safari */
653 #define SCHIZO_UEAFSR_ECCSYND 0x00000000000001ffUL /* Safari */
654
655 static irqreturn_t schizo_ue_intr(int irq, void *dev_id, struct pt_regs *regs)
656 {
657 struct pci_controller_info *p = dev_id;
658 unsigned long afsr_reg = p->pbm_B.controller_regs + SCHIZO_UE_AFSR;
659 unsigned long afar_reg = p->pbm_B.controller_regs + SCHIZO_UE_AFAR;
660 unsigned long afsr, afar, error_bits;
661 int reported, limit;
662
663 /* Latch uncorrectable error status. */
664 afar = schizo_read(afar_reg);
665
666 /* If either of the error pending bits are set in the
667 * AFSR, the error status is being actively updated by
668 * the hardware and we must re-read to get a clean value.
669 */
670 limit = 1000;
671 do {
672 afsr = schizo_read(afsr_reg);
673 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
674
675 /* Clear the primary/secondary error status bits. */
676 error_bits = afsr &
677 (SCHIZO_UEAFSR_PPIO | SCHIZO_UEAFSR_PDRD | SCHIZO_UEAFSR_PDWR |
678 SCHIZO_UEAFSR_SPIO | SCHIZO_UEAFSR_SDMA);
679 if (!error_bits)
680 return IRQ_NONE;
681 schizo_write(afsr_reg, error_bits);
682
683 /* Log the error. */
684 printk("PCI%d: Uncorrectable Error, primary error type[%s]\n",
685 p->index,
686 (((error_bits & SCHIZO_UEAFSR_PPIO) ?
687 "PIO" :
688 ((error_bits & SCHIZO_UEAFSR_PDRD) ?
689 "DMA Read" :
690 ((error_bits & SCHIZO_UEAFSR_PDWR) ?
691 "DMA Write" : "???")))));
692 printk("PCI%d: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
693 p->index,
694 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
695 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
696 (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
697 printk("PCI%d: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
698 p->index,
699 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
700 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
701 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
702 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
703 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
704 printk("PCI%d: UE AFAR [%016lx]\n", p->index, afar);
705 printk("PCI%d: UE Secondary errors [", p->index);
706 reported = 0;
707 if (afsr & SCHIZO_UEAFSR_SPIO) {
708 reported++;
709 printk("(PIO)");
710 }
711 if (afsr & SCHIZO_UEAFSR_SDMA) {
712 reported++;
713 printk("(DMA)");
714 }
715 if (!reported)
716 printk("(none)");
717 printk("]\n");
718
719 /* Interrogate IOMMU for error status. */
720 schizo_check_iommu_error(p, UE_ERR);
721
722 schizo_clear_other_err_intr(p, irq);
723
724 return IRQ_HANDLED;
725 }
726
727 #define SCHIZO_CE_AFSR 0x10040UL
728 #define SCHIZO_CE_AFAR 0x10048UL
729
730 #define SCHIZO_CEAFSR_PPIO 0x8000000000000000UL
731 #define SCHIZO_CEAFSR_PDRD 0x4000000000000000UL
732 #define SCHIZO_CEAFSR_PDWR 0x2000000000000000UL
733 #define SCHIZO_CEAFSR_SPIO 0x1000000000000000UL
734 #define SCHIZO_CEAFSR_SDMA 0x0800000000000000UL
735 #define SCHIZO_CEAFSR_ERRPNDG 0x0300000000000000UL
736 #define SCHIZO_CEAFSR_BMSK 0x000003ff00000000UL
737 #define SCHIZO_CEAFSR_QOFF 0x00000000c0000000UL
738 #define SCHIZO_CEAFSR_AID 0x000000001f000000UL
739 #define SCHIZO_CEAFSR_PARTIAL 0x0000000000800000UL
740 #define SCHIZO_CEAFSR_OWNEDIN 0x0000000000400000UL
741 #define SCHIZO_CEAFSR_MTAGSYND 0x00000000000f0000UL
742 #define SCHIZO_CEAFSR_MTAG 0x000000000000e000UL
743 #define SCHIZO_CEAFSR_ECCSYND 0x00000000000001ffUL
744
745 static irqreturn_t schizo_ce_intr(int irq, void *dev_id, struct pt_regs *regs)
746 {
747 struct pci_controller_info *p = dev_id;
748 unsigned long afsr_reg = p->pbm_B.controller_regs + SCHIZO_CE_AFSR;
749 unsigned long afar_reg = p->pbm_B.controller_regs + SCHIZO_CE_AFAR;
750 unsigned long afsr, afar, error_bits;
751 int reported, limit;
752
753 /* Latch error status. */
754 afar = schizo_read(afar_reg);
755
756 /* If either of the error pending bits are set in the
757 * AFSR, the error status is being actively updated by
758 * the hardware and we must re-read to get a clean value.
759 */
760 limit = 1000;
761 do {
762 afsr = schizo_read(afsr_reg);
763 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
764
765 /* Clear primary/secondary error status bits. */
766 error_bits = afsr &
767 (SCHIZO_CEAFSR_PPIO | SCHIZO_CEAFSR_PDRD | SCHIZO_CEAFSR_PDWR |
768 SCHIZO_CEAFSR_SPIO | SCHIZO_CEAFSR_SDMA);
769 if (!error_bits)
770 return IRQ_NONE;
771 schizo_write(afsr_reg, error_bits);
772
773 /* Log the error. */
774 printk("PCI%d: Correctable Error, primary error type[%s]\n",
775 p->index,
776 (((error_bits & SCHIZO_CEAFSR_PPIO) ?
777 "PIO" :
778 ((error_bits & SCHIZO_CEAFSR_PDRD) ?
779 "DMA Read" :
780 ((error_bits & SCHIZO_CEAFSR_PDWR) ?
781 "DMA Write" : "???")))));
782
783 /* XXX Use syndrome and afar to print out module string just like
784 * XXX UDB CE trap handler does... -DaveM
785 */
786 printk("PCI%d: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
787 p->index,
788 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
789 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
790 (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
791 printk("PCI%d: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
792 p->index,
793 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
794 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
795 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
796 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
797 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
798 printk("PCI%d: CE AFAR [%016lx]\n", p->index, afar);
799 printk("PCI%d: CE Secondary errors [", p->index);
800 reported = 0;
801 if (afsr & SCHIZO_CEAFSR_SPIO) {
802 reported++;
803 printk("(PIO)");
804 }
805 if (afsr & SCHIZO_CEAFSR_SDMA) {
806 reported++;
807 printk("(DMA)");
808 }
809 if (!reported)
810 printk("(none)");
811 printk("]\n");
812
813 schizo_clear_other_err_intr(p, irq);
814
815 return IRQ_HANDLED;
816 }
817
818 #define SCHIZO_PCI_AFSR 0x2010UL
819 #define SCHIZO_PCI_AFAR 0x2018UL
820
821 #define SCHIZO_PCIAFSR_PMA 0x8000000000000000UL /* Schizo/Tomatillo */
822 #define SCHIZO_PCIAFSR_PTA 0x4000000000000000UL /* Schizo/Tomatillo */
823 #define SCHIZO_PCIAFSR_PRTRY 0x2000000000000000UL /* Schizo/Tomatillo */
824 #define SCHIZO_PCIAFSR_PPERR 0x1000000000000000UL /* Schizo/Tomatillo */
825 #define SCHIZO_PCIAFSR_PTTO 0x0800000000000000UL /* Schizo/Tomatillo */
826 #define SCHIZO_PCIAFSR_PUNUS 0x0400000000000000UL /* Schizo */
827 #define SCHIZO_PCIAFSR_SMA 0x0200000000000000UL /* Schizo/Tomatillo */
828 #define SCHIZO_PCIAFSR_STA 0x0100000000000000UL /* Schizo/Tomatillo */
829 #define SCHIZO_PCIAFSR_SRTRY 0x0080000000000000UL /* Schizo/Tomatillo */
830 #define SCHIZO_PCIAFSR_SPERR 0x0040000000000000UL /* Schizo/Tomatillo */
831 #define SCHIZO_PCIAFSR_STTO 0x0020000000000000UL /* Schizo/Tomatillo */
832 #define SCHIZO_PCIAFSR_SUNUS 0x0010000000000000UL /* Schizo */
833 #define SCHIZO_PCIAFSR_BMSK 0x000003ff00000000UL /* Schizo/Tomatillo */
834 #define SCHIZO_PCIAFSR_BLK 0x0000000080000000UL /* Schizo/Tomatillo */
835 #define SCHIZO_PCIAFSR_CFG 0x0000000040000000UL /* Schizo/Tomatillo */
836 #define SCHIZO_PCIAFSR_MEM 0x0000000020000000UL /* Schizo/Tomatillo */
837 #define SCHIZO_PCIAFSR_IO 0x0000000010000000UL /* Schizo/Tomatillo */
838
839 #define SCHIZO_PCI_CTRL (0x2000UL)
840 #define SCHIZO_PCICTRL_BUS_UNUS (1UL << 63UL) /* Safari */
841 #define SCHIZO_PCICTRL_DTO_INT (1UL << 61UL) /* Tomatillo */
842 #define SCHIZO_PCICTRL_ARB_PRIO (0x1ff << 52UL) /* Tomatillo */
843 #define SCHIZO_PCICTRL_ESLCK (1UL << 51UL) /* Safari */
844 #define SCHIZO_PCICTRL_ERRSLOT (7UL << 48UL) /* Safari */
845 #define SCHIZO_PCICTRL_TTO_ERR (1UL << 38UL) /* Safari/Tomatillo */
846 #define SCHIZO_PCICTRL_RTRY_ERR (1UL << 37UL) /* Safari/Tomatillo */
847 #define SCHIZO_PCICTRL_DTO_ERR (1UL << 36UL) /* Safari/Tomatillo */
848 #define SCHIZO_PCICTRL_SBH_ERR (1UL << 35UL) /* Safari */
849 #define SCHIZO_PCICTRL_SERR (1UL << 34UL) /* Safari/Tomatillo */
850 #define SCHIZO_PCICTRL_PCISPD (1UL << 33UL) /* Safari */
851 #define SCHIZO_PCICTRL_MRM_PREF (1UL << 30UL) /* Tomatillo */
852 #define SCHIZO_PCICTRL_RDO_PREF (1UL << 29UL) /* Tomatillo */
853 #define SCHIZO_PCICTRL_RDL_PREF (1UL << 28UL) /* Tomatillo */
854 #define SCHIZO_PCICTRL_PTO (3UL << 24UL) /* Safari/Tomatillo */
855 #define SCHIZO_PCICTRL_PTO_SHIFT 24UL
856 #define SCHIZO_PCICTRL_TRWSW (7UL << 21UL) /* Tomatillo */
857 #define SCHIZO_PCICTRL_F_TGT_A (1UL << 20UL) /* Tomatillo */
858 #define SCHIZO_PCICTRL_S_DTO_INT (1UL << 19UL) /* Safari */
859 #define SCHIZO_PCICTRL_F_TGT_RT (1UL << 19UL) /* Tomatillo */
860 #define SCHIZO_PCICTRL_SBH_INT (1UL << 18UL) /* Safari */
861 #define SCHIZO_PCICTRL_T_DTO_INT (1UL << 18UL) /* Tomatillo */
862 #define SCHIZO_PCICTRL_EEN (1UL << 17UL) /* Safari/Tomatillo */
863 #define SCHIZO_PCICTRL_PARK (1UL << 16UL) /* Safari/Tomatillo */
864 #define SCHIZO_PCICTRL_PCIRST (1UL << 8UL) /* Safari */
865 #define SCHIZO_PCICTRL_ARB_S (0x3fUL << 0UL) /* Safari */
866 #define SCHIZO_PCICTRL_ARB_T (0xffUL << 0UL) /* Tomatillo */
867
868 static irqreturn_t schizo_pcierr_intr_other(struct pci_pbm_info *pbm)
869 {
870 unsigned long csr_reg, csr, csr_error_bits;
871 irqreturn_t ret = IRQ_NONE;
872 u16 stat;
873
874 csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL;
875 csr = schizo_read(csr_reg);
876 csr_error_bits =
877 csr & (SCHIZO_PCICTRL_BUS_UNUS |
878 SCHIZO_PCICTRL_TTO_ERR |
879 SCHIZO_PCICTRL_RTRY_ERR |
880 SCHIZO_PCICTRL_DTO_ERR |
881 SCHIZO_PCICTRL_SBH_ERR |
882 SCHIZO_PCICTRL_SERR);
883 if (csr_error_bits) {
884 /* Clear the errors. */
885 schizo_write(csr_reg, csr);
886
887 /* Log 'em. */
888 if (csr_error_bits & SCHIZO_PCICTRL_BUS_UNUS)
889 printk("%s: Bus unusable error asserted.\n",
890 pbm->name);
891 if (csr_error_bits & SCHIZO_PCICTRL_TTO_ERR)
892 printk("%s: PCI TRDY# timeout error asserted.\n",
893 pbm->name);
894 if (csr_error_bits & SCHIZO_PCICTRL_RTRY_ERR)
895 printk("%s: PCI excessive retry error asserted.\n",
896 pbm->name);
897 if (csr_error_bits & SCHIZO_PCICTRL_DTO_ERR)
898 printk("%s: PCI discard timeout error asserted.\n",
899 pbm->name);
900 if (csr_error_bits & SCHIZO_PCICTRL_SBH_ERR)
901 printk("%s: PCI streaming byte hole error asserted.\n",
902 pbm->name);
903 if (csr_error_bits & SCHIZO_PCICTRL_SERR)
904 printk("%s: PCI SERR signal asserted.\n",
905 pbm->name);
906 ret = IRQ_HANDLED;
907 }
908 pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat);
909 if (stat & (PCI_STATUS_PARITY |
910 PCI_STATUS_SIG_TARGET_ABORT |
911 PCI_STATUS_REC_TARGET_ABORT |
912 PCI_STATUS_REC_MASTER_ABORT |
913 PCI_STATUS_SIG_SYSTEM_ERROR)) {
914 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
915 pbm->name, stat);
916 pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff);
917 ret = IRQ_HANDLED;
918 }
919 return ret;
920 }
921
922 static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id, struct pt_regs *regs)
923 {
924 struct pci_pbm_info *pbm = dev_id;
925 struct pci_controller_info *p = pbm->parent;
926 unsigned long afsr_reg, afar_reg, base;
927 unsigned long afsr, afar, error_bits;
928 int reported;
929
930 base = pbm->pbm_regs;
931
932 afsr_reg = base + SCHIZO_PCI_AFSR;
933 afar_reg = base + SCHIZO_PCI_AFAR;
934
935 /* Latch error status. */
936 afar = schizo_read(afar_reg);
937 afsr = schizo_read(afsr_reg);
938
939 /* Clear primary/secondary error status bits. */
940 error_bits = afsr &
941 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
942 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
943 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
944 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
945 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
946 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS);
947 if (!error_bits)
948 return schizo_pcierr_intr_other(pbm);
949 schizo_write(afsr_reg, error_bits);
950
951 /* Log the error. */
952 printk("%s: PCI Error, primary error type[%s]\n",
953 pbm->name,
954 (((error_bits & SCHIZO_PCIAFSR_PMA) ?
955 "Master Abort" :
956 ((error_bits & SCHIZO_PCIAFSR_PTA) ?
957 "Target Abort" :
958 ((error_bits & SCHIZO_PCIAFSR_PRTRY) ?
959 "Excessive Retries" :
960 ((error_bits & SCHIZO_PCIAFSR_PPERR) ?
961 "Parity Error" :
962 ((error_bits & SCHIZO_PCIAFSR_PTTO) ?
963 "Timeout" :
964 ((error_bits & SCHIZO_PCIAFSR_PUNUS) ?
965 "Bus Unusable" : "???"))))))));
966 printk("%s: bytemask[%04lx] was_block(%d) space(%s)\n",
967 pbm->name,
968 (afsr & SCHIZO_PCIAFSR_BMSK) >> 32UL,
969 (afsr & SCHIZO_PCIAFSR_BLK) ? 1 : 0,
970 ((afsr & SCHIZO_PCIAFSR_CFG) ?
971 "Config" :
972 ((afsr & SCHIZO_PCIAFSR_MEM) ?
973 "Memory" :
974 ((afsr & SCHIZO_PCIAFSR_IO) ?
975 "I/O" : "???"))));
976 printk("%s: PCI AFAR [%016lx]\n",
977 pbm->name, afar);
978 printk("%s: PCI Secondary errors [",
979 pbm->name);
980 reported = 0;
981 if (afsr & SCHIZO_PCIAFSR_SMA) {
982 reported++;
983 printk("(Master Abort)");
984 }
985 if (afsr & SCHIZO_PCIAFSR_STA) {
986 reported++;
987 printk("(Target Abort)");
988 }
989 if (afsr & SCHIZO_PCIAFSR_SRTRY) {
990 reported++;
991 printk("(Excessive Retries)");
992 }
993 if (afsr & SCHIZO_PCIAFSR_SPERR) {
994 reported++;
995 printk("(Parity Error)");
996 }
997 if (afsr & SCHIZO_PCIAFSR_STTO) {
998 reported++;
999 printk("(Timeout)");
1000 }
1001 if (afsr & SCHIZO_PCIAFSR_SUNUS) {
1002 reported++;
1003 printk("(Bus Unusable)");
1004 }
1005 if (!reported)
1006 printk("(none)");
1007 printk("]\n");
1008
1009 /* For the error types shown, scan PBM's PCI bus for devices
1010 * which have logged that error type.
1011 */
1012
1013 /* If we see a Target Abort, this could be the result of an
1014 * IOMMU translation error of some sort. It is extremely
1015 * useful to log this information as usually it indicates
1016 * a bug in the IOMMU support code or a PCI device driver.
1017 */
1018 if (error_bits & (SCHIZO_PCIAFSR_PTA | SCHIZO_PCIAFSR_STA)) {
1019 schizo_check_iommu_error(p, PCI_ERR);
1020 pci_scan_for_target_abort(p, pbm, pbm->pci_bus);
1021 }
1022 if (error_bits & (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_SMA))
1023 pci_scan_for_master_abort(p, pbm, pbm->pci_bus);
1024
1025 /* For excessive retries, PSYCHO/PBM will abort the device
1026 * and there is no way to specifically check for excessive
1027 * retries in the config space status registers. So what
1028 * we hope is that we'll catch it via the master/target
1029 * abort events.
1030 */
1031
1032 if (error_bits & (SCHIZO_PCIAFSR_PPERR | SCHIZO_PCIAFSR_SPERR))
1033 pci_scan_for_parity_error(p, pbm, pbm->pci_bus);
1034
1035 schizo_clear_other_err_intr(p, irq);
1036
1037 return IRQ_HANDLED;
1038 }
1039
1040 #define SCHIZO_SAFARI_ERRLOG 0x10018UL
1041
1042 #define SAFARI_ERRLOG_ERROUT 0x8000000000000000UL
1043
1044 #define BUS_ERROR_BADCMD 0x4000000000000000UL /* Schizo/Tomatillo */
1045 #define BUS_ERROR_SSMDIS 0x2000000000000000UL /* Safari */
1046 #define BUS_ERROR_BADMA 0x1000000000000000UL /* Safari */
1047 #define BUS_ERROR_BADMB 0x0800000000000000UL /* Safari */
1048 #define BUS_ERROR_BADMC 0x0400000000000000UL /* Safari */
1049 #define BUS_ERROR_SNOOP_GR 0x0000000000200000UL /* Tomatillo */
1050 #define BUS_ERROR_SNOOP_PCI 0x0000000000100000UL /* Tomatillo */
1051 #define BUS_ERROR_SNOOP_RD 0x0000000000080000UL /* Tomatillo */
1052 #define BUS_ERROR_SNOOP_RDS 0x0000000000020000UL /* Tomatillo */
1053 #define BUS_ERROR_SNOOP_RDSA 0x0000000000010000UL /* Tomatillo */
1054 #define BUS_ERROR_SNOOP_OWN 0x0000000000008000UL /* Tomatillo */
1055 #define BUS_ERROR_SNOOP_RDO 0x0000000000004000UL /* Tomatillo */
1056 #define BUS_ERROR_CPU1PS 0x0000000000002000UL /* Safari */
1057 #define BUS_ERROR_WDATA_PERR 0x0000000000002000UL /* Tomatillo */
1058 #define BUS_ERROR_CPU1PB 0x0000000000001000UL /* Safari */
1059 #define BUS_ERROR_CTRL_PERR 0x0000000000001000UL /* Tomatillo */
1060 #define BUS_ERROR_CPU0PS 0x0000000000000800UL /* Safari */
1061 #define BUS_ERROR_SNOOP_ERR 0x0000000000000800UL /* Tomatillo */
1062 #define BUS_ERROR_CPU0PB 0x0000000000000400UL /* Safari */
1063 #define BUS_ERROR_JBUS_ILL_B 0x0000000000000400UL /* Tomatillo */
1064 #define BUS_ERROR_CIQTO 0x0000000000000200UL /* Safari */
1065 #define BUS_ERROR_LPQTO 0x0000000000000100UL /* Safari */
1066 #define BUS_ERROR_JBUS_ILL_C 0x0000000000000100UL /* Tomatillo */
1067 #define BUS_ERROR_SFPQTO 0x0000000000000080UL /* Safari */
1068 #define BUS_ERROR_UFPQTO 0x0000000000000040UL /* Safari */
1069 #define BUS_ERROR_RD_PERR 0x0000000000000040UL /* Tomatillo */
1070 #define BUS_ERROR_APERR 0x0000000000000020UL /* Safari/Tomatillo */
1071 #define BUS_ERROR_UNMAP 0x0000000000000010UL /* Safari/Tomatillo */
1072 #define BUS_ERROR_BUSERR 0x0000000000000004UL /* Safari/Tomatillo */
1073 #define BUS_ERROR_TIMEOUT 0x0000000000000002UL /* Safari/Tomatillo */
1074 #define BUS_ERROR_ILL 0x0000000000000001UL /* Safari */
1075
1076 /* We only expect UNMAP errors here. The rest of the Safari errors
1077 * are marked fatal and thus cause a system reset.
1078 */
1079 static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id, struct pt_regs *regs)
1080 {
1081 struct pci_controller_info *p = dev_id;
1082 u64 errlog;
1083
1084 errlog = schizo_read(p->pbm_B.controller_regs + SCHIZO_SAFARI_ERRLOG);
1085 schizo_write(p->pbm_B.controller_regs + SCHIZO_SAFARI_ERRLOG,
1086 errlog & ~(SAFARI_ERRLOG_ERROUT));
1087
1088 if (!(errlog & BUS_ERROR_UNMAP)) {
1089 printk("PCI%d: Unexpected Safari/JBUS error interrupt, errlog[%016lx]\n",
1090 p->index, errlog);
1091
1092 schizo_clear_other_err_intr(p, irq);
1093 return IRQ_HANDLED;
1094 }
1095
1096 printk("PCI%d: Safari/JBUS interrupt, UNMAPPED error, interrogating IOMMUs.\n",
1097 p->index);
1098 schizo_check_iommu_error(p, SAFARI_ERR);
1099
1100 schizo_clear_other_err_intr(p, irq);
1101 return IRQ_HANDLED;
1102 }
1103
1104 /* Nearly identical to PSYCHO equivalents... */
1105 #define SCHIZO_ECC_CTRL 0x10020UL
1106 #define SCHIZO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
1107 #define SCHIZO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
1108 #define SCHIZO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
1109
1110 #define SCHIZO_SAFARI_ERRCTRL 0x10008UL
1111 #define SCHIZO_SAFERRCTRL_EN 0x8000000000000000UL
1112 #define SCHIZO_SAFARI_IRQCTRL 0x10010UL
1113 #define SCHIZO_SAFIRQCTRL_EN 0x8000000000000000UL
1114
1115 /* How the Tomatillo IRQs are routed around is pure guesswork here.
1116 *
1117 * All the Tomatillo devices I see in prtconf dumps seem to have only
1118 * a single PCI bus unit attached to it. It would seem they are seperate
1119 * devices because their PortID (ie. JBUS ID) values are all different
1120 * and thus the registers are mapped to totally different locations.
1121 *
1122 * However, two Tomatillo's look "similar" in that the only difference
1123 * in their PortID is the lowest bit.
1124 *
1125 * So if we were to ignore this lower bit, it certainly looks like two
1126 * PCI bus units of the same Tomatillo. I still have not really
1127 * figured this out...
1128 */
1129 static void tomatillo_register_error_handlers(struct pci_controller_info *p)
1130 {
1131 struct pci_pbm_info *pbm;
1132 unsigned int irq;
1133 u64 tmp, err_mask, err_no_mask;
1134
1135 /* Build IRQs and register handlers. */
1136 pbm = pbm_for_ino(p, SCHIZO_UE_INO);
1137 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_UE_INO);
1138 if (request_irq(irq, schizo_ue_intr,
1139 SA_SHIRQ, "TOMATILLO UE", p) < 0) {
1140 prom_printf("%s: Cannot register UE interrupt.\n",
1141 pbm->name);
1142 prom_halt();
1143 }
1144 tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_UE_INO));
1145 upa_writel(tmp, (pbm->pbm_regs +
1146 schizo_imap_offset(SCHIZO_UE_INO) + 4));
1147
1148 pbm = pbm_for_ino(p, SCHIZO_CE_INO);
1149 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_CE_INO);
1150 if (request_irq(irq, schizo_ce_intr,
1151 SA_SHIRQ, "TOMATILLO CE", p) < 0) {
1152 prom_printf("%s: Cannot register CE interrupt.\n",
1153 pbm->name);
1154 prom_halt();
1155 }
1156 tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_CE_INO));
1157 upa_writel(tmp, (pbm->pbm_regs +
1158 schizo_imap_offset(SCHIZO_CE_INO) + 4));
1159
1160 pbm = pbm_for_ino(p, SCHIZO_PCIERR_A_INO);
1161 irq = schizo_irq_build(pbm, NULL, ((pbm->portid << 6) |
1162 SCHIZO_PCIERR_A_INO));
1163 if (request_irq(irq, schizo_pcierr_intr,
1164 SA_SHIRQ, "TOMATILLO PCIERR", pbm) < 0) {
1165 prom_printf("%s: Cannot register PBM A PciERR interrupt.\n",
1166 pbm->name);
1167 prom_halt();
1168 }
1169 tmp = upa_readl(schizo_ino_to_imap(pbm, ((pbm->portid << 6) |
1170 SCHIZO_PCIERR_A_INO)));
1171 upa_writel(tmp, (pbm->pbm_regs +
1172 schizo_imap_offset(SCHIZO_PCIERR_A_INO) + 4));
1173
1174 pbm = pbm_for_ino(p, SCHIZO_PCIERR_B_INO);
1175 irq = schizo_irq_build(pbm, NULL, ((pbm->portid << 6) |
1176 SCHIZO_PCIERR_B_INO));
1177 if (request_irq(irq, schizo_pcierr_intr,
1178 SA_SHIRQ, "TOMATILLO PCIERR", pbm) < 0) {
1179 prom_printf("%s: Cannot register PBM B PciERR interrupt.\n",
1180 pbm->name);
1181 prom_halt();
1182 }
1183 tmp = upa_readl(schizo_ino_to_imap(pbm, ((pbm->portid << 6) |
1184 SCHIZO_PCIERR_B_INO)));
1185 upa_writel(tmp, (pbm->pbm_regs +
1186 schizo_imap_offset(SCHIZO_PCIERR_B_INO) + 4));
1187
1188 pbm = pbm_for_ino(p, SCHIZO_SERR_INO);
1189 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_SERR_INO);
1190 if (request_irq(irq, schizo_safarierr_intr,
1191 SA_SHIRQ, "TOMATILLO SERR", p) < 0) {
1192 prom_printf("%s: Cannot register SafariERR interrupt.\n",
1193 pbm->name);
1194 prom_halt();
1195 }
1196 tmp = upa_readl(schizo_ino_to_imap(pbm, ((pbm->portid << 6) |
1197 SCHIZO_SERR_INO)));
1198 upa_writel(tmp, (pbm->pbm_regs +
1199 schizo_imap_offset(SCHIZO_SERR_INO) + 4));
1200
1201 /* Enable UE and CE interrupts for controller. */
1202 schizo_write(p->pbm_A.controller_regs + SCHIZO_ECC_CTRL,
1203 (SCHIZO_ECCCTRL_EE |
1204 SCHIZO_ECCCTRL_UE |
1205 SCHIZO_ECCCTRL_CE));
1206
1207 schizo_write(p->pbm_B.controller_regs + SCHIZO_ECC_CTRL,
1208 (SCHIZO_ECCCTRL_EE |
1209 SCHIZO_ECCCTRL_UE |
1210 SCHIZO_ECCCTRL_CE));
1211
1212 /* Enable PCI Error interrupts and clear error
1213 * bits.
1214 */
1215 err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
1216 SCHIZO_PCICTRL_TTO_ERR |
1217 SCHIZO_PCICTRL_RTRY_ERR |
1218 SCHIZO_PCICTRL_SERR |
1219 SCHIZO_PCICTRL_EEN);
1220
1221 err_no_mask = SCHIZO_PCICTRL_DTO_ERR;
1222
1223 tmp = schizo_read(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL);
1224 tmp |= err_mask;
1225 tmp &= ~err_no_mask;
1226 schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL, tmp);
1227
1228 tmp = schizo_read(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL);
1229 tmp |= err_mask;
1230 tmp &= ~err_no_mask;
1231 schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL, tmp);
1232
1233 err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1234 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1235 SCHIZO_PCIAFSR_PTTO |
1236 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
1237 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1238 SCHIZO_PCIAFSR_STTO);
1239
1240 schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_AFSR, err_mask);
1241 schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_AFSR, err_mask);
1242
1243 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR |
1244 BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD |
1245 BUS_ERROR_SNOOP_RDS | BUS_ERROR_SNOOP_RDSA |
1246 BUS_ERROR_SNOOP_OWN | BUS_ERROR_SNOOP_RDO |
1247 BUS_ERROR_WDATA_PERR | BUS_ERROR_CTRL_PERR |
1248 BUS_ERROR_SNOOP_ERR | BUS_ERROR_JBUS_ILL_B |
1249 BUS_ERROR_JBUS_ILL_C | BUS_ERROR_RD_PERR |
1250 BUS_ERROR_APERR | BUS_ERROR_UNMAP |
1251 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT);
1252
1253 schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_ERRCTRL,
1254 (SCHIZO_SAFERRCTRL_EN | err_mask));
1255 schizo_write(p->pbm_B.controller_regs + SCHIZO_SAFARI_ERRCTRL,
1256 (SCHIZO_SAFERRCTRL_EN | err_mask));
1257
1258 schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_IRQCTRL,
1259 (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)));
1260 schizo_write(p->pbm_B.controller_regs + SCHIZO_SAFARI_IRQCTRL,
1261 (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)));
1262 }
1263
1264 static void schizo_register_error_handlers(struct pci_controller_info *p)
1265 {
1266 struct pci_pbm_info *pbm;
1267 unsigned int irq;
1268 u64 tmp, err_mask, err_no_mask;
1269
1270 /* Build IRQs and register handlers. */
1271 pbm = pbm_for_ino(p, SCHIZO_UE_INO);
1272 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_UE_INO);
1273 if (request_irq(irq, schizo_ue_intr,
1274 SA_SHIRQ, "SCHIZO UE", p) < 0) {
1275 prom_printf("%s: Cannot register UE interrupt.\n",
1276 pbm->name);
1277 prom_halt();
1278 }
1279 tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_UE_INO));
1280 upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_UE_INO) + 4));
1281
1282 pbm = pbm_for_ino(p, SCHIZO_CE_INO);
1283 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_CE_INO);
1284 if (request_irq(irq, schizo_ce_intr,
1285 SA_SHIRQ, "SCHIZO CE", p) < 0) {
1286 prom_printf("%s: Cannot register CE interrupt.\n",
1287 pbm->name);
1288 prom_halt();
1289 }
1290 tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_CE_INO));
1291 upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_CE_INO) + 4));
1292
1293 pbm = pbm_for_ino(p, SCHIZO_PCIERR_A_INO);
1294 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_PCIERR_A_INO);
1295 if (request_irq(irq, schizo_pcierr_intr,
1296 SA_SHIRQ, "SCHIZO PCIERR", pbm) < 0) {
1297 prom_printf("%s: Cannot register PBM A PciERR interrupt.\n",
1298 pbm->name);
1299 prom_halt();
1300 }
1301 tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_PCIERR_A_INO));
1302 upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_PCIERR_A_INO) + 4));
1303
1304 pbm = pbm_for_ino(p, SCHIZO_PCIERR_B_INO);
1305 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_PCIERR_B_INO);
1306 if (request_irq(irq, schizo_pcierr_intr,
1307 SA_SHIRQ, "SCHIZO PCIERR", &p->pbm_B) < 0) {
1308 prom_printf("%s: Cannot register PBM B PciERR interrupt.\n",
1309 pbm->name);
1310 prom_halt();
1311 }
1312 tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_PCIERR_B_INO));
1313 upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_PCIERR_B_INO) + 4));
1314
1315 pbm = pbm_for_ino(p, SCHIZO_SERR_INO);
1316 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_SERR_INO);
1317 if (request_irq(irq, schizo_safarierr_intr,
1318 SA_SHIRQ, "SCHIZO SERR", p) < 0) {
1319 prom_printf("%s: Cannot register SafariERR interrupt.\n",
1320 pbm->name);
1321 prom_halt();
1322 }
1323 tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_SERR_INO));
1324 upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_SERR_INO) + 4));
1325
1326 /* Enable UE and CE interrupts for controller. */
1327 schizo_write(p->pbm_A.controller_regs + SCHIZO_ECC_CTRL,
1328 (SCHIZO_ECCCTRL_EE |
1329 SCHIZO_ECCCTRL_UE |
1330 SCHIZO_ECCCTRL_CE));
1331
1332 err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
1333 SCHIZO_PCICTRL_ESLCK |
1334 SCHIZO_PCICTRL_TTO_ERR |
1335 SCHIZO_PCICTRL_RTRY_ERR |
1336 SCHIZO_PCICTRL_SBH_ERR |
1337 SCHIZO_PCICTRL_SERR |
1338 SCHIZO_PCICTRL_EEN);
1339
1340 err_no_mask = (SCHIZO_PCICTRL_DTO_ERR |
1341 SCHIZO_PCICTRL_SBH_INT);
1342
1343 /* Enable PCI Error interrupts and clear error
1344 * bits for each PBM.
1345 */
1346 tmp = schizo_read(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL);
1347 tmp |= err_mask;
1348 tmp &= ~err_no_mask;
1349 schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL, tmp);
1350
1351 schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_AFSR,
1352 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1353 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1354 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
1355 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
1356 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1357 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS));
1358
1359 tmp = schizo_read(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL);
1360 tmp |= err_mask;
1361 tmp &= ~err_no_mask;
1362 schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL, tmp);
1363
1364 schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_AFSR,
1365 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1366 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1367 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
1368 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
1369 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1370 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS));
1371
1372 /* Make all Safari error conditions fatal except unmapped
1373 * errors which we make generate interrupts.
1374 */
1375 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SSMDIS |
1376 BUS_ERROR_BADMA | BUS_ERROR_BADMB |
1377 BUS_ERROR_BADMC |
1378 BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
1379 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB |
1380 BUS_ERROR_CIQTO |
1381 BUS_ERROR_LPQTO | BUS_ERROR_SFPQTO |
1382 BUS_ERROR_UFPQTO | BUS_ERROR_APERR |
1383 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT |
1384 BUS_ERROR_ILL);
1385 #if 1
1386 /* XXX Something wrong with some Excalibur systems
1387 * XXX Sun is shipping. The behavior on a 2-cpu
1388 * XXX machine is that both CPU1 parity error bits
1389 * XXX are set and are immediately set again when
1390 * XXX their error status bits are cleared. Just
1391 * XXX ignore them for now. -DaveM
1392 */
1393 err_mask &= ~(BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
1394 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB);
1395 #endif
1396
1397 schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_ERRCTRL,
1398 (SCHIZO_SAFERRCTRL_EN | err_mask));
1399
1400 schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_IRQCTRL,
1401 (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)));
1402 }
1403
1404 static void pbm_config_busmastering(struct pci_pbm_info *pbm)
1405 {
1406 u8 *addr;
1407
1408 /* Set cache-line size to 64 bytes, this is actually
1409 * a nop but I do it for completeness.
1410 */
1411 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1412 0, PCI_CACHE_LINE_SIZE);
1413 pci_config_write8(addr, 64 / sizeof(u32));
1414
1415 /* Set PBM latency timer to 64 PCI clocks. */
1416 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1417 0, PCI_LATENCY_TIMER);
1418 pci_config_write8(addr, 64);
1419 }
1420
1421 static void pbm_scan_bus(struct pci_controller_info *p,
1422 struct pci_pbm_info *pbm)
1423 {
1424 struct pcidev_cookie *cookie = kzalloc(sizeof(*cookie), GFP_KERNEL);
1425
1426 if (!cookie) {
1427 prom_printf("%s: Critical allocation failure.\n", pbm->name);
1428 prom_halt();
1429 }
1430
1431 /* All we care about is the PBM. */
1432 cookie->pbm = pbm;
1433
1434 pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno,
1435 p->pci_ops,
1436 pbm);
1437 pci_fixup_host_bridge_self(pbm->pci_bus);
1438 pbm->pci_bus->self->sysdata = cookie;
1439
1440 pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
1441 pci_record_assignments(pbm, pbm->pci_bus);
1442 pci_assign_unassigned(pbm, pbm->pci_bus);
1443 pci_fixup_irq(pbm, pbm->pci_bus);
1444 pci_determine_66mhz_disposition(pbm, pbm->pci_bus);
1445 pci_setup_busmastering(pbm, pbm->pci_bus);
1446 }
1447
1448 static void __schizo_scan_bus(struct pci_controller_info *p,
1449 int chip_type)
1450 {
1451 if (!p->pbm_B.prom_node || !p->pbm_A.prom_node) {
1452 printk("PCI: Only one PCI bus module of controller found.\n");
1453 printk("PCI: Ignoring entire controller.\n");
1454 return;
1455 }
1456
1457 pbm_config_busmastering(&p->pbm_B);
1458 p->pbm_B.is_66mhz_capable =
1459 prom_getbool(p->pbm_B.prom_node, "66mhz-capable");
1460 pbm_config_busmastering(&p->pbm_A);
1461 p->pbm_A.is_66mhz_capable =
1462 prom_getbool(p->pbm_A.prom_node, "66mhz-capable");
1463 pbm_scan_bus(p, &p->pbm_B);
1464 pbm_scan_bus(p, &p->pbm_A);
1465
1466 /* After the PCI bus scan is complete, we can register
1467 * the error interrupt handlers.
1468 */
1469 if (chip_type == PBM_CHIP_TYPE_TOMATILLO)
1470 tomatillo_register_error_handlers(p);
1471 else
1472 schizo_register_error_handlers(p);
1473 }
1474
1475 static void schizo_scan_bus(struct pci_controller_info *p)
1476 {
1477 __schizo_scan_bus(p, PBM_CHIP_TYPE_SCHIZO);
1478 }
1479
1480 static void tomatillo_scan_bus(struct pci_controller_info *p)
1481 {
1482 __schizo_scan_bus(p, PBM_CHIP_TYPE_TOMATILLO);
1483 }
1484
1485 static void schizo_base_address_update(struct pci_dev *pdev, int resource)
1486 {
1487 struct pcidev_cookie *pcp = pdev->sysdata;
1488 struct pci_pbm_info *pbm = pcp->pbm;
1489 struct resource *res, *root;
1490 u32 reg;
1491 int where, size, is_64bit;
1492
1493 res = &pdev->resource[resource];
1494 if (resource < 6) {
1495 where = PCI_BASE_ADDRESS_0 + (resource * 4);
1496 } else if (resource == PCI_ROM_RESOURCE) {
1497 where = pdev->rom_base_reg;
1498 } else {
1499 /* Somebody might have asked allocation of a non-standard resource */
1500 return;
1501 }
1502
1503 is_64bit = 0;
1504 if (res->flags & IORESOURCE_IO)
1505 root = &pbm->io_space;
1506 else {
1507 root = &pbm->mem_space;
1508 if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
1509 == PCI_BASE_ADDRESS_MEM_TYPE_64)
1510 is_64bit = 1;
1511 }
1512
1513 size = res->end - res->start;
1514 pci_read_config_dword(pdev, where, &reg);
1515 reg = ((reg & size) |
1516 (((u32)(res->start - root->start)) & ~size));
1517 if (resource == PCI_ROM_RESOURCE) {
1518 reg |= PCI_ROM_ADDRESS_ENABLE;
1519 res->flags |= IORESOURCE_ROM_ENABLE;
1520 }
1521 pci_write_config_dword(pdev, where, reg);
1522
1523 /* This knows that the upper 32-bits of the address
1524 * must be zero. Our PCI common layer enforces this.
1525 */
1526 if (is_64bit)
1527 pci_write_config_dword(pdev, where + 4, 0);
1528 }
1529
1530 static void schizo_resource_adjust(struct pci_dev *pdev,
1531 struct resource *res,
1532 struct resource *root)
1533 {
1534 res->start += root->start;
1535 res->end += root->start;
1536 }
1537
1538 /* Use ranges property to determine where PCI MEM, I/O, and Config
1539 * space are for this PCI bus module.
1540 */
1541 static void schizo_determine_mem_io_space(struct pci_pbm_info *pbm)
1542 {
1543 int i, saw_cfg, saw_mem, saw_io;
1544
1545 saw_cfg = saw_mem = saw_io = 0;
1546 for (i = 0; i < pbm->num_pbm_ranges; i++) {
1547 struct linux_prom_pci_ranges *pr = &pbm->pbm_ranges[i];
1548 unsigned long a;
1549 int type;
1550
1551 type = (pr->child_phys_hi >> 24) & 0x3;
1552 a = (((unsigned long)pr->parent_phys_hi << 32UL) |
1553 ((unsigned long)pr->parent_phys_lo << 0UL));
1554
1555 switch (type) {
1556 case 0:
1557 /* PCI config space, 16MB */
1558 pbm->config_space = a;
1559 saw_cfg = 1;
1560 break;
1561
1562 case 1:
1563 /* 16-bit IO space, 16MB */
1564 pbm->io_space.start = a;
1565 pbm->io_space.end = a + ((16UL*1024UL*1024UL) - 1UL);
1566 pbm->io_space.flags = IORESOURCE_IO;
1567 saw_io = 1;
1568 break;
1569
1570 case 2:
1571 /* 32-bit MEM space, 2GB */
1572 pbm->mem_space.start = a;
1573 pbm->mem_space.end = a + (0x80000000UL - 1UL);
1574 pbm->mem_space.flags = IORESOURCE_MEM;
1575 saw_mem = 1;
1576 break;
1577
1578 default:
1579 break;
1580 };
1581 }
1582
1583 if (!saw_cfg || !saw_io || !saw_mem) {
1584 prom_printf("%s: Fatal error, missing %s PBM range.\n",
1585 pbm->name,
1586 ((!saw_cfg ?
1587 "CFG" :
1588 (!saw_io ?
1589 "IO" : "MEM"))));
1590 prom_halt();
1591 }
1592
1593 printk("%s: PCI CFG[%lx] IO[%lx] MEM[%lx]\n",
1594 pbm->name,
1595 pbm->config_space,
1596 pbm->io_space.start,
1597 pbm->mem_space.start);
1598 }
1599
1600 static void pbm_register_toplevel_resources(struct pci_controller_info *p,
1601 struct pci_pbm_info *pbm)
1602 {
1603 pbm->io_space.name = pbm->mem_space.name = pbm->name;
1604
1605 request_resource(&ioport_resource, &pbm->io_space);
1606 request_resource(&iomem_resource, &pbm->mem_space);
1607 pci_register_legacy_regions(&pbm->io_space,
1608 &pbm->mem_space);
1609 }
1610
1611 #define SCHIZO_STRBUF_CONTROL (0x02800UL)
1612 #define SCHIZO_STRBUF_FLUSH (0x02808UL)
1613 #define SCHIZO_STRBUF_FSYNC (0x02810UL)
1614 #define SCHIZO_STRBUF_CTXFLUSH (0x02818UL)
1615 #define SCHIZO_STRBUF_CTXMATCH (0x10000UL)
1616
1617 static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm)
1618 {
1619 unsigned long base = pbm->pbm_regs;
1620 u64 control;
1621
1622 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1623 /* TOMATILLO lacks streaming cache. */
1624 return;
1625 }
1626
1627 /* SCHIZO has context flushing. */
1628 pbm->stc.strbuf_control = base + SCHIZO_STRBUF_CONTROL;
1629 pbm->stc.strbuf_pflush = base + SCHIZO_STRBUF_FLUSH;
1630 pbm->stc.strbuf_fsync = base + SCHIZO_STRBUF_FSYNC;
1631 pbm->stc.strbuf_ctxflush = base + SCHIZO_STRBUF_CTXFLUSH;
1632 pbm->stc.strbuf_ctxmatch_base = base + SCHIZO_STRBUF_CTXMATCH;
1633
1634 pbm->stc.strbuf_flushflag = (volatile unsigned long *)
1635 ((((unsigned long)&pbm->stc.__flushflag_buf[0])
1636 + 63UL)
1637 & ~63UL);
1638 pbm->stc.strbuf_flushflag_pa = (unsigned long)
1639 __pa(pbm->stc.strbuf_flushflag);
1640
1641 /* Turn off LRU locking and diag mode, enable the
1642 * streaming buffer and leave the rerun-disable
1643 * setting however OBP set it.
1644 */
1645 control = schizo_read(pbm->stc.strbuf_control);
1646 control &= ~(SCHIZO_STRBUF_CTRL_LPTR |
1647 SCHIZO_STRBUF_CTRL_LENAB |
1648 SCHIZO_STRBUF_CTRL_DENAB);
1649 control |= SCHIZO_STRBUF_CTRL_ENAB;
1650 schizo_write(pbm->stc.strbuf_control, control);
1651
1652 pbm->stc.strbuf_enabled = 1;
1653 }
1654
1655 #define SCHIZO_IOMMU_CONTROL (0x00200UL)
1656 #define SCHIZO_IOMMU_TSBBASE (0x00208UL)
1657 #define SCHIZO_IOMMU_FLUSH (0x00210UL)
1658 #define SCHIZO_IOMMU_CTXFLUSH (0x00218UL)
1659
1660 static void schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
1661 {
1662 struct pci_iommu *iommu = pbm->iommu;
1663 unsigned long i, tagbase, database;
1664 u32 vdma[2], dma_mask;
1665 u64 control;
1666 int err, tsbsize;
1667
1668 err = prom_getproperty(pbm->prom_node, "virtual-dma",
1669 (char *)&vdma[0], sizeof(vdma));
1670 if (err == 0 || err == -1) {
1671 /* No property, use default values. */
1672 vdma[0] = 0xc0000000;
1673 vdma[1] = 0x40000000;
1674 }
1675
1676 dma_mask = vdma[0];
1677 switch (vdma[1]) {
1678 case 0x20000000:
1679 dma_mask |= 0x1fffffff;
1680 tsbsize = 64;
1681 break;
1682
1683 case 0x40000000:
1684 dma_mask |= 0x3fffffff;
1685 tsbsize = 128;
1686 break;
1687
1688 case 0x80000000:
1689 dma_mask |= 0x7fffffff;
1690 tsbsize = 128;
1691 break;
1692
1693 default:
1694 prom_printf("SCHIZO: strange virtual-dma size.\n");
1695 prom_halt();
1696 };
1697
1698 /* Register addresses, SCHIZO has iommu ctx flushing. */
1699 iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL;
1700 iommu->iommu_tsbbase = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE;
1701 iommu->iommu_flush = pbm->pbm_regs + SCHIZO_IOMMU_FLUSH;
1702 iommu->iommu_ctxflush = pbm->pbm_regs + SCHIZO_IOMMU_CTXFLUSH;
1703
1704 /* We use the main control/status register of SCHIZO as the write
1705 * completion register.
1706 */
1707 iommu->write_complete_reg = pbm->controller_regs + 0x10000UL;
1708
1709 /*
1710 * Invalidate TLB Entries.
1711 */
1712 control = schizo_read(iommu->iommu_control);
1713 control |= SCHIZO_IOMMU_CTRL_DENAB;
1714 schizo_write(iommu->iommu_control, control);
1715
1716 tagbase = SCHIZO_IOMMU_TAG, database = SCHIZO_IOMMU_DATA;
1717
1718 for(i = 0; i < 16; i++) {
1719 schizo_write(pbm->pbm_regs + tagbase + (i * 8UL), 0);
1720 schizo_write(pbm->pbm_regs + database + (i * 8UL), 0);
1721 }
1722
1723 /* Leave diag mode enabled for full-flushing done
1724 * in pci_iommu.c
1725 */
1726 pci_iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask);
1727
1728 schizo_write(iommu->iommu_tsbbase, __pa(iommu->page_table));
1729
1730 control = schizo_read(iommu->iommu_control);
1731 control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ);
1732 switch (tsbsize) {
1733 case 64:
1734 control |= SCHIZO_IOMMU_TSBSZ_64K;
1735 break;
1736 case 128:
1737 control |= SCHIZO_IOMMU_TSBSZ_128K;
1738 break;
1739 };
1740
1741 control |= SCHIZO_IOMMU_CTRL_ENAB;
1742 schizo_write(iommu->iommu_control, control);
1743 }
1744
1745 #define SCHIZO_PCI_IRQ_RETRY (0x1a00UL)
1746 #define SCHIZO_IRQ_RETRY_INF 0xffUL
1747
1748 #define SCHIZO_PCI_DIAG (0x2020UL)
1749 #define SCHIZO_PCIDIAG_D_BADECC (1UL << 10UL) /* Disable BAD ECC errors (Schizo) */
1750 #define SCHIZO_PCIDIAG_D_BYPASS (1UL << 9UL) /* Disable MMU bypass mode (Schizo/Tomatillo) */
1751 #define SCHIZO_PCIDIAG_D_TTO (1UL << 8UL) /* Disable TTO errors (Schizo/Tomatillo) */
1752 #define SCHIZO_PCIDIAG_D_RTRYARB (1UL << 7UL) /* Disable retry arbitration (Schizo) */
1753 #define SCHIZO_PCIDIAG_D_RETRY (1UL << 6UL) /* Disable retry limit (Schizo/Tomatillo) */
1754 #define SCHIZO_PCIDIAG_D_INTSYNC (1UL << 5UL) /* Disable interrupt/DMA synch (Schizo/Tomatillo) */
1755 #define SCHIZO_PCIDIAG_I_DMA_PARITY (1UL << 3UL) /* Invert DMA parity (Schizo/Tomatillo) */
1756 #define SCHIZO_PCIDIAG_I_PIOD_PARITY (1UL << 2UL) /* Invert PIO data parity (Schizo/Tomatillo) */
1757 #define SCHIZO_PCIDIAG_I_PIOA_PARITY (1UL << 1UL) /* Invert PIO address parity (Schizo/Tomatillo) */
1758
1759 #define TOMATILLO_PCI_IOC_CSR (0x2248UL)
1760 #define TOMATILLO_IOC_PART_WPENAB 0x0000000000080000UL
1761 #define TOMATILLO_IOC_RDMULT_PENAB 0x0000000000040000UL
1762 #define TOMATILLO_IOC_RDONE_PENAB 0x0000000000020000UL
1763 #define TOMATILLO_IOC_RDLINE_PENAB 0x0000000000010000UL
1764 #define TOMATILLO_IOC_RDMULT_PLEN 0x000000000000c000UL
1765 #define TOMATILLO_IOC_RDMULT_PLEN_SHIFT 14UL
1766 #define TOMATILLO_IOC_RDONE_PLEN 0x0000000000003000UL
1767 #define TOMATILLO_IOC_RDONE_PLEN_SHIFT 12UL
1768 #define TOMATILLO_IOC_RDLINE_PLEN 0x0000000000000c00UL
1769 #define TOMATILLO_IOC_RDLINE_PLEN_SHIFT 10UL
1770 #define TOMATILLO_IOC_PREF_OFF 0x00000000000003f8UL
1771 #define TOMATILLO_IOC_PREF_OFF_SHIFT 3UL
1772 #define TOMATILLO_IOC_RDMULT_CPENAB 0x0000000000000004UL
1773 #define TOMATILLO_IOC_RDONE_CPENAB 0x0000000000000002UL
1774 #define TOMATILLO_IOC_RDLINE_CPENAB 0x0000000000000001UL
1775
1776 #define TOMATILLO_PCI_IOC_TDIAG (0x2250UL)
1777 #define TOMATILLO_PCI_IOC_DDIAG (0x2290UL)
1778
1779 static void schizo_pbm_hw_init(struct pci_pbm_info *pbm)
1780 {
1781 u64 tmp;
1782
1783 schizo_write(pbm->pbm_regs + SCHIZO_PCI_IRQ_RETRY, 5);
1784
1785 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1786
1787 /* Enable arbiter for all PCI slots. */
1788 tmp |= 0xff;
1789
1790 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
1791 pbm->chip_version >= 0x2)
1792 tmp |= 0x3UL << SCHIZO_PCICTRL_PTO_SHIFT;
1793
1794 if (!prom_getbool(pbm->prom_node, "no-bus-parking"))
1795 tmp |= SCHIZO_PCICTRL_PARK;
1796 else
1797 tmp &= ~SCHIZO_PCICTRL_PARK;
1798
1799 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
1800 pbm->chip_version <= 0x1)
1801 tmp |= SCHIZO_PCICTRL_DTO_INT;
1802 else
1803 tmp &= ~SCHIZO_PCICTRL_DTO_INT;
1804
1805 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
1806 tmp |= (SCHIZO_PCICTRL_MRM_PREF |
1807 SCHIZO_PCICTRL_RDO_PREF |
1808 SCHIZO_PCICTRL_RDL_PREF);
1809
1810 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp);
1811
1812 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_DIAG);
1813 tmp &= ~(SCHIZO_PCIDIAG_D_RTRYARB |
1814 SCHIZO_PCIDIAG_D_RETRY |
1815 SCHIZO_PCIDIAG_D_INTSYNC);
1816 schizo_write(pbm->pbm_regs + SCHIZO_PCI_DIAG, tmp);
1817
1818 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1819 /* Clear prefetch lengths to workaround a bug in
1820 * Jalapeno...
1821 */
1822 tmp = (TOMATILLO_IOC_PART_WPENAB |
1823 (1 << TOMATILLO_IOC_PREF_OFF_SHIFT) |
1824 TOMATILLO_IOC_RDMULT_CPENAB |
1825 TOMATILLO_IOC_RDONE_CPENAB |
1826 TOMATILLO_IOC_RDLINE_CPENAB);
1827
1828 schizo_write(pbm->pbm_regs + TOMATILLO_PCI_IOC_CSR,
1829 tmp);
1830 }
1831 }
1832
1833 static void schizo_pbm_init(struct pci_controller_info *p,
1834 int prom_node, u32 portid,
1835 int chip_type)
1836 {
1837 struct linux_prom64_registers pr_regs[4];
1838 unsigned int busrange[2];
1839 struct pci_pbm_info *pbm;
1840 const char *chipset_name;
1841 u32 ino_bitmap[2];
1842 int is_pbm_a;
1843 int err;
1844
1845 switch (chip_type) {
1846 case PBM_CHIP_TYPE_TOMATILLO:
1847 chipset_name = "TOMATILLO";
1848 break;
1849
1850 case PBM_CHIP_TYPE_SCHIZO_PLUS:
1851 chipset_name = "SCHIZO+";
1852 break;
1853
1854 case PBM_CHIP_TYPE_SCHIZO:
1855 default:
1856 chipset_name = "SCHIZO";
1857 break;
1858 };
1859
1860 /* For SCHIZO, three OBP regs:
1861 * 1) PBM controller regs
1862 * 2) Schizo front-end controller regs (same for both PBMs)
1863 * 3) PBM PCI config space
1864 *
1865 * For TOMATILLO, four OBP regs:
1866 * 1) PBM controller regs
1867 * 2) Tomatillo front-end controller regs
1868 * 3) PBM PCI config space
1869 * 4) Ichip regs
1870 */
1871 err = prom_getproperty(prom_node, "reg",
1872 (char *)&pr_regs[0],
1873 sizeof(pr_regs));
1874 if (err == 0 || err == -1) {
1875 prom_printf("%s: Fatal error, no reg property.\n",
1876 chipset_name);
1877 prom_halt();
1878 }
1879
1880 is_pbm_a = ((pr_regs[0].phys_addr & 0x00700000) == 0x00600000);
1881
1882 if (is_pbm_a)
1883 pbm = &p->pbm_A;
1884 else
1885 pbm = &p->pbm_B;
1886
1887 pbm->portid = portid;
1888 pbm->parent = p;
1889 pbm->prom_node = prom_node;
1890 pbm->pci_first_slot = 1;
1891
1892 pbm->chip_type = chip_type;
1893 pbm->chip_version =
1894 prom_getintdefault(prom_node, "version#", 0);
1895 pbm->chip_revision =
1896 prom_getintdefault(prom_node, "module-revision#", 0);
1897
1898 pbm->pbm_regs = pr_regs[0].phys_addr;
1899 pbm->controller_regs = pr_regs[1].phys_addr - 0x10000UL;
1900
1901 if (chip_type == PBM_CHIP_TYPE_TOMATILLO)
1902 pbm->sync_reg = pr_regs[3].phys_addr + 0x1a18UL;
1903
1904 sprintf(pbm->name,
1905 (chip_type == PBM_CHIP_TYPE_TOMATILLO ?
1906 "TOMATILLO%d PBM%c" :
1907 "SCHIZO%d PBM%c"),
1908 p->index,
1909 (pbm == &p->pbm_A ? 'A' : 'B'));
1910
1911 printk("%s: ver[%x:%x], portid %x, "
1912 "cregs[%lx] pregs[%lx]\n",
1913 pbm->name,
1914 pbm->chip_version, pbm->chip_revision,
1915 pbm->portid,
1916 pbm->controller_regs,
1917 pbm->pbm_regs);
1918
1919 schizo_pbm_hw_init(pbm);
1920
1921 prom_getstring(prom_node, "name",
1922 pbm->prom_name,
1923 sizeof(pbm->prom_name));
1924
1925 err = prom_getproperty(prom_node, "ranges",
1926 (char *) pbm->pbm_ranges,
1927 sizeof(pbm->pbm_ranges));
1928 if (err == 0 || err == -1) {
1929 prom_printf("%s: Fatal error, no ranges property.\n",
1930 pbm->name);
1931 prom_halt();
1932 }
1933
1934 pbm->num_pbm_ranges =
1935 (err / sizeof(struct linux_prom_pci_ranges));
1936
1937 schizo_determine_mem_io_space(pbm);
1938 pbm_register_toplevel_resources(p, pbm);
1939
1940 err = prom_getproperty(prom_node, "interrupt-map",
1941 (char *)pbm->pbm_intmap,
1942 sizeof(pbm->pbm_intmap));
1943 if (err != -1) {
1944 pbm->num_pbm_intmap = (err / sizeof(struct linux_prom_pci_intmap));
1945 err = prom_getproperty(prom_node, "interrupt-map-mask",
1946 (char *)&pbm->pbm_intmask,
1947 sizeof(pbm->pbm_intmask));
1948 if (err == -1) {
1949 prom_printf("%s: Fatal error, no "
1950 "interrupt-map-mask.\n", pbm->name);
1951 prom_halt();
1952 }
1953 } else {
1954 pbm->num_pbm_intmap = 0;
1955 memset(&pbm->pbm_intmask, 0, sizeof(pbm->pbm_intmask));
1956 }
1957
1958 err = prom_getproperty(prom_node, "ino-bitmap",
1959 (char *) &ino_bitmap[0],
1960 sizeof(ino_bitmap));
1961 if (err == 0 || err == -1) {
1962 prom_printf("%s: Fatal error, no ino-bitmap.\n", pbm->name);
1963 prom_halt();
1964 }
1965 pbm->ino_bitmap = (((u64)ino_bitmap[1] << 32UL) |
1966 ((u64)ino_bitmap[0] << 0UL));
1967
1968 err = prom_getproperty(prom_node, "bus-range",
1969 (char *)&busrange[0],
1970 sizeof(busrange));
1971 if (err == 0 || err == -1) {
1972 prom_printf("%s: Fatal error, no bus-range.\n", pbm->name);
1973 prom_halt();
1974 }
1975 pbm->pci_first_busno = busrange[0];
1976 pbm->pci_last_busno = busrange[1];
1977
1978 schizo_pbm_iommu_init(pbm);
1979 schizo_pbm_strbuf_init(pbm);
1980 }
1981
1982 static inline int portid_compare(u32 x, u32 y, int chip_type)
1983 {
1984 if (chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1985 if (x == (y ^ 1))
1986 return 1;
1987 return 0;
1988 }
1989 return (x == y);
1990 }
1991
1992 static void __schizo_init(int node, char *model_name, int chip_type)
1993 {
1994 struct pci_controller_info *p;
1995 struct pci_iommu *iommu;
1996 int is_pbm_a;
1997 u32 portid;
1998
1999 portid = prom_getintdefault(node, "portid", 0xff);
2000
2001 for(p = pci_controller_root; p; p = p->next) {
2002 struct pci_pbm_info *pbm;
2003
2004 if (p->pbm_A.prom_node && p->pbm_B.prom_node)
2005 continue;
2006
2007 pbm = (p->pbm_A.prom_node ?
2008 &p->pbm_A :
2009 &p->pbm_B);
2010
2011 if (portid_compare(pbm->portid, portid, chip_type)) {
2012 is_pbm_a = (p->pbm_A.prom_node == 0);
2013 schizo_pbm_init(p, node, portid, chip_type);
2014 return;
2015 }
2016 }
2017
2018 p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
2019 if (!p) {
2020 prom_printf("SCHIZO: Fatal memory allocation error.\n");
2021 prom_halt();
2022 }
2023
2024 iommu = kzalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
2025 if (!iommu) {
2026 prom_printf("SCHIZO: Fatal memory allocation error.\n");
2027 prom_halt();
2028 }
2029 p->pbm_A.iommu = iommu;
2030
2031 iommu = kzalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
2032 if (!iommu) {
2033 prom_printf("SCHIZO: Fatal memory allocation error.\n");
2034 prom_halt();
2035 }
2036 p->pbm_B.iommu = iommu;
2037
2038 p->next = pci_controller_root;
2039 pci_controller_root = p;
2040
2041 p->index = pci_num_controllers++;
2042 p->pbms_same_domain = 0;
2043 p->scan_bus = (chip_type == PBM_CHIP_TYPE_TOMATILLO ?
2044 tomatillo_scan_bus :
2045 schizo_scan_bus);
2046 p->irq_build = schizo_irq_build;
2047 p->base_address_update = schizo_base_address_update;
2048 p->resource_adjust = schizo_resource_adjust;
2049 p->pci_ops = &schizo_ops;
2050
2051 /* Like PSYCHO we have a 2GB aligned area for memory space. */
2052 pci_memspace_mask = 0x7fffffffUL;
2053
2054 schizo_pbm_init(p, node, portid, chip_type);
2055 }
2056
2057 void schizo_init(int node, char *model_name)
2058 {
2059 __schizo_init(node, model_name, PBM_CHIP_TYPE_SCHIZO);
2060 }
2061
2062 void schizo_plus_init(int node, char *model_name)
2063 {
2064 __schizo_init(node, model_name, PBM_CHIP_TYPE_SCHIZO_PLUS);
2065 }
2066
2067 void tomatillo_init(int node, char *model_name)
2068 {
2069 __schizo_init(node, model_name, PBM_CHIP_TYPE_TOMATILLO);
2070 }
Verdex Pro support