include/asm-arm/arch-lh7a40x/entry-macro.S

   1 /*
   2  * include/asm-arm/arch-lh7a40x/entry-macro.S
   3  *
   4  * Low-level IRQ helper macros for LH7A40x platforms
   5  *
   6  * This file is licensed under  the terms of the GNU General Public
   7  * License version 2. This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10 #include <asm/hardware.h>
  11 #include <asm/arch/irqs.h>
  12
  13 /* In order to allow there to be support for both of the processor
  14    classes at the same time, we make a hack here that isn't very
  15    pretty.  At startup, the link pointed to with the
  16    branch_irq_lh7a400 symbol is replaced with a NOP when the CPU is
  17    detected as a lh7a404.
  18
  19    *** FIXME: we should clean this up so that there is only one
  20               implementation for each CPU's design.
  21
  22 */
  23
  24 #if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
  25
  26                 .macro  disable_fiq
  27                 .endm
  28
  29                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
  30
  31 branch_irq_lh7a400: b 1000f
  32
  33 @ Implementation of the LH7A404 get_irqnr_and_base.
  34
  35                 mov     \irqnr, #0                      @ VIC1 irq base
  36                 mov     \base, #io_p2v(0x80000000)      @ APB registers
  37                 add     \base, \base, #0x8000
  38                 ldr     \tmp, [\base, #0x0030]          @ VIC1_VECTADDR
  39                 tst     \tmp, #VA_VECTORED              @ Direct vectored
  40                 bne     1002f
  41                 tst     \tmp, #VA_VIC1DEFAULT           @ Default vectored VIC1
  42                 ldrne   \irqstat, [\base, #0]           @ VIC1_IRQSTATUS
  43                 bne     1001f
  44                 add     \base, \base, #(0xa000 - 0x8000)
  45                 ldr     \tmp, [\base, #0x0030]          @ VIC2_VECTADDR
  46                 tst     \tmp, #VA_VECTORED              @ Direct vectored
  47                 bne     1002f
  48                 ldr     \irqstat, [\base, #0]           @ VIC2_IRQSTATUS
  49                 mov     \irqnr, #32                     @ VIC2 irq base
  50
  51 1001:           movs    \irqstat, \irqstat, lsr #1      @ Shift into carry
  52                 bcs     1008f                           @ Bit set; irq found
  53                 add     \irqnr, \irqnr, #1
  54                 bne     1001b                           @ Until no bits
  55                 b       1009f                           @ Nothing?  Hmm.
  56 1002:           and     \irqnr, \tmp, #0x3f             @ Mask for valid bits
  57 1008:           movs    \irqstat, #1                    @ Force !Z
  58                 str     \tmp, [\base, #0x0030]          @ Clear vector
  59                 b       1009f
  60
  61 @ Implementation of the LH7A400 get_irqnr_and_base.
  62
  63 1000:           mov     \irqnr, #0
  64                 mov     \base, #io_p2v(0x80000000)      @ APB registers
  65                 ldr     \irqstat, [\base, #0x500]       @ PIC INTSR
  66
  67 1001:           movs    \irqstat, \irqstat, lsr #1      @ Shift into carry
  68                 bcs     1008f                           @ Bit set; irq found
  69                 add     \irqnr, \irqnr, #1
  70                 bne     1001b                           @ Until no bits
  71                 b       1009f                           @ Nothing?  Hmm.
  72 1008:           movs    \irqstat, #1                    @ Force !Z
  73
  74 1009:
  75                .endm
  76
  77
  78
  79 #elif defined (CONFIG_ARCH_LH7A400)
  80                 .macro  disable_fiq
  81                 .endm
  82
  83                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
  84                 mov     \irqnr, #0
  85                 mov     \base, #io_p2v(0x80000000)      @ APB registers
  86                 ldr     \irqstat, [\base, #0x500]       @ PIC INTSR
  87
  88 1001:           movs    \irqstat, \irqstat, lsr #1      @ Shift into carry
  89                 bcs     1008f                           @ Bit set; irq found
  90                 add     \irqnr, \irqnr, #1
  91                 bne     1001b                           @ Until no bits
  92                 b       1009f                           @ Nothing?  Hmm.
  93 1008:           movs    \irqstat, #1                    @ Force !Z
  94 1009:
  95                .endm
  96
  97 #elif defined(CONFIG_ARCH_LH7A404)
  98
  99                 .macro  disable_fiq
 100                 .endm
 101
 102                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
 103                 mov     \irqnr, #0                      @ VIC1 irq base
 104                 mov     \base, #io_p2v(0x80000000)      @ APB registers
 105                 add     \base, \base, #0x8000
 106                 ldr     \tmp, [\base, #0x0030]          @ VIC1_VECTADDR
 107                 tst     \tmp, #VA_VECTORED              @ Direct vectored
 108                 bne     1002f
 109                 tst     \tmp, #VA_VIC1DEFAULT           @ Default vectored VIC1
 110                 ldrne   \irqstat, [\base, #0]           @ VIC1_IRQSTATUS
 111                 bne     1001f
 112                 add     \base, \base, #(0xa000 - 0x8000)
 113                 ldr     \tmp, [\base, #0x0030]          @ VIC2_VECTADDR
 114                 tst     \tmp, #VA_VECTORED              @ Direct vectored
 115                 bne     1002f
 116                 ldr     \irqstat, [\base, #0]           @ VIC2_IRQSTATUS
 117                 mov     \irqnr, #32                     @ VIC2 irq base
 118
 119 1001:           movs    \irqstat, \irqstat, lsr #1      @ Shift into carry
 120                 bcs     1008f                           @ Bit set; irq found
 121                 add     \irqnr, \irqnr, #1
 122                 bne     1001b                           @ Until no bits
 123                 b       1009f                           @ Nothing?  Hmm.
 124 1002:           and     \irqnr, \tmp, #0x3f             @ Mask for valid bits
 125 1008:           movs    \irqstat, #1                    @ Force !Z
 126                 str     \tmp, [\base, #0x0030]          @ Clear vector
 127 1009:
 128                .endm
 129 #endif
 130
 131