include/asm-arm/arch-s3c2410/dma.h

   1 /* linux/include/asm-arm/arch-bast/dma.h
   2  *
   3  * Copyright (C) 2003,2004 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * Samsung S3C2410X DMA support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Changelog:
  13  *  ??-May-2003 BJD   Created file
  14  *  ??-Jun-2003 BJD   Added more dma functionality to go with arch
  15  *  10-Nov-2004 BJD   Added sys_device support
  16 */
  17
  18 #ifndef __ASM_ARCH_DMA_H
  19 #define __ASM_ARCH_DMA_H __FILE__
  20
  21 #include <linux/sysdev.h>
  22 #include "hardware.h"
  23
  24
  25 /*
  26  * This is the maximum DMA address(physical address) that can be DMAd to.
  27  *
  28  */
  29 #define MAX_DMA_ADDRESS         0x20000000
  30 #define MAX_DMA_TRANSFER_SIZE   0x100000 /* Data Unit is half word  */
  31
  32
  33 /* we have 4 dma channels */
  34 #define S3C2410_DMA_CHANNELS        (4)
  35
  36 /* types */
  37
  38 typedef enum {
  39         S3C2410_DMA_IDLE,
  40         S3C2410_DMA_RUNNING,
  41         S3C2410_DMA_PAUSED
  42 } s3c2410_dma_state_t;
  43
  44
  45 /* s3c2410_dma_loadst_t
  46  *
  47  * This represents the state of the DMA engine, wrt to the loaded / running
  48  * transfers. Since we don't have any way of knowing exactly the state of
  49  * the DMA transfers, we need to know the state to make decisions on wether
  50  * we can
  51  *
  52  * S3C2410_DMA_NONE
  53  *
  54  * There are no buffers loaded (the channel should be inactive)
  55  *
  56  * S3C2410_DMA_1LOADED
  57  *
  58  * There is one buffer loaded, however it has not been confirmed to be
  59  * loaded by the DMA engine. This may be because the channel is not
  60  * yet running, or the DMA driver decided that it was too costly to
  61  * sit and wait for it to happen.
  62  *
  63  * S3C2410_DMA_1RUNNING
  64  *
  65  * The buffer has been confirmed running, and not finisged
  66  *
  67  * S3C2410_DMA_1LOADED_1RUNNING
  68  *
  69  * There is a buffer waiting to be loaded by the DMA engine, and one
  70  * currently running.
  71 */
  72
  73 typedef enum {
  74         S3C2410_DMALOAD_NONE,
  75         S3C2410_DMALOAD_1LOADED,
  76         S3C2410_DMALOAD_1RUNNING,
  77         S3C2410_DMALOAD_1LOADED_1RUNNING,
  78 } s3c2410_dma_loadst_t;
  79
  80 typedef enum {
  81         S3C2410_RES_OK,
  82         S3C2410_RES_ERR,
  83         S3C2410_RES_ABORT
  84 } s3c2410_dma_buffresult_t;
  85
  86
  87 typedef enum s3c2410_dmasrc_e s3c2410_dmasrc_t;
  88
  89 enum s3c2410_dmasrc_e {
  90         S3C2410_DMASRC_HW,      /* source is memory */
  91         S3C2410_DMASRC_MEM      /* source is hardware */
  92 };
  93
  94 /* enum s3c2410_chan_op_e
  95  *
  96  * operation codes passed to the DMA code by the user, and also used
  97  * to inform the current channel owner of any changes to the system state
  98 */
  99
 100 enum s3c2410_chan_op_e {
 101         S3C2410_DMAOP_START,
 102         S3C2410_DMAOP_STOP,
 103         S3C2410_DMAOP_PAUSE,
 104         S3C2410_DMAOP_RESUME,
 105         S3C2410_DMAOP_FLUSH,
 106         S3C2410_DMAOP_TIMEOUT,           /* internal signal to handler */
 107 };
 108
 109 typedef enum s3c2410_chan_op_e s3c2410_chan_op_t;
 110
 111 /* flags */
 112
 113 #define S3C2410_DMAF_SLOW         (1<<0)   /* slow, so don't worry about
 114                                             * waiting for reloads */
 115 #define S3C2410_DMAF_AUTOSTART    (1<<1)   /* auto-start if buffer queued */
 116
 117 /* dma buffer */
 118
 119 typedef struct s3c2410_dma_buf_s s3c2410_dma_buf_t;
 120
 121 struct s3c2410_dma_client {
 122         char                *name;
 123 };
 124
 125 typedef struct s3c2410_dma_client s3c2410_dma_client_t;
 126
 127 /* s3c2410_dma_buf_s
 128  *
 129  * internally used buffer structure to describe a queued or running
 130  * buffer.
 131 */
 132
 133 struct s3c2410_dma_buf_s {
 134         s3c2410_dma_buf_t   *next;
 135         int                  magic;        /* magic */
 136         int                  size;         /* buffer size in bytes */
 137         dma_addr_t           data;         /* start of DMA data */
 138         dma_addr_t           ptr;          /* where the DMA got to [1] */
 139         void                *id;           /* client's id */
 140 };
 141
 142 /* [1] is this updated for both recv/send modes? */
 143
 144 typedef struct s3c2410_dma_chan_s s3c2410_dma_chan_t;
 145
 146 /* s3c2410_dma_cbfn_t
 147  *
 148  * buffer callback routine type
 149 */
 150
 151 typedef void (*s3c2410_dma_cbfn_t)(s3c2410_dma_chan_t *, void *buf, int size,
 152                                    s3c2410_dma_buffresult_t result);
 153
 154 typedef int  (*s3c2410_dma_opfn_t)(s3c2410_dma_chan_t *,
 155                                    s3c2410_chan_op_t );
 156
 157 struct s3c2410_dma_stats_s {
 158         unsigned long          loads;
 159         unsigned long          timeout_longest;
 160         unsigned long          timeout_shortest;
 161         unsigned long          timeout_avg;
 162         unsigned long          timeout_failed;
 163 };
 164
 165 typedef struct s3c2410_dma_stats_s s3c2410_dma_stats_t;
 166
 167 /* struct s3c2410_dma_chan_s
 168  *
 169  * full state information for each DMA channel
 170 */
 171
 172 struct s3c2410_dma_chan_s {
 173         /* channel state flags and information */
 174         unsigned char          number;      /* number of this dma channel */
 175         unsigned char          in_use;      /* channel allocated */
 176         unsigned char          irq_claimed; /* irq claimed for channel */
 177         unsigned char          irq_enabled; /* irq enabled for channel */
 178         unsigned char          xfer_unit;   /* size of an transfer */
 179
 180         /* channel state */
 181
 182         s3c2410_dma_state_t    state;
 183         s3c2410_dma_loadst_t   load_state;
 184         s3c2410_dma_client_t  *client;
 185
 186         /* channel configuration */
 187         s3c2410_dmasrc_t       source;
 188         unsigned long          dev_addr;
 189         unsigned long          load_timeout;
 190         unsigned int           flags;        /* channel flags */
 191
 192         /* channel's hardware position and configuration */
 193         void __iomem           *regs;        /* channels registers */
 194         void __iomem           *addr_reg;    /* data address register */
 195         unsigned int           irq;          /* channel irq */
 196         unsigned long          dcon;         /* default value of DCON */
 197
 198         /* driver handles */
 199         s3c2410_dma_cbfn_t     callback_fn;  /* buffer done callback */
 200         s3c2410_dma_opfn_t     op_fn;        /* channel operation callback */
 201
 202         /* stats gathering */
 203         s3c2410_dma_stats_t   *stats;
 204         s3c2410_dma_stats_t    stats_store;
 205
 206         /* buffer list and information */
 207         s3c2410_dma_buf_t      *curr;        /* current dma buffer */
 208         s3c2410_dma_buf_t      *next;        /* next buffer to load */
 209         s3c2410_dma_buf_t      *end;         /* end of queue */
 210
 211         /* system device */
 212         struct sys_device       dev;
 213 };
 214
 215 /* the currently allocated channel information */
 216 extern s3c2410_dma_chan_t s3c2410_chans[];
 217
 218 /* note, we don't really use dma_device_t at the moment */
 219 typedef unsigned long dma_device_t;
 220
 221 /* functions --------------------------------------------------------------- */
 222
 223 /* s3c2410_dma_request
 224  *
 225  * request a dma channel exclusivley
 226 */
 227
 228 extern int s3c2410_dma_request(dmach_t channel,
 229                                s3c2410_dma_client_t *, void *dev);
 230
 231
 232 /* s3c2410_dma_ctrl
 233  *
 234  * change the state of the dma channel
 235 */
 236
 237 extern int s3c2410_dma_ctrl(dmach_t channel, s3c2410_chan_op_t op);
 238
 239 /* s3c2410_dma_setflags
 240  *
 241  * set the channel's flags to a given state
 242 */
 243
 244 extern int s3c2410_dma_setflags(dmach_t channel,
 245                                 unsigned int flags);
 246
 247 /* s3c2410_dma_free
 248  *
 249  * free the dma channel (will also abort any outstanding operations)
 250 */
 251
 252 extern int s3c2410_dma_free(dmach_t channel, s3c2410_dma_client_t *);
 253
 254 /* s3c2410_dma_enqueue
 255  *
 256  * place the given buffer onto the queue of operations for the channel.
 257  * The buffer must be allocated from dma coherent memory, or the Dcache/WB
 258  * drained before the buffer is given to the DMA system.
 259 */
 260
 261 extern int s3c2410_dma_enqueue(dmach_t channel, void *id,
 262                                dma_addr_t data, int size);
 263
 264 /* s3c2410_dma_config
 265  *
 266  * configure the dma channel
 267 */
 268
 269 extern int s3c2410_dma_config(dmach_t channel, int xferunit, int dcon);
 270
 271 /* s3c2410_dma_devconfig
 272  *
 273  * configure the device we're talking to
 274 */
 275
 276 extern int s3c2410_dma_devconfig(int channel, s3c2410_dmasrc_t source,
 277                                  int hwcfg, unsigned long devaddr);
 278
 279 /* s3c2410_dma_getposition
 280  *
 281  * get the position that the dma transfer is currently at
 282 */
 283
 284 extern int s3c2410_dma_getposition(dmach_t channel,
 285                                    dma_addr_t *src, dma_addr_t *dest);
 286
 287 extern int s3c2410_dma_set_opfn(dmach_t, s3c2410_dma_opfn_t rtn);
 288 extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn);
 289
 290 /* DMA Register definitions */
 291
 292 #define S3C2410_DMA_DISRC       (0x00)
 293 #define S3C2410_DMA_DISRCC      (0x04)
 294 #define S3C2410_DMA_DIDST       (0x08)
 295 #define S3C2410_DMA_DIDSTC      (0x0C)
 296 #define S3C2410_DMA_DCON        (0x10)
 297 #define S3C2410_DMA_DSTAT       (0x14)
 298 #define S3C2410_DMA_DCSRC       (0x18)
 299 #define S3C2410_DMA_DCDST       (0x1C)
 300 #define S3C2410_DMA_DMASKTRIG   (0x20)
 301
 302 #define S3C2410_DISRCC_INC      (1<<0)
 303 #define S3C2410_DISRCC_APB      (1<<1)
 304
 305 #define S3C2410_DMASKTRIG_STOP   (1<<2)
 306 #define S3C2410_DMASKTRIG_ON     (1<<1)
 307 #define S3C2410_DMASKTRIG_SWTRIG (1<<0)
 308
 309 #define S3C2410_DCON_DEMAND     (0<<31)
 310 #define S3C2410_DCON_HANDSHAKE  (1<<31)
 311 #define S3C2410_DCON_SYNC_PCLK  (0<<30)
 312 #define S3C2410_DCON_SYNC_HCLK  (1<<30)
 313
 314 #define S3C2410_DCON_INTREQ     (1<<29)
 315
 316 #define S3C2410_DCON_CH0_XDREQ0 (0<<24)
 317 #define S3C2410_DCON_CH0_UART0  (1<<24)
 318 #define S3C2410_DCON_CH0_SDI    (2<<24)
 319 #define S3C2410_DCON_CH0_TIMER  (3<<24)
 320 #define S3C2410_DCON_CH0_USBEP1 (4<<24)
 321
 322 #define S3C2410_DCON_CH1_XDREQ1 (0<<24)
 323 #define S3C2410_DCON_CH1_UART1  (1<<24)
 324 #define S3C2410_DCON_CH1_I2SSDI (2<<24)
 325 #define S3C2410_DCON_CH1_SPI    (3<<24)
 326 #define S3C2410_DCON_CH1_USBEP2 (4<<24)
 327
 328 #define S3C2410_DCON_CH2_I2SSDO (0<<24)
 329 #define S3C2410_DCON_CH2_I2SSDI (1<<24)
 330 #define S3C2410_DCON_CH2_SDI    (2<<24)
 331 #define S3C2410_DCON_CH2_TIMER  (3<<24)
 332 #define S3C2410_DCON_CH2_USBEP3 (4<<24)
 333
 334 #define S3C2410_DCON_CH3_UART2  (0<<24)
 335 #define S3C2410_DCON_CH3_SDI    (1<<24)
 336 #define S3C2410_DCON_CH3_SPI    (2<<24)
 337 #define S3C2410_DCON_CH3_TIMER  (3<<24)
 338 #define S3C2410_DCON_CH3_USBEP4 (4<<24)
 339
 340 #define S3C2410_DCON_SRCSHIFT   (24)
 341 #define S3C2410_DCON_SRCMASK    (7<<24)
 342
 343 #define S3C2410_DCON_BYTE       (0<<20)
 344 #define S3C2410_DCON_HALFWORD   (1<<20)
 345 #define S3C2410_DCON_WORD       (2<<20)
 346
 347 #define S3C2410_DCON_AUTORELOAD (0<<22)
 348 #define S3C2410_DCON_NORELOAD   (1<<22)
 349 #define S3C2410_DCON_HWTRIG     (1<<23)
 350
 351 #ifdef CONFIG_CPU_S3C2440
 352 #define S3C2440_DIDSTC_CHKINT   (1<<2)
 353
 354 #define S3C2440_DCON_CH0_I2SSDO (5<<24)
 355 #define S3C2440_DCON_CH0_PCMIN  (6<<24)
 356
 357 #define S3C2440_DCON_CH1_PCMOUT (5<<24)
 358 #define S3C2440_DCON_CH1_SDI    (6<<24)
 359
 360 #define S3C2440_DCON_CH2_PCMIN  (5<<24)
 361 #define S3C2440_DCON_CH2_MICIN  (6<<24)
 362
 363 #define S3C2440_DCON_CH3_MICIN  (5<<24)
 364 #define S3C2440_DCON_CH3_PCMOUT (6<<24)
 365 #endif
 366
 367 #endif /* __ASM_ARCH_DMA_H */