[PATCH] w1: Userspace communication protocol over connector.
[linux-2.6/verdex.git] / include / asm-i386 / processor.h
blob4df3818e41226e8adb90a57aff788191cf95fd86
1 /*
2 * include/asm-i386/processor.h
4 * Copyright (C) 1994 Linus Torvalds
5 */
7 #ifndef __ASM_I386_PROCESSOR_H
8 #define __ASM_I386_PROCESSOR_H
10 #include <asm/vm86.h>
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/page.h>
14 #include <asm/types.h>
15 #include <asm/sigcontext.h>
16 #include <asm/cpufeature.h>
17 #include <asm/msr.h>
18 #include <asm/system.h>
19 #include <linux/cache.h>
20 #include <linux/threads.h>
21 #include <asm/percpu.h>
22 #include <linux/cpumask.h>
24 /* flag for disabling the tsc */
25 extern int tsc_disable;
27 struct desc_struct {
28 unsigned long a,b;
31 #define desc_empty(desc) \
32 (!((desc)->a | (desc)->b))
34 #define desc_equal(desc1, desc2) \
35 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
37 * Default implementation of macro that returns current
38 * instruction pointer ("program counter").
40 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
43 * CPU type and hardware bug flags. Kept separately for each CPU.
44 * Members of this structure are referenced in head.S, so think twice
45 * before touching them. [mj]
48 struct cpuinfo_x86 {
49 __u8 x86; /* CPU family */
50 __u8 x86_vendor; /* CPU vendor */
51 __u8 x86_model;
52 __u8 x86_mask;
53 char wp_works_ok; /* It doesn't on 386's */
54 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
55 char hard_math;
56 char rfu;
57 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
58 unsigned long x86_capability[NCAPINTS];
59 char x86_vendor_id[16];
60 char x86_model_id[64];
61 int x86_cache_size; /* in KB - valid for CPUS which support this
62 call */
63 int x86_cache_alignment; /* In bytes */
64 char fdiv_bug;
65 char f00f_bug;
66 char coma_bug;
67 char pad0;
68 int x86_power;
69 unsigned long loops_per_jiffy;
70 #ifdef CONFIG_SMP
71 cpumask_t llc_shared_map; /* cpus sharing the last level cache */
72 #endif
73 unsigned char x86_max_cores; /* cpuid returned max cores value */
74 unsigned char booted_cores; /* number of cores as seen by OS */
75 unsigned char apicid;
76 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
78 #define X86_VENDOR_INTEL 0
79 #define X86_VENDOR_CYRIX 1
80 #define X86_VENDOR_AMD 2
81 #define X86_VENDOR_UMC 3
82 #define X86_VENDOR_NEXGEN 4
83 #define X86_VENDOR_CENTAUR 5
84 #define X86_VENDOR_RISE 6
85 #define X86_VENDOR_TRANSMETA 7
86 #define X86_VENDOR_NSC 8
87 #define X86_VENDOR_NUM 9
88 #define X86_VENDOR_UNKNOWN 0xff
91 * capabilities of CPUs
94 extern struct cpuinfo_x86 boot_cpu_data;
95 extern struct cpuinfo_x86 new_cpu_data;
96 extern struct tss_struct doublefault_tss;
97 DECLARE_PER_CPU(struct tss_struct, init_tss);
99 #ifdef CONFIG_SMP
100 extern struct cpuinfo_x86 cpu_data[];
101 #define current_cpu_data cpu_data[smp_processor_id()]
102 #else
103 #define cpu_data (&boot_cpu_data)
104 #define current_cpu_data boot_cpu_data
105 #endif
107 extern int phys_proc_id[NR_CPUS];
108 extern int cpu_core_id[NR_CPUS];
109 extern int cpu_llc_id[NR_CPUS];
110 extern char ignore_fpu_irq;
112 extern void identify_cpu(struct cpuinfo_x86 *);
113 extern void print_cpu_info(struct cpuinfo_x86 *);
114 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
116 #ifdef CONFIG_X86_HT
117 extern void detect_ht(struct cpuinfo_x86 *c);
118 #else
119 static inline void detect_ht(struct cpuinfo_x86 *c) {}
120 #endif
123 * EFLAGS bits
125 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
126 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
127 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
128 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
129 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
130 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
131 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
132 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
133 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
134 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
135 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
136 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
137 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
138 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
139 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
140 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
141 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
144 * Generic CPUID function
145 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
146 * resulting in stale register contents being returned.
148 static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
150 __asm__("cpuid"
151 : "=a" (*eax),
152 "=b" (*ebx),
153 "=c" (*ecx),
154 "=d" (*edx)
155 : "0" (op), "c"(0));
158 /* Some CPUID calls want 'count' to be placed in ecx */
159 static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
160 int *edx)
162 __asm__("cpuid"
163 : "=a" (*eax),
164 "=b" (*ebx),
165 "=c" (*ecx),
166 "=d" (*edx)
167 : "0" (op), "c" (count));
171 * CPUID functions returning a single datum
173 static inline unsigned int cpuid_eax(unsigned int op)
175 unsigned int eax;
177 __asm__("cpuid"
178 : "=a" (eax)
179 : "0" (op)
180 : "bx", "cx", "dx");
181 return eax;
183 static inline unsigned int cpuid_ebx(unsigned int op)
185 unsigned int eax, ebx;
187 __asm__("cpuid"
188 : "=a" (eax), "=b" (ebx)
189 : "0" (op)
190 : "cx", "dx" );
191 return ebx;
193 static inline unsigned int cpuid_ecx(unsigned int op)
195 unsigned int eax, ecx;
197 __asm__("cpuid"
198 : "=a" (eax), "=c" (ecx)
199 : "0" (op)
200 : "bx", "dx" );
201 return ecx;
203 static inline unsigned int cpuid_edx(unsigned int op)
205 unsigned int eax, edx;
207 __asm__("cpuid"
208 : "=a" (eax), "=d" (edx)
209 : "0" (op)
210 : "bx", "cx");
211 return edx;
214 #define load_cr3(pgdir) write_cr3(__pa(pgdir))
217 * Intel CPU features in CR4
219 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
220 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
221 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
222 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
223 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
224 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
225 #define X86_CR4_MCE 0x0040 /* Machine check enable */
226 #define X86_CR4_PGE 0x0080 /* enable global pages */
227 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
228 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
229 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
232 * Save the cr4 feature set we're using (ie
233 * Pentium 4MB enable and PPro Global page
234 * enable), so that any CPU's that boot up
235 * after us can get the correct flags.
237 extern unsigned long mmu_cr4_features;
239 static inline void set_in_cr4 (unsigned long mask)
241 unsigned cr4;
242 mmu_cr4_features |= mask;
243 cr4 = read_cr4();
244 cr4 |= mask;
245 write_cr4(cr4);
248 static inline void clear_in_cr4 (unsigned long mask)
250 unsigned cr4;
251 mmu_cr4_features &= ~mask;
252 cr4 = read_cr4();
253 cr4 &= ~mask;
254 write_cr4(cr4);
258 * NSC/Cyrix CPU configuration register indexes
261 #define CX86_PCR0 0x20
262 #define CX86_GCR 0xb8
263 #define CX86_CCR0 0xc0
264 #define CX86_CCR1 0xc1
265 #define CX86_CCR2 0xc2
266 #define CX86_CCR3 0xc3
267 #define CX86_CCR4 0xe8
268 #define CX86_CCR5 0xe9
269 #define CX86_CCR6 0xea
270 #define CX86_CCR7 0xeb
271 #define CX86_PCR1 0xf0
272 #define CX86_DIR0 0xfe
273 #define CX86_DIR1 0xff
274 #define CX86_ARR_BASE 0xc4
275 #define CX86_RCR_BASE 0xdc
278 * NSC/Cyrix CPU indexed register access macros
281 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
283 #define setCx86(reg, data) do { \
284 outb((reg), 0x22); \
285 outb((data), 0x23); \
286 } while (0)
288 /* Stop speculative execution */
289 static inline void sync_core(void)
291 int tmp;
292 asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
295 static inline void __monitor(const void *eax, unsigned long ecx,
296 unsigned long edx)
298 /* "monitor %eax,%ecx,%edx;" */
299 asm volatile(
300 ".byte 0x0f,0x01,0xc8;"
301 : :"a" (eax), "c" (ecx), "d"(edx));
304 static inline void __mwait(unsigned long eax, unsigned long ecx)
306 /* "mwait %eax,%ecx;" */
307 asm volatile(
308 ".byte 0x0f,0x01,0xc9;"
309 : :"a" (eax), "c" (ecx));
312 /* from system description table in BIOS. Mostly for MCA use, but
313 others may find it useful. */
314 extern unsigned int machine_id;
315 extern unsigned int machine_submodel_id;
316 extern unsigned int BIOS_revision;
317 extern unsigned int mca_pentium_flag;
319 /* Boot loader type from the setup header */
320 extern int bootloader_type;
323 * User space process size: 3GB (default).
325 #define TASK_SIZE (PAGE_OFFSET)
327 /* This decides where the kernel will search for a free chunk of vm
328 * space during mmap's.
330 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
332 #define HAVE_ARCH_PICK_MMAP_LAYOUT
335 * Size of io_bitmap.
337 #define IO_BITMAP_BITS 65536
338 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
339 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
340 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
341 #define INVALID_IO_BITMAP_OFFSET 0x8000
342 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
344 struct i387_fsave_struct {
345 long cwd;
346 long swd;
347 long twd;
348 long fip;
349 long fcs;
350 long foo;
351 long fos;
352 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
353 long status; /* software status information */
356 struct i387_fxsave_struct {
357 unsigned short cwd;
358 unsigned short swd;
359 unsigned short twd;
360 unsigned short fop;
361 long fip;
362 long fcs;
363 long foo;
364 long fos;
365 long mxcsr;
366 long mxcsr_mask;
367 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
368 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
369 long padding[56];
370 } __attribute__ ((aligned (16)));
372 struct i387_soft_struct {
373 long cwd;
374 long swd;
375 long twd;
376 long fip;
377 long fcs;
378 long foo;
379 long fos;
380 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
381 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
382 struct info *info;
383 unsigned long entry_eip;
386 union i387_union {
387 struct i387_fsave_struct fsave;
388 struct i387_fxsave_struct fxsave;
389 struct i387_soft_struct soft;
392 typedef struct {
393 unsigned long seg;
394 } mm_segment_t;
396 struct thread_struct;
398 struct tss_struct {
399 unsigned short back_link,__blh;
400 unsigned long esp0;
401 unsigned short ss0,__ss0h;
402 unsigned long esp1;
403 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
404 unsigned long esp2;
405 unsigned short ss2,__ss2h;
406 unsigned long __cr3;
407 unsigned long eip;
408 unsigned long eflags;
409 unsigned long eax,ecx,edx,ebx;
410 unsigned long esp;
411 unsigned long ebp;
412 unsigned long esi;
413 unsigned long edi;
414 unsigned short es, __esh;
415 unsigned short cs, __csh;
416 unsigned short ss, __ssh;
417 unsigned short ds, __dsh;
418 unsigned short fs, __fsh;
419 unsigned short gs, __gsh;
420 unsigned short ldt, __ldth;
421 unsigned short trace, io_bitmap_base;
423 * The extra 1 is there because the CPU will access an
424 * additional byte beyond the end of the IO permission
425 * bitmap. The extra byte must be all 1 bits, and must
426 * be within the limit.
428 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
430 * Cache the current maximum and the last task that used the bitmap:
432 unsigned long io_bitmap_max;
433 struct thread_struct *io_bitmap_owner;
435 * pads the TSS to be cacheline-aligned (size is 0x100)
437 unsigned long __cacheline_filler[35];
439 * .. and then another 0x100 bytes for emergency kernel stack
441 unsigned long stack[64];
442 } __attribute__((packed));
444 #define ARCH_MIN_TASKALIGN 16
446 struct thread_struct {
447 /* cached TLS descriptors. */
448 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
449 unsigned long esp0;
450 unsigned long sysenter_cs;
451 unsigned long eip;
452 unsigned long esp;
453 unsigned long fs;
454 unsigned long gs;
455 /* Hardware debugging registers */
456 unsigned long debugreg[8]; /* %%db0-7 debug registers */
457 /* fault info */
458 unsigned long cr2, trap_no, error_code;
459 /* floating point info */
460 union i387_union i387;
461 /* virtual 86 mode info */
462 struct vm86_struct __user * vm86_info;
463 unsigned long screen_bitmap;
464 unsigned long v86flags, v86mask, saved_esp0;
465 unsigned int saved_fs, saved_gs;
466 /* IO permissions */
467 unsigned long *io_bitmap_ptr;
468 unsigned long iopl;
469 /* max allowed port in the bitmap, in bytes: */
470 unsigned long io_bitmap_max;
473 #define INIT_THREAD { \
474 .vm86_info = NULL, \
475 .sysenter_cs = __KERNEL_CS, \
476 .io_bitmap_ptr = NULL, \
480 * Note that the .io_bitmap member must be extra-big. This is because
481 * the CPU will access an additional byte beyond the end of the IO
482 * permission bitmap. The extra byte must be all 1 bits, and must
483 * be within the limit.
485 #define INIT_TSS { \
486 .esp0 = sizeof(init_stack) + (long)&init_stack, \
487 .ss0 = __KERNEL_DS, \
488 .ss1 = __KERNEL_CS, \
489 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
490 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
493 static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
495 tss->esp0 = thread->esp0;
496 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
497 if (unlikely(tss->ss1 != thread->sysenter_cs)) {
498 tss->ss1 = thread->sysenter_cs;
499 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
503 #define start_thread(regs, new_eip, new_esp) do { \
504 __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \
505 set_fs(USER_DS); \
506 regs->xds = __USER_DS; \
507 regs->xes = __USER_DS; \
508 regs->xss = __USER_DS; \
509 regs->xcs = __USER_CS; \
510 regs->eip = new_eip; \
511 regs->esp = new_esp; \
512 } while (0)
515 * These special macros can be used to get or set a debugging register
517 #define get_debugreg(var, register) \
518 __asm__("movl %%db" #register ", %0" \
519 :"=r" (var))
520 #define set_debugreg(value, register) \
521 __asm__("movl %0,%%db" #register \
522 : /* no output */ \
523 :"r" (value))
526 * Set IOPL bits in EFLAGS from given mask
528 static inline void set_iopl_mask(unsigned mask)
530 unsigned int reg;
531 __asm__ __volatile__ ("pushfl;"
532 "popl %0;"
533 "andl %1, %0;"
534 "orl %2, %0;"
535 "pushl %0;"
536 "popfl"
537 : "=&r" (reg)
538 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
541 /* Forward declaration, a strange C thing */
542 struct task_struct;
543 struct mm_struct;
545 /* Free all resources held by a thread. */
546 extern void release_thread(struct task_struct *);
548 /* Prepare to copy thread state - unlazy all lazy status */
549 extern void prepare_to_copy(struct task_struct *tsk);
552 * create a kernel thread without removing it from tasklists
554 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
556 extern unsigned long thread_saved_pc(struct task_struct *tsk);
557 void show_trace(struct task_struct *task, unsigned long *stack);
559 unsigned long get_wchan(struct task_struct *p);
561 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
562 #define KSTK_TOP(info) \
563 ({ \
564 unsigned long *__ptr = (unsigned long *)(info); \
565 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
569 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
570 * This is necessary to guarantee that the entire "struct pt_regs"
571 * is accessable even if the CPU haven't stored the SS/ESP registers
572 * on the stack (interrupt gate does not save these registers
573 * when switching to the same priv ring).
574 * Therefore beware: accessing the xss/esp fields of the
575 * "struct pt_regs" is possible, but they may contain the
576 * completely wrong values.
578 #define task_pt_regs(task) \
579 ({ \
580 struct pt_regs *__regs__; \
581 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
582 __regs__ - 1; \
585 #define KSTK_EIP(task) (task_pt_regs(task)->eip)
586 #define KSTK_ESP(task) (task_pt_regs(task)->esp)
589 struct microcode_header {
590 unsigned int hdrver;
591 unsigned int rev;
592 unsigned int date;
593 unsigned int sig;
594 unsigned int cksum;
595 unsigned int ldrver;
596 unsigned int pf;
597 unsigned int datasize;
598 unsigned int totalsize;
599 unsigned int reserved[3];
602 struct microcode {
603 struct microcode_header hdr;
604 unsigned int bits[0];
607 typedef struct microcode microcode_t;
608 typedef struct microcode_header microcode_header_t;
610 /* microcode format is extended from prescott processors */
611 struct extended_signature {
612 unsigned int sig;
613 unsigned int pf;
614 unsigned int cksum;
617 struct extended_sigtable {
618 unsigned int count;
619 unsigned int cksum;
620 unsigned int reserved[3];
621 struct extended_signature sigs[0];
624 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
625 static inline void rep_nop(void)
627 __asm__ __volatile__("rep;nop": : :"memory");
630 #define cpu_relax() rep_nop()
632 /* generic versions from gas */
633 #define GENERIC_NOP1 ".byte 0x90\n"
634 #define GENERIC_NOP2 ".byte 0x89,0xf6\n"
635 #define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
636 #define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
637 #define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
638 #define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
639 #define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
640 #define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
642 /* Opteron nops */
643 #define K8_NOP1 GENERIC_NOP1
644 #define K8_NOP2 ".byte 0x66,0x90\n"
645 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
646 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
647 #define K8_NOP5 K8_NOP3 K8_NOP2
648 #define K8_NOP6 K8_NOP3 K8_NOP3
649 #define K8_NOP7 K8_NOP4 K8_NOP3
650 #define K8_NOP8 K8_NOP4 K8_NOP4
652 /* K7 nops */
653 /* uses eax dependencies (arbitary choice) */
654 #define K7_NOP1 GENERIC_NOP1
655 #define K7_NOP2 ".byte 0x8b,0xc0\n"
656 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
657 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
658 #define K7_NOP5 K7_NOP4 ASM_NOP1
659 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
660 #define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
661 #define K7_NOP8 K7_NOP7 ASM_NOP1
663 #ifdef CONFIG_MK8
664 #define ASM_NOP1 K8_NOP1
665 #define ASM_NOP2 K8_NOP2
666 #define ASM_NOP3 K8_NOP3
667 #define ASM_NOP4 K8_NOP4
668 #define ASM_NOP5 K8_NOP5
669 #define ASM_NOP6 K8_NOP6
670 #define ASM_NOP7 K8_NOP7
671 #define ASM_NOP8 K8_NOP8
672 #elif defined(CONFIG_MK7)
673 #define ASM_NOP1 K7_NOP1
674 #define ASM_NOP2 K7_NOP2
675 #define ASM_NOP3 K7_NOP3
676 #define ASM_NOP4 K7_NOP4
677 #define ASM_NOP5 K7_NOP5
678 #define ASM_NOP6 K7_NOP6
679 #define ASM_NOP7 K7_NOP7
680 #define ASM_NOP8 K7_NOP8
681 #else
682 #define ASM_NOP1 GENERIC_NOP1
683 #define ASM_NOP2 GENERIC_NOP2
684 #define ASM_NOP3 GENERIC_NOP3
685 #define ASM_NOP4 GENERIC_NOP4
686 #define ASM_NOP5 GENERIC_NOP5
687 #define ASM_NOP6 GENERIC_NOP6
688 #define ASM_NOP7 GENERIC_NOP7
689 #define ASM_NOP8 GENERIC_NOP8
690 #endif
692 #define ASM_NOP_MAX 8
694 /* Prefetch instructions for Pentium III and AMD Athlon */
695 /* It's not worth to care about 3dnow! prefetches for the K6
696 because they are microcoded there and very slow.
697 However we don't do prefetches for pre XP Athlons currently
698 That should be fixed. */
699 #define ARCH_HAS_PREFETCH
700 static inline void prefetch(const void *x)
702 alternative_input(ASM_NOP4,
703 "prefetchnta (%1)",
704 X86_FEATURE_XMM,
705 "r" (x));
708 #define ARCH_HAS_PREFETCH
709 #define ARCH_HAS_PREFETCHW
710 #define ARCH_HAS_SPINLOCK_PREFETCH
712 /* 3dnow! prefetch to get an exclusive cache line. Useful for
713 spinlocks to avoid one state transition in the cache coherency protocol. */
714 static inline void prefetchw(const void *x)
716 alternative_input(ASM_NOP4,
717 "prefetchw (%1)",
718 X86_FEATURE_3DNOW,
719 "r" (x));
721 #define spin_lock_prefetch(x) prefetchw(x)
723 extern void select_idle_routine(const struct cpuinfo_x86 *c);
725 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
727 extern unsigned long boot_option_idle_override;
728 extern void enable_sep_cpu(void);
729 extern int sysenter_setup(void);
731 #ifdef CONFIG_MTRR
732 extern void mtrr_ap_init(void);
733 extern void mtrr_bp_init(void);
734 #else
735 #define mtrr_ap_init() do {} while (0)
736 #define mtrr_bp_init() do {} while (0)
737 #endif
739 #ifdef CONFIG_X86_MCE
740 extern void mcheck_init(struct cpuinfo_x86 *c);
741 #else
742 #define mcheck_init(c) do {} while(0)
743 #endif
745 #endif /* __ASM_I386_PROCESSOR_H */