1 #ifndef _M68KNOMMU_SYSTEM_H
2 #define _M68KNOMMU_SYSTEM_H
4 #include <linux/linkage.h>
5 #include <asm/segment.h>
9 * switch_to(n) should switch tasks to task ptr, first checking that
10 * ptr isn't the current task, in which case it does nothing. This
11 * also clears the TS-flag if the task we switched to has used the
12 * math co-processor latest.
15 * switch_to() saves the extra registers, that are not saved
16 * automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and
17 * a0-a1. Some of these are used by schedule() and its predecessors
18 * and so we might get see unexpected behaviors when a task returns
19 * with unexpected register values.
21 * syscall stores these registers itself and none of them are used
22 * by syscall after the function in the syscall has been called.
24 * Beware that resume now expects *next to be in d1 and the offset of
25 * tss to be in a1. This saves a few instructions as we no longer have
26 * to push them onto the stack and read them back right after.
28 * 02/17/96 - Jes Sorensen (jds@kom.auc.dk)
30 * Changed 96/09/19 by Andreas Schwab
31 * pass prev in a0, next in a1, offset of tss in d1, and whether
32 * the mm structures are shared in d2 (to avoid atc flushing).
34 asmlinkage
void resume(void);
35 #define switch_to(prev,next,last) \
38 __asm__ __volatile__( \
39 "movel %1, %%a0\n\t" \
40 "movel %2, %%a1\n\t" \
42 "movel %%d1, %0\n\t" \
44 : "d" (prev), "d" (next) \
45 : "cc", "d0", "d1", "d2", "d3", "d4", "d5", "a0", "a1"); \
49 #ifdef CONFIG_COLDFIRE
50 #define local_irq_enable() __asm__ __volatile__ ( \
51 "move %/sr,%%d0\n\t" \
52 "andi.l #0xf8ff,%%d0\n\t" \
56 : "cc", "%d0", "memory")
57 #define local_irq_disable() __asm__ __volatile__ ( \
58 "move %/sr,%%d0\n\t" \
59 "ori.l #0x0700,%%d0\n\t" \
63 : "cc", "%d0", "memory")
64 /* For spinlocks etc */
65 #define local_irq_save(x) __asm__ __volatile__ ( \
67 "movew #0x0700,%%d0\n\t" \
72 : "cc", "%d0", "memory")
75 /* portable version */ /* FIXME - see entry.h*/
76 #define ALLOWINT 0xf8ff
78 #define local_irq_enable() asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory")
79 #define local_irq_disable() asm volatile ("oriw #0x0700,%%sr": : : "memory")
82 #define local_save_flags(x) asm volatile ("movew %%sr,%0":"=d" (x) : : "memory")
83 #define local_irq_restore(x) asm volatile ("movew %0,%%sr": :"d" (x) : "memory")
85 /* For spinlocks etc */
86 #ifndef local_irq_save
87 #define local_irq_save(x) do { local_save_flags(x); local_irq_disable(); } while (0)
90 #define irqs_disabled() \
92 unsigned long flags; \
93 local_save_flags(flags); \
94 ((flags & 0x0700) == 0x0700); \
97 #define iret() __asm__ __volatile__ ("rte": : :"memory", "sp", "cc")
100 * Force strict CPU ordering.
101 * Not really required on m68k...
103 #define nop() asm volatile ("nop"::)
104 #define mb() asm volatile ("" : : :"memory")
105 #define rmb() asm volatile ("" : : :"memory")
106 #define wmb() asm volatile ("" : : :"memory")
107 #define set_rmb(var, value) do { xchg(&var, value); } while (0)
108 #define set_mb(var, value) set_rmb(var, value)
109 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
112 #define smp_mb() mb()
113 #define smp_rmb() rmb()
114 #define smp_wmb() wmb()
115 #define smp_read_barrier_depends() read_barrier_depends()
117 #define smp_mb() barrier()
118 #define smp_rmb() barrier()
119 #define smp_wmb() barrier()
120 #define smp_read_barrier_depends() do { } while(0)
123 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
124 #define tas(ptr) (xchg((ptr),1))
126 struct __xchg_dummy
{ unsigned long a
[100]; };
127 #define __xg(x) ((volatile struct __xchg_dummy *)(x))
129 #ifndef CONFIG_RMW_INSNS
130 static inline unsigned long __xchg(unsigned long x
, volatile void * ptr
, int size
)
132 unsigned long tmp
, flags
;
134 local_irq_save(flags
);
141 : "=&d" (tmp
) : "d" (x
), "m" (*__xg(ptr
)) : "memory");
147 : "=&d" (tmp
) : "d" (x
), "m" (*__xg(ptr
)) : "memory");
153 : "=&d" (tmp
) : "d" (x
), "m" (*__xg(ptr
)) : "memory");
156 local_irq_restore(flags
);
160 static inline unsigned long __xchg(unsigned long x
, volatile void * ptr
, int size
)
169 : "=&d" (x
) : "d" (x
), "m" (*__xg(ptr
)) : "memory");
177 : "=&d" (x
) : "d" (x
), "m" (*__xg(ptr
)) : "memory");
185 : "=&d" (x
) : "d" (x
), "m" (*__xg(ptr
)) : "memory");
193 * Atomic compare and exchange. Compare OLD with MEM, if identical,
194 * store NEW in MEM. Return the initial value in MEM. Success is
195 * indicated by comparing RETURN with OLD.
197 #define __HAVE_ARCH_CMPXCHG 1
199 static __inline__
unsigned long
200 cmpxchg(volatile int *p
, int old
, int new)
205 local_irq_save(flags
);
206 if ((prev
= *p
) == old
)
208 local_irq_restore(flags
);
214 #define HARD_RESET_NOW() ({ \
215 local_irq_disable(); \
217 movew #0x0000, 0xfffa6a; \
219 /*movew #0x1557, 0xfffa44;*/ \
220 /*movew #0x0155, 0xfffa46;*/ \
230 #if defined( CONFIG_M68328 ) || defined( CONFIG_M68EZ328 ) || \
231 defined (CONFIG_M68360) || defined( CONFIG_M68VZ328 )
232 #define HARD_RESET_NOW() ({ \
233 local_irq_disable(); \
235 moveal #0x10c00000, %a0; \
236 moveb #0, 0xFFFFF300; \
237 moveal 0(%a0), %sp; \
238 moveal 4(%a0), %a0; \
244 #ifdef CONFIG_COLDFIRE
245 #if defined(CONFIG_M5272) && defined(CONFIG_NETtel)
247 * Need to account for broken early mask of 5272 silicon. So don't
248 * jump through the original start address. Jump strait into the
249 * known start of the FLASH code.
251 #define HARD_RESET_NOW() ({ \
253 movew #0x2700, %sr; \
257 #elif defined(CONFIG_NETtel) || defined(CONFIG_eLIA) || \
258 defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3) || \
259 defined(CONFIG_CLEOPATRA)
260 #define HARD_RESET_NOW() ({ \
262 movew #0x2700, %sr; \
263 moveal #0x10000044, %a0; \
264 movel #0xffffffff, (%a0); \
265 moveal #0x10000001, %a0; \
266 moveb #0x00, (%a0); \
267 moveal #0xf0000004, %a0; \
272 #elif defined(CONFIG_M5272)
274 * Retrieve the boot address in flash using CSBR0 and CSOR0
275 * find the reset vector at flash_address + 4 (e.g. 0x400)
276 * remap it in the flash's current location (e.g. 0xf0000400)
279 #define HARD_RESET_NOW() ({ \
281 movew #0x2700, %%sr; \
282 move.l %0+0x40,%%d0; \
283 and.l %0+0x44,%%d0; \
284 andi.l #0xfffff000,%%d0; \
290 : "o" (*(char *)MCF_MBAR) ); \
292 #elif defined(CONFIG_M528x)
294 * The MCF528x has a bit (SOFTRST) in memory (Reset Control Register RCR),
295 * that when set, resets the MCF528x.
297 #define HARD_RESET_NOW() \
299 unsigned char volatile *reset; \
300 asm("move.w #0x2700, %sr"); \
301 reset = ((volatile unsigned short *)(MCF_IPSBAR + 0x110000)); \
303 *reset |= (0x01 << 7);\
305 #elif defined(CONFIG_M523x)
306 #define HARD_RESET_NOW() ({ \
308 movew #0x2700, %sr; \
309 movel #0x01000000, %sp; \
310 moveal #0x40110000, %a0; \
311 moveb #0x80, (%a0); \
314 #elif defined(CONFIG_M520x)
316 * The MCF5208 has a bit (SOFTRST) in memory (Reset Control Register
317 * RCR), that when set, resets the MCF5208.
319 #define HARD_RESET_NOW() \
321 unsigned char volatile *reset; \
322 asm("move.w #0x2700, %sr"); \
323 reset = ((volatile unsigned short *)(MCF_IPSBAR + 0xA0000)); \
328 #define HARD_RESET_NOW() ({ \
330 movew #0x2700, %sr; \
338 #define arch_align_stack(x) (x)
340 #endif /* _M68KNOMMU_SYSTEM_H */