include/asm-ppc/mpc85xx.h

   1 /*
   2  * include/asm-ppc/mpc85xx.h
   3  *
   4  * MPC85xx definitions
   5  *
   6  * Maintainer: Kumar Gala <galak@kernel.crashing.org>
   7  *
   8  * Copyright 2004 Freescale Semiconductor, Inc
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #ifdef __KERNEL__
  17 #ifndef __ASM_MPC85xx_H__
  18 #define __ASM_MPC85xx_H__
  19
  20 #include <asm/mmu.h>
  21
  22 #ifdef CONFIG_85xx
  23
  24 #ifdef CONFIG_MPC8540_ADS
  25 #include <platforms/85xx/mpc8540_ads.h>
  26 #endif
  27 #if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
  28 #include <platforms/85xx/mpc8555_cds.h>
  29 #endif
  30 #ifdef CONFIG_MPC8560_ADS
  31 #include <platforms/85xx/mpc8560_ads.h>
  32 #endif
  33 #ifdef CONFIG_SBC8560
  34 #include <platforms/85xx/sbc8560.h>
  35 #endif
  36 #ifdef CONFIG_STX_GP3
  37 #include <platforms/85xx/stx_gp3.h>
  38 #endif
  39 #if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8541) || \
  40         defined(CONFIG_TQM8555) || defined(CONFIG_TQM8560)
  41 #include <platforms/85xx/tqm85xx.h>
  42 #endif
  43
  44 #define _IO_BASE        isa_io_base
  45 #define _ISA_MEM_BASE   isa_mem_base
  46 #ifdef CONFIG_PCI
  47 #define PCI_DRAM_OFFSET pci_dram_offset
  48 #else
  49 #define PCI_DRAM_OFFSET 0
  50 #endif
  51
  52 /*
  53  * The "residual" board information structure the boot loader passes
  54  * into the kernel.
  55  */
  56 extern unsigned char __res[];
  57
  58 /* Offset from CCSRBAR */
  59 #define MPC85xx_CPM_OFFSET      (0x80000)
  60 #define MPC85xx_CPM_SIZE        (0x40000)
  61 #define MPC85xx_DMA_OFFSET      (0x21000)
  62 #define MPC85xx_DMA_SIZE        (0x01000)
  63 #define MPC85xx_DMA0_OFFSET     (0x21100)
  64 #define MPC85xx_DMA0_SIZE       (0x00080)
  65 #define MPC85xx_DMA1_OFFSET     (0x21180)
  66 #define MPC85xx_DMA1_SIZE       (0x00080)
  67 #define MPC85xx_DMA2_OFFSET     (0x21200)
  68 #define MPC85xx_DMA2_SIZE       (0x00080)
  69 #define MPC85xx_DMA3_OFFSET     (0x21280)
  70 #define MPC85xx_DMA3_SIZE       (0x00080)
  71 #define MPC85xx_ENET1_OFFSET    (0x24000)
  72 #define MPC85xx_ENET1_SIZE      (0x01000)
  73 #define MPC85xx_MIIM_OFFSET     (0x24520)
  74 #define MPC85xx_MIIM_SIZE       (0x00018)
  75 #define MPC85xx_ENET2_OFFSET    (0x25000)
  76 #define MPC85xx_ENET2_SIZE      (0x01000)
  77 #define MPC85xx_ENET3_OFFSET    (0x26000)
  78 #define MPC85xx_ENET3_SIZE      (0x01000)
  79 #define MPC85xx_GUTS_OFFSET     (0xe0000)
  80 #define MPC85xx_GUTS_SIZE       (0x01000)
  81 #define MPC85xx_IIC1_OFFSET     (0x03000)
  82 #define MPC85xx_IIC1_SIZE       (0x00100)
  83 #define MPC85xx_OPENPIC_OFFSET  (0x40000)
  84 #define MPC85xx_OPENPIC_SIZE    (0x40000)
  85 #define MPC85xx_PCI1_OFFSET     (0x08000)
  86 #define MPC85xx_PCI1_SIZE       (0x01000)
  87 #define MPC85xx_PCI2_OFFSET     (0x09000)
  88 #define MPC85xx_PCI2_SIZE       (0x01000)
  89 #define MPC85xx_PERFMON_OFFSET  (0xe1000)
  90 #define MPC85xx_PERFMON_SIZE    (0x01000)
  91 #define MPC85xx_SEC2_OFFSET     (0x30000)
  92 #define MPC85xx_SEC2_SIZE       (0x10000)
  93 #define MPC85xx_UART0_OFFSET    (0x04500)
  94 #define MPC85xx_UART0_SIZE      (0x00100)
  95 #define MPC85xx_UART1_OFFSET    (0x04600)
  96 #define MPC85xx_UART1_SIZE      (0x00100)
  97
  98 #define MPC85xx_CCSRBAR_SIZE    (1024*1024)
  99
 100 /* Let modules/drivers get at CCSRBAR */
 101 extern phys_addr_t get_ccsrbar(void);
 102
 103 #ifdef MODULE
 104 #define CCSRBAR get_ccsrbar()
 105 #else
 106 #define CCSRBAR BOARD_CCSRBAR
 107 #endif
 108
 109 enum ppc_sys_devices {
 110         MPC85xx_TSEC1,
 111         MPC85xx_TSEC2,
 112         MPC85xx_FEC,
 113         MPC85xx_IIC1,
 114         MPC85xx_DMA0,
 115         MPC85xx_DMA1,
 116         MPC85xx_DMA2,
 117         MPC85xx_DMA3,
 118         MPC85xx_DUART,
 119         MPC85xx_PERFMON,
 120         MPC85xx_SEC2,
 121         MPC85xx_CPM_SPI,
 122         MPC85xx_CPM_I2C,
 123         MPC85xx_CPM_USB,
 124         MPC85xx_CPM_SCC1,
 125         MPC85xx_CPM_SCC2,
 126         MPC85xx_CPM_SCC3,
 127         MPC85xx_CPM_SCC4,
 128         MPC85xx_CPM_FCC1,
 129         MPC85xx_CPM_FCC2,
 130         MPC85xx_CPM_FCC3,
 131         MPC85xx_CPM_MCC1,
 132         MPC85xx_CPM_MCC2,
 133         MPC85xx_CPM_SMC1,
 134         MPC85xx_CPM_SMC2,
 135         MPC85xx_eTSEC1,
 136         MPC85xx_eTSEC2,
 137         MPC85xx_eTSEC3,
 138         MPC85xx_eTSEC4,
 139         MPC85xx_IIC2,
 140         MPC85xx_MDIO,
 141         NUM_PPC_SYS_DEVS,
 142 };
 143
 144 /* Internal interrupts are all Level Sensitive, and Positive Polarity */
 145 #define MPC85XX_INTERNAL_IRQ_SENSES \
 146         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  0 */       \
 147         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  1 */       \
 148         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  2 */       \
 149         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  3 */       \
 150         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  4 */       \
 151         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  5 */       \
 152         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  6 */       \
 153         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  7 */       \
 154         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  8 */       \
 155         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  9 */       \
 156         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 10 */       \
 157         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 11 */       \
 158         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 12 */       \
 159         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 13 */       \
 160         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 14 */       \
 161         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 15 */       \
 162         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 16 */       \
 163         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 17 */       \
 164         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 18 */       \
 165         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 19 */       \
 166         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 20 */       \
 167         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 21 */       \
 168         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 22 */       \
 169         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 23 */       \
 170         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 24 */       \
 171         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 25 */       \
 172         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 26 */       \
 173         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 27 */       \
 174         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 28 */       \
 175         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 29 */       \
 176         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 30 */       \
 177         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 31 */       \
 178         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 32 */       \
 179         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 33 */       \
 180         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 34 */       \
 181         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 35 */       \
 182         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 36 */       \
 183         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 37 */       \
 184         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 38 */       \
 185         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 39 */       \
 186         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 40 */       \
 187         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 41 */       \
 188         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 42 */       \
 189         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 43 */       \
 190         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 44 */       \
 191         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 45 */       \
 192         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 46 */       \
 193         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE)       /* Internal 47 */
 194
 195 #endif /* CONFIG_85xx */
 196 #endif /* __ASM_MPC85xx_H__ */
 197 #endif /* __KERNEL__ */