include/asm-sh/irq.h

   1 #ifndef __ASM_SH_IRQ_H
   2 #define __ASM_SH_IRQ_H
   3
   4 /*
   5  *
   6  * linux/include/asm-sh/irq.h
   7  *
   8  * Copyright (C) 1999  Niibe Yutaka & Takeshi Yaegashi
   9  * Copyright (C) 2000  Kazumoto Kojima
  10  * Copyright (C) 2003  Paul Mundt
  11  *
  12  */
  13
  14 #include <linux/config.h>
  15 #include <asm/machvec.h>
  16 #include <asm/ptrace.h>         /* for pt_regs */
  17
  18 #if defined(CONFIG_SH_HP6XX) || \
  19     defined(CONFIG_SH_RTS7751R2D) || \
  20     defined(CONFIG_SH_HS7751RVOIP) || \
  21     defined(CONFIG_SH_HS7751RVOIP) || \
  22     defined(CONFIG_SH_SH03) || \
  23     defined(CONFIG_SH_R7780RP) || \
  24     defined(CONFIG_SH_LANDISK)
  25 #include <asm/mach/ide.h>
  26 #endif
  27
  28 #ifndef CONFIG_CPU_SUBTYPE_SH7780
  29
  30 #define INTC_DMAC0_MSK  0
  31
  32 #if defined(CONFIG_CPU_SH3)
  33 #define INTC_IPRA       0xfffffee2UL
  34 #define INTC_IPRB       0xfffffee4UL
  35 #elif defined(CONFIG_CPU_SH4)
  36 #define INTC_IPRA       0xffd00004UL
  37 #define INTC_IPRB       0xffd00008UL
  38 #define INTC_IPRC       0xffd0000cUL
  39 #define INTC_IPRD       0xffd00010UL
  40 #endif
  41
  42 #ifdef CONFIG_IDE
  43 # ifndef IRQ_CFCARD
  44 #  define IRQ_CFCARD    14
  45 # endif
  46 # ifndef IRQ_PCMCIA
  47 #  define IRQ_PCMCIA    15
  48 # endif
  49 #endif
  50
  51 #define TIMER_IRQ       16
  52 #define TIMER_IPR_ADDR  INTC_IPRA
  53 #define TIMER_IPR_POS    3
  54 #define TIMER_PRIORITY   2
  55
  56 #define TIMER1_IRQ      17
  57 #define TIMER1_IPR_ADDR INTC_IPRA
  58 #define TIMER1_IPR_POS   2
  59 #define TIMER1_PRIORITY  4
  60
  61 #define RTC_IRQ         22
  62 #define RTC_IPR_ADDR    INTC_IPRA
  63 #define RTC_IPR_POS      0
  64 #define RTC_PRIORITY    TIMER_PRIORITY
  65
  66 #if defined(CONFIG_CPU_SH3)
  67 #define DMTE0_IRQ       48
  68 #define DMTE1_IRQ       49
  69 #define DMTE2_IRQ       50
  70 #define DMTE3_IRQ       51
  71 #define DMA_IPR_ADDR    INTC_IPRE
  72 #define DMA_IPR_POS     3
  73 #define DMA_PRIORITY    7
  74 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
  75 /* TMU2 */
  76 #define TIMER2_IRQ      18
  77 #define TIMER2_IPR_ADDR INTC_IPRA
  78 #define TIMER2_IPR_POS   1
  79 #define TIMER2_PRIORITY  2
  80
  81 /* WDT */
  82 #define WDT_IRQ         27
  83 #define WDT_IPR_ADDR    INTC_IPRB
  84 #define WDT_IPR_POS      3
  85 #define WDT_PRIORITY     2
  86
  87 /* SIM (SIM Card Module) */
  88 #define SIM_ERI_IRQ     23
  89 #define SIM_RXI_IRQ     24
  90 #define SIM_TXI_IRQ     25
  91 #define SIM_TEND_IRQ    26
  92 #define SIM_IPR_ADDR    INTC_IPRB
  93 #define SIM_IPR_POS      1
  94 #define SIM_PRIORITY     2
  95
  96 /* VIO (Video I/O) */
  97 #define VIO_IRQ         52
  98 #define VIO_IPR_ADDR    INTC_IPRE
  99 #define VIO_IPR_POS      2
 100 #define VIO_PRIORITY     2
 101
 102 /* MFI (Multi Functional Interface) */
 103 #define MFI_IRQ         56
 104 #define MFI_IPR_ADDR    INTC_IPRE
 105 #define MFI_IPR_POS      1
 106 #define MFI_PRIORITY     2
 107
 108 /* VPU (Video Processing Unit) */
 109 #define VPU_IRQ         60
 110 #define VPU_IPR_ADDR    INTC_IPRE
 111 #define VPU_IPR_POS      0
 112 #define VPU_PRIORITY     2
 113
 114 /* KEY (Key Scan Interface) */
 115 #define KEY_IRQ         79
 116 #define KEY_IPR_ADDR    INTC_IPRF
 117 #define KEY_IPR_POS      3
 118 #define KEY_PRIORITY     2
 119
 120 /* CMT (Compare Match Timer) */
 121 #define CMT_IRQ         104
 122 #define CMT_IPR_ADDR    INTC_IPRF
 123 #define CMT_IPR_POS      0
 124 #define CMT_PRIORITY     2
 125
 126 /* DMAC(1) */
 127 #define DMTE0_IRQ       48
 128 #define DMTE1_IRQ       49
 129 #define DMTE2_IRQ       50
 130 #define DMTE3_IRQ       51
 131 #define DMA1_IPR_ADDR   INTC_IPRE
 132 #define DMA1_IPR_POS    3
 133 #define DMA1_PRIORITY   7
 134
 135 /* DMAC(2) */
 136 #define DMTE4_IRQ       76
 137 #define DMTE5_IRQ       77
 138 #define DMA2_IPR_ADDR   INTC_IPRF
 139 #define DMA2_IPR_POS    2
 140 #define DMA2_PRIORITY   7
 141
 142 /* SIOF0 */
 143 #define SIOF0_IRQ       84
 144 #define SIOF0_IPR_ADDR  INTC_IPRH
 145 #define SIOF0_IPR_POS   3
 146 #define SIOF0_PRIORITY  3
 147
 148 /* FLCTL (Flash Memory Controller) */
 149 #define FLSTE_IRQ       92
 150 #define FLTEND_IRQ      93
 151 #define FLTRQ0_IRQ      94
 152 #define FLTRQ1_IRQ      95
 153 #define FLCTL_IPR_ADDR  INTC_IPRH
 154 #define FLCTL_IPR_POS   1
 155 #define FLCTL_PRIORITY  3
 156
 157 /* IIC (IIC Bus Interface) */
 158 #define IIC_ALI_IRQ     96
 159 #define IIC_TACKI_IRQ   97
 160 #define IIC_WAITI_IRQ   98
 161 #define IIC_DTEI_IRQ    99
 162 #define IIC_IPR_ADDR    INTC_IPRH
 163 #define IIC_IPR_POS     0
 164 #define IIC_PRIORITY    3
 165
 166 /* SIO0 */
 167 #define SIO0_IRQ        88
 168 #define SIO0_IPR_ADDR   INTC_IPRI
 169 #define SIO0_IPR_POS    3
 170 #define SIO0_PRIORITY   3
 171
 172 /* SIU (Sound Interface Unit) */
 173 #define SIU_IRQ         108
 174 #define SIU_IPR_ADDR    INTC_IPRJ
 175 #define SIU_IPR_POS     1
 176 #define SIU_PRIORITY    3
 177
 178 #endif
 179 #elif defined(CONFIG_CPU_SH4)
 180 #define DMTE0_IRQ       34
 181 #define DMTE1_IRQ       35
 182 #define DMTE2_IRQ       36
 183 #define DMTE3_IRQ       37
 184 #define DMTE4_IRQ       44      /* 7751R only */
 185 #define DMTE5_IRQ       45      /* 7751R only */
 186 #define DMTE6_IRQ       46      /* 7751R only */
 187 #define DMTE7_IRQ       47      /* 7751R only */
 188 #define DMAE_IRQ        38
 189 #define DMA_IPR_ADDR    INTC_IPRC
 190 #define DMA_IPR_POS     2
 191 #define DMA_PRIORITY    7
 192 #endif
 193
 194 #if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \
 195     defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \
 196     defined (CONFIG_CPU_SUBTYPE_SH7751)
 197 #define SCI_ERI_IRQ     23
 198 #define SCI_RXI_IRQ     24
 199 #define SCI_TXI_IRQ     25
 200 #define SCI_IPR_ADDR    INTC_IPRB
 201 #define SCI_IPR_POS     1
 202 #define SCI_PRIORITY    3
 203 #endif
 204
 205 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
 206 #define SCIF0_IRQ       80
 207 #define SCIF0_IPR_ADDR  INTC_IPRG
 208 #define SCIF0_IPR_POS   3
 209 #define SCIF0_PRIORITY  3
 210 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 211       defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 212       defined(CONFIG_CPU_SUBTYPE_SH7709)
 213 #define SCIF_ERI_IRQ    56
 214 #define SCIF_RXI_IRQ    57
 215 #define SCIF_BRI_IRQ    58
 216 #define SCIF_TXI_IRQ    59
 217 #define SCIF_IPR_ADDR   INTC_IPRE
 218 #define SCIF_IPR_POS    1
 219 #define SCIF_PRIORITY   3
 220
 221 #define IRDA_ERI_IRQ    52
 222 #define IRDA_RXI_IRQ    53
 223 #define IRDA_BRI_IRQ    54
 224 #define IRDA_TXI_IRQ    55
 225 #define IRDA_IPR_ADDR   INTC_IPRE
 226 #define IRDA_IPR_POS    2
 227 #define IRDA_PRIORITY   3
 228 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 229       defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
 230 #define SCIF_ERI_IRQ    40
 231 #define SCIF_RXI_IRQ    41
 232 #define SCIF_BRI_IRQ    42
 233 #define SCIF_TXI_IRQ    43
 234 #define SCIF_IPR_ADDR   INTC_IPRC
 235 #define SCIF_IPR_POS    1
 236 #define SCIF_PRIORITY   3
 237 #if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
 238 #define SCIF1_ERI_IRQ   23
 239 #define SCIF1_RXI_IRQ   24
 240 #define SCIF1_BRI_IRQ   25
 241 #define SCIF1_TXI_IRQ   26
 242 #define SCIF1_IPR_ADDR  INTC_IPRB
 243 #define SCIF1_IPR_POS   1
 244 #define SCIF1_PRIORITY  3
 245 #endif /* ST40STB1 */
 246
 247 #endif /* 775x / SH4-202 / ST40STB1 */
 248
 249 /* NR_IRQS is made from three components:
 250  *   1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
 251  *   2. PINT_NR_IRQS   - number of PINT interrupts
 252  *   3. OFFCHIP_NR_IRQS - numbe of IRQs from off-chip peripherial modules
 253  */
 254
 255 /* 1. ONCHIP_NR_IRQS */
 256 #if defined(CONFIG_CPU_SUBTYPE_SH7604)
 257 # define ONCHIP_NR_IRQS 24      // Actually 21
 258 #elif defined(CONFIG_CPU_SUBTYPE_SH7707)
 259 # define ONCHIP_NR_IRQS 64
 260 # define PINT_NR_IRQS   16
 261 #elif defined(CONFIG_CPU_SUBTYPE_SH7708)
 262 # define ONCHIP_NR_IRQS 32
 263 #elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
 264       defined(CONFIG_CPU_SUBTYPE_SH7705)
 265 # define ONCHIP_NR_IRQS 64      // Actually 61
 266 # define PINT_NR_IRQS   16
 267 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)
 268 # define ONCHIP_NR_IRQS 48      // Actually 44
 269 #elif defined(CONFIG_CPU_SUBTYPE_SH7751)
 270 # define ONCHIP_NR_IRQS 72
 271 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
 272 # define ONCHIP_NR_IRQS 112     /* XXX */
 273 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
 274 # define ONCHIP_NR_IRQS 72
 275 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
 276 # define ONCHIP_NR_IRQS 144
 277 #elif defined(CONFIG_CPU_SUBTYPE_SH7300)
 278 # define ONCHIP_NR_IRQS 109
 279 #elif defined(CONFIG_SH_UNKNOWN)        /* Most be last */
 280 # define ONCHIP_NR_IRQS 144
 281 #endif
 282
 283 /* 2. PINT_NR_IRQS */
 284 #ifdef CONFIG_SH_UNKNOWN
 285 # define PINT_NR_IRQS 16
 286 #else
 287 # ifndef PINT_NR_IRQS
 288 #  define PINT_NR_IRQS 0
 289 # endif
 290 #endif
 291
 292 #if PINT_NR_IRQS > 0
 293 # define PINT_IRQ_BASE  ONCHIP_NR_IRQS
 294 #endif
 295
 296 /* 3. OFFCHIP_NR_IRQS */
 297 #if defined(CONFIG_HD64461)
 298 # define OFFCHIP_NR_IRQS 18
 299 #elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */
 300 # define OFFCHIP_NR_IRQS 48
 301 #elif defined(CONFIG_HD64465)
 302 # define OFFCHIP_NR_IRQS 16
 303 #elif defined (CONFIG_SH_EC3104)
 304 # define OFFCHIP_NR_IRQS 16
 305 #elif defined (CONFIG_SH_DREAMCAST)
 306 # define OFFCHIP_NR_IRQS 96
 307 #elif defined (CONFIG_SH_TITAN)
 308 # define OFFCHIP_NR_IRQS 4
 309 #elif defined(CONFIG_SH_UNKNOWN)
 310 # define OFFCHIP_NR_IRQS 16     /* Must also be last */
 311 #else
 312 # define OFFCHIP_NR_IRQS 0
 313 #endif
 314
 315 #if OFFCHIP_NR_IRQS > 0
 316 # define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS)
 317 #endif
 318
 319 /* NR_IRQS. 1+2+3 */
 320 #define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
 321
 322 extern void disable_irq(unsigned int);
 323 extern void disable_irq_nosync(unsigned int);
 324 extern void enable_irq(unsigned int);
 325
 326 /*
 327  * Simple Mask Register Support
 328  */
 329 extern void make_maskreg_irq(unsigned int irq);
 330 extern unsigned short *irq_mask_register;
 331
 332 /*
 333  * Function for "on chip support modules".
 334  */
 335 extern void make_ipr_irq(unsigned int irq, unsigned int addr,
 336                          int pos,  int priority);
 337 extern void make_imask_irq(unsigned int irq);
 338
 339 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
 340 #undef INTC_IPRA
 341 #undef INTC_IPRB
 342 #define INTC_IPRA       0xA414FEE2UL
 343 #define INTC_IPRB       0xA414FEE4UL
 344 #define INTC_IPRC       0xA4140016UL
 345 #define INTC_IPRD       0xA4140018UL
 346 #define INTC_IPRE       0xA414001AUL
 347 #define INTC_IPRF       0xA4080000UL
 348 #define INTC_IPRG       0xA4080002UL
 349 #define INTC_IPRH       0xA4080004UL
 350 #define INTC_IPRI       0xA4080006UL
 351 #define INTC_IPRJ       0xA4080008UL
 352
 353 #define INTC_IMR0       0xA4080040UL
 354 #define INTC_IMR1       0xA4080042UL
 355 #define INTC_IMR2       0xA4080044UL
 356 #define INTC_IMR3       0xA4080046UL
 357 #define INTC_IMR4       0xA4080048UL
 358 #define INTC_IMR5       0xA408004AUL
 359 #define INTC_IMR6       0xA408004CUL
 360 #define INTC_IMR7       0xA408004EUL
 361 #define INTC_IMR8       0xA4080050UL
 362 #define INTC_IMR9       0xA4080052UL
 363 #define INTC_IMR10      0xA4080054UL
 364
 365 #define INTC_IMCR0      0xA4080060UL
 366 #define INTC_IMCR1      0xA4080062UL
 367 #define INTC_IMCR2      0xA4080064UL
 368 #define INTC_IMCR3      0xA4080066UL
 369 #define INTC_IMCR4      0xA4080068UL
 370 #define INTC_IMCR5      0xA408006AUL
 371 #define INTC_IMCR6      0xA408006CUL
 372 #define INTC_IMCR7      0xA408006EUL
 373 #define INTC_IMCR8      0xA4080070UL
 374 #define INTC_IMCR9      0xA4080072UL
 375 #define INTC_IMCR10     0xA4080074UL
 376
 377 #define INTC_ICR0       0xA414FEE0UL
 378 #define INTC_ICR1       0xA4140010UL
 379
 380 #define INTC_IRR0       0xA4140004UL
 381
 382 #define PORT_PACR       0xA4050100UL
 383 #define PORT_PBCR       0xA4050102UL
 384 #define PORT_PCCR       0xA4050104UL
 385 #define PORT_PDCR       0xA4050106UL
 386 #define PORT_PECR       0xA4050108UL
 387 #define PORT_PFCR       0xA405010AUL
 388 #define PORT_PGCR       0xA405010CUL
 389 #define PORT_PHCR       0xA405010EUL
 390 #define PORT_PJCR       0xA4050110UL
 391 #define PORT_PKCR       0xA4050112UL
 392 #define PORT_PLCR       0xA4050114UL
 393 #define PORT_SCPCR      0xA4050116UL
 394 #define PORT_PMCR       0xA4050118UL
 395 #define PORT_PNCR       0xA405011AUL
 396 #define PORT_PQCR       0xA405011CUL
 397
 398 #define PORT_PSELA      0xA4050140UL
 399 #define PORT_PSELB      0xA4050142UL
 400 #define PORT_PSELC      0xA4050144UL
 401
 402 #define PORT_HIZCRA     0xA4050146UL
 403 #define PORT_HIZCRB     0xA4050148UL
 404 #define PORT_DRVCR      0xA4050150UL
 405
 406 #define PORT_PADR       0xA4050120UL
 407 #define PORT_PBDR       0xA4050122UL
 408 #define PORT_PCDR       0xA4050124UL
 409 #define PORT_PDDR       0xA4050126UL
 410 #define PORT_PEDR       0xA4050128UL
 411 #define PORT_PFDR       0xA405012AUL
 412 #define PORT_PGDR       0xA405012CUL
 413 #define PORT_PHDR       0xA405012EUL
 414 #define PORT_PJDR       0xA4050130UL
 415 #define PORT_PKDR       0xA4050132UL
 416 #define PORT_PLDR       0xA4050134UL
 417 #define PORT_SCPDR      0xA4050136UL
 418 #define PORT_PMDR       0xA4050138UL
 419 #define PORT_PNDR       0xA405013AUL
 420 #define PORT_PQDR       0xA405013CUL
 421
 422 #define IRQ0_IRQ        32
 423 #define IRQ1_IRQ        33
 424 #define IRQ2_IRQ        34
 425 #define IRQ3_IRQ        35
 426 #define IRQ4_IRQ        36
 427 #define IRQ5_IRQ        37
 428
 429 #define IRQ0_IPR_ADDR   INTC_IPRC
 430 #define IRQ1_IPR_ADDR   INTC_IPRC
 431 #define IRQ2_IPR_ADDR   INTC_IPRC
 432 #define IRQ3_IPR_ADDR   INTC_IPRC
 433 #define IRQ4_IPR_ADDR   INTC_IPRD
 434 #define IRQ5_IPR_ADDR   INTC_IPRD
 435
 436 #define IRQ0_IPR_POS    0
 437 #define IRQ1_IPR_POS    1
 438 #define IRQ2_IPR_POS    2
 439 #define IRQ3_IPR_POS    3
 440 #define IRQ4_IPR_POS    0
 441 #define IRQ5_IPR_POS    1
 442
 443 #define IRQ0_PRIORITY   1
 444 #define IRQ1_PRIORITY   1
 445 #define IRQ2_PRIORITY   1
 446 #define IRQ3_PRIORITY   1
 447 #define IRQ4_PRIORITY   1
 448 #define IRQ5_PRIORITY   1
 449
 450 extern int ipr_irq_demux(int irq);
 451 #define __irq_demux(irq) ipr_irq_demux(irq)
 452
 453 #elif defined(CONFIG_CPU_SUBTYPE_SH7604)
 454 #define INTC_IPRA       0xfffffee2UL
 455 #define INTC_IPRB       0xfffffe60UL
 456
 457 #define INTC_VCRA       0xfffffe62UL
 458 #define INTC_VCRB       0xfffffe64UL
 459 #define INTC_VCRC       0xfffffe66UL
 460 #define INTC_VCRD       0xfffffe68UL
 461
 462 #define INTC_VCRWDT     0xfffffee4UL
 463 #define INTC_VCRDIV     0xffffff0cUL
 464 #define INTC_VCRDMA0    0xffffffa0UL
 465 #define INTC_VCRDMA1    0xffffffa8UL
 466
 467 #define INTC_ICR        0xfffffee0UL
 468 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 469       defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 470       defined(CONFIG_CPU_SUBTYPE_SH7709)
 471 #define INTC_IRR0       0xa4000004UL
 472 #define INTC_IRR1       0xa4000006UL
 473 #define INTC_IRR2       0xa4000008UL
 474
 475 #define INTC_ICR0       0xfffffee0UL
 476 #define INTC_ICR1       0xa4000010UL
 477 #define INTC_ICR2       0xa4000012UL
 478 #define INTC_INTER      0xa4000014UL
 479
 480 #define INTC_IPRC       0xa4000016UL
 481 #define INTC_IPRD       0xa4000018UL
 482 #define INTC_IPRE       0xa400001aUL
 483 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
 484 #define INTC_IPRF       0xa400001cUL
 485 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
 486 #define INTC_IPRF       0xa4080000UL
 487 #define INTC_IPRG       0xa4080002UL
 488 #define INTC_IPRH       0xa4080004UL
 489 #endif
 490
 491 #define PORT_PACR       0xa4000100UL
 492 #define PORT_PBCR       0xa4000102UL
 493 #define PORT_PCCR       0xa4000104UL
 494 #define PORT_PFCR       0xa400010aUL
 495 #define PORT_PADR       0xa4000120UL
 496 #define PORT_PBDR       0xa4000122UL
 497 #define PORT_PCDR       0xa4000124UL
 498 #define PORT_PFDR       0xa400012aUL
 499
 500 #define IRQ0_IRQ        32
 501 #define IRQ1_IRQ        33
 502 #define IRQ2_IRQ        34
 503 #define IRQ3_IRQ        35
 504 #define IRQ4_IRQ        36
 505 #define IRQ5_IRQ        37
 506
 507 #define IRQ0_IPR_ADDR   INTC_IPRC
 508 #define IRQ1_IPR_ADDR   INTC_IPRC
 509 #define IRQ2_IPR_ADDR   INTC_IPRC
 510 #define IRQ3_IPR_ADDR   INTC_IPRC
 511 #define IRQ4_IPR_ADDR   INTC_IPRD
 512 #define IRQ5_IPR_ADDR   INTC_IPRD
 513
 514 #define IRQ0_IPR_POS    0
 515 #define IRQ1_IPR_POS    1
 516 #define IRQ2_IPR_POS    2
 517 #define IRQ3_IPR_POS    3
 518 #define IRQ4_IPR_POS    0
 519 #define IRQ5_IPR_POS    1
 520
 521 #define IRQ0_PRIORITY   1
 522 #define IRQ1_PRIORITY   1
 523 #define IRQ2_PRIORITY   1
 524 #define IRQ3_PRIORITY   1
 525 #define IRQ4_PRIORITY   1
 526 #define IRQ5_PRIORITY   1
 527
 528 #define PINT0_IRQ       40
 529 #define PINT8_IRQ       41
 530
 531 #define PINT0_IPR_ADDR  INTC_IPRD
 532 #define PINT8_IPR_ADDR  INTC_IPRD
 533
 534 #define PINT0_IPR_POS   3
 535 #define PINT8_IPR_POS   2
 536 #define PINT0_PRIORITY  2
 537 #define PINT8_PRIORITY  2
 538
 539 extern int ipr_irq_demux(int irq);
 540 #define __irq_demux(irq) ipr_irq_demux(irq)
 541 #endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
 542
 543 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 544     defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
 545 #define INTC_ICR        0xffd00000
 546 #define INTC_ICR_NMIL   (1<<15)
 547 #define INTC_ICR_MAI    (1<<14)
 548 #define INTC_ICR_NMIB   (1<<9)
 549 #define INTC_ICR_NMIE   (1<<8)
 550 #define INTC_ICR_IRLM   (1<<7)
 551 #endif
 552
 553 #else
 554 #include <asm/irq-sh7780.h>
 555 #endif
 556
 557 /* SH with INTC2-style interrupts */
 558 #ifdef CONFIG_CPU_HAS_INTC2_IRQ
 559 #if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
 560 #define INTC2_BASE      0xfe080000
 561 #define INTC2_FIRST_IRQ 64
 562 #define INTC2_INTREQ_OFFSET     0x20
 563 #define INTC2_INTMSK_OFFSET     0x40
 564 #define INTC2_INTMSKCLR_OFFSET  0x60
 565 #define NR_INTC2_IRQS   25
 566 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
 567 #define INTC2_BASE      0xfe080000
 568 #define INTC2_FIRST_IRQ 48      /* INTEVT 0x800 */
 569 #define INTC2_INTREQ_OFFSET     0x20
 570 #define INTC2_INTMSK_OFFSET     0x40
 571 #define INTC2_INTMSKCLR_OFFSET  0x60
 572 #define NR_INTC2_IRQS   64
 573 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 574 #define INTC2_BASE      0xffd40000
 575 #define INTC2_FIRST_IRQ 22
 576 #define INTC2_INTMSK_OFFSET     (0x38)
 577 #define INTC2_INTMSKCLR_OFFSET  (0x3c)
 578 #define NR_INTC2_IRQS   60
 579 #endif
 580
 581 #define INTC2_INTPRI_OFFSET     0x00
 582
 583 void make_intc2_irq(unsigned int irq,
 584                     unsigned int ipr_offset, unsigned int ipr_shift,
 585                     unsigned int msk_offset, unsigned int msk_shift,
 586                     unsigned int priority);
 587 void init_IRQ_intc2(void);
 588 void intc2_add_clear_irq(int irq, int (*fn)(int));
 589
 590 #endif
 591
 592 static inline int generic_irq_demux(int irq)
 593 {
 594         return irq;
 595 }
 596
 597 #ifndef __irq_demux
 598 #define __irq_demux(irq)        (irq)
 599 #endif
 600 #define irq_canonicalize(irq)   (irq)
 601 #define irq_demux(irq)          __irq_demux(sh_mv.mv_irq_demux(irq))
 602
 603 #if defined(CONFIG_CPU_SUBTYPE_SH73180)
 604 #include <asm/irq-sh73180.h>
 605 #endif
 606
 607 #endif /* __ASM_SH_IRQ_H */