[ARM] 2995/1: Replace map_desc.physical with map_desc.pfn: Versatile
[linux-2.6/verdex.git] / arch / arm / mach-versatile / core.c
blob7e4bdd07f4afb4c82778a4c3c796d39684587103
1 /*
2 * linux/arch/arm/mach-versatile/core.c
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/config.h>
22 #include <linux/init.h>
23 #include <linux/device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/sysdev.h>
26 #include <linux/interrupt.h>
28 #include <asm/system.h>
29 #include <asm/hardware.h>
30 #include <asm/io.h>
31 #include <asm/irq.h>
32 #include <asm/leds.h>
33 #include <asm/hardware/amba.h>
34 #include <asm/hardware/amba_clcd.h>
35 #include <asm/hardware/arm_timer.h>
36 #include <asm/hardware/icst307.h>
38 #include <asm/mach/arch.h>
39 #include <asm/mach/flash.h>
40 #include <asm/mach/irq.h>
41 #include <asm/mach/time.h>
42 #include <asm/mach/map.h>
43 #include <asm/mach/mmc.h>
45 #include "core.h"
46 #include "clock.h"
49 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
50 * is the (PA >> 12).
52 * Setup a VA for the Versatile Vectored Interrupt Controller.
54 #define __io_address(n) __io(IO_ADDRESS(n))
55 #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
56 #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
58 static void vic_mask_irq(unsigned int irq)
60 irq -= IRQ_VIC_START;
61 writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR);
64 static void vic_unmask_irq(unsigned int irq)
66 irq -= IRQ_VIC_START;
67 writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE);
70 static struct irqchip vic_chip = {
71 .ack = vic_mask_irq,
72 .mask = vic_mask_irq,
73 .unmask = vic_unmask_irq,
76 static void sic_mask_irq(unsigned int irq)
78 irq -= IRQ_SIC_START;
79 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
82 static void sic_unmask_irq(unsigned int irq)
84 irq -= IRQ_SIC_START;
85 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
88 static struct irqchip sic_chip = {
89 .ack = sic_mask_irq,
90 .mask = sic_mask_irq,
91 .unmask = sic_unmask_irq,
94 static void
95 sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
97 unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
99 if (status == 0) {
100 do_bad_IRQ(irq, desc, regs);
101 return;
104 do {
105 irq = ffs(status) - 1;
106 status &= ~(1 << irq);
108 irq += IRQ_SIC_START;
110 desc = irq_desc + irq;
111 desc_handle_irq(irq, desc, regs);
112 } while (status);
115 #if 1
116 #define IRQ_MMCI0A IRQ_VICSOURCE22
117 #define IRQ_AACI IRQ_VICSOURCE24
118 #define IRQ_ETH IRQ_VICSOURCE25
119 #define PIC_MASK 0xFFD00000
120 #else
121 #define IRQ_MMCI0A IRQ_SIC_MMCI0A
122 #define IRQ_AACI IRQ_SIC_AACI
123 #define IRQ_ETH IRQ_SIC_ETH
124 #define PIC_MASK 0
125 #endif
127 void __init versatile_init_irq(void)
129 unsigned int i, value;
131 /* Disable all interrupts initially. */
133 writel(0, VA_VIC_BASE + VIC_INT_SELECT);
134 writel(0, VA_VIC_BASE + VIC_IRQ_ENABLE);
135 writel(~0, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR);
136 writel(0, VA_VIC_BASE + VIC_IRQ_STATUS);
137 writel(0, VA_VIC_BASE + VIC_ITCR);
138 writel(~0, VA_VIC_BASE + VIC_IRQ_SOFT_CLEAR);
141 * Make sure we clear all existing interrupts
143 writel(0, VA_VIC_BASE + VIC_VECT_ADDR);
144 for (i = 0; i < 19; i++) {
145 value = readl(VA_VIC_BASE + VIC_VECT_ADDR);
146 writel(value, VA_VIC_BASE + VIC_VECT_ADDR);
149 for (i = 0; i < 16; i++) {
150 value = readl(VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4));
151 writel(value | VICVectCntl_Enable | i, VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4));
154 writel(32, VA_VIC_BASE + VIC_DEF_VECT_ADDR);
156 for (i = IRQ_VIC_START; i <= IRQ_VIC_END; i++) {
157 if (i != IRQ_VICSOURCE31) {
158 set_irq_chip(i, &vic_chip);
159 set_irq_handler(i, do_level_IRQ);
160 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
164 set_irq_handler(IRQ_VICSOURCE31, sic_handle_irq);
165 vic_unmask_irq(IRQ_VICSOURCE31);
167 /* Do second interrupt controller */
168 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
170 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
171 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
172 set_irq_chip(i, &sic_chip);
173 set_irq_handler(i, do_level_IRQ);
174 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
179 * Interrupts on secondary controller from 0 to 8 are routed to
180 * source 31 on PIC.
181 * Interrupts from 21 to 31 are routed directly to the VIC on
182 * the corresponding number on primary controller. This is controlled
183 * by setting PIC_ENABLEx.
185 writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
188 static struct map_desc versatile_io_desc[] __initdata = {
190 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
191 .pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
192 .length = SZ_4K,
193 .type = MT_DEVICE
194 }, {
195 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
196 .pfn = __phys_to_pfn(VERSATILE_SIC_BASE),
197 .length = SZ_4K,
198 .type = MT_DEVICE
199 }, {
200 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
201 .pfn = __phys_to_pfn(VERSATILE_VIC_BASE),
202 .length = SZ_4K,
203 .type = MT_DEVICE
204 }, {
205 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
206 .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
207 .length = SZ_4K * 9,
208 .type = MT_DEVICE
210 #ifdef CONFIG_MACH_VERSATILE_AB
212 .virtual = IO_ADDRESS(VERSATILE_GPIO0_BASE),
213 .pfn = __phys_to_pfn(VERSATILE_GPIO0_BASE),
214 .length = SZ_4K,
215 .type = MT_DEVICE
216 }, {
217 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
218 .pfn = __phys_to_pfn(VERSATILE_IB2_BASE),
219 .length = SZ_64M,
220 .type = MT_DEVICE
222 #endif
223 #ifdef CONFIG_DEBUG_LL
225 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
226 .pfn = __phys_to_pfn(VERSATILE_UART0_BASE),
227 .length = SZ_4K,
228 .type = MT_DEVICE
230 #endif
231 #ifdef CONFIG_PCI
233 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
234 .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
235 .length = SZ_4K,
236 .type = MT_DEVICE
237 }, {
238 .virtual = VERSATILE_PCI_VIRT_BASE,
239 .pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
240 .length = VERSATILE_PCI_BASE_SIZE,
241 .type = MT_DEVICE
242 }, {
243 .virtual = VERSATILE_PCI_CFG_VIRT_BASE,
244 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
245 .length = VERSATILE_PCI_CFG_BASE_SIZE,
246 .type = MT_DEVICE
248 #if 0
250 .virtual = VERSATILE_PCI_VIRT_MEM_BASE0,
251 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
252 .length = SZ_16M,
253 .type = MT_DEVICE
254 }, {
255 .virtual = VERSATILE_PCI_VIRT_MEM_BASE1,
256 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
257 .length = SZ_16M,
258 .type = MT_DEVICE
259 }, {
260 .virtual = VERSATILE_PCI_VIRT_MEM_BASE2,
261 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
262 .length = SZ_16M,
263 .type = MT_DEVICE
265 #endif
266 #endif
269 void __init versatile_map_io(void)
271 iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
274 #define VERSATILE_REFCOUNTER (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
277 * This is the Versatile sched_clock implementation. This has
278 * a resolution of 41.7ns, and a maximum value of about 179s.
280 unsigned long long sched_clock(void)
282 unsigned long long v;
284 v = (unsigned long long)readl(VERSATILE_REFCOUNTER) * 125;
285 do_div(v, 3);
287 return v;
291 #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
293 static int versatile_flash_init(void)
295 u32 val;
297 val = __raw_readl(VERSATILE_FLASHCTRL);
298 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
299 __raw_writel(val, VERSATILE_FLASHCTRL);
301 return 0;
304 static void versatile_flash_exit(void)
306 u32 val;
308 val = __raw_readl(VERSATILE_FLASHCTRL);
309 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
310 __raw_writel(val, VERSATILE_FLASHCTRL);
313 static void versatile_flash_set_vpp(int on)
315 u32 val;
317 val = __raw_readl(VERSATILE_FLASHCTRL);
318 if (on)
319 val |= VERSATILE_FLASHPROG_FLVPPEN;
320 else
321 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
322 __raw_writel(val, VERSATILE_FLASHCTRL);
325 static struct flash_platform_data versatile_flash_data = {
326 .map_name = "cfi_probe",
327 .width = 4,
328 .init = versatile_flash_init,
329 .exit = versatile_flash_exit,
330 .set_vpp = versatile_flash_set_vpp,
333 static struct resource versatile_flash_resource = {
334 .start = VERSATILE_FLASH_BASE,
335 .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE,
336 .flags = IORESOURCE_MEM,
339 static struct platform_device versatile_flash_device = {
340 .name = "armflash",
341 .id = 0,
342 .dev = {
343 .platform_data = &versatile_flash_data,
345 .num_resources = 1,
346 .resource = &versatile_flash_resource,
349 static struct resource smc91x_resources[] = {
350 [0] = {
351 .start = VERSATILE_ETH_BASE,
352 .end = VERSATILE_ETH_BASE + SZ_64K - 1,
353 .flags = IORESOURCE_MEM,
355 [1] = {
356 .start = IRQ_ETH,
357 .end = IRQ_ETH,
358 .flags = IORESOURCE_IRQ,
362 static struct platform_device smc91x_device = {
363 .name = "smc91x",
364 .id = 0,
365 .num_resources = ARRAY_SIZE(smc91x_resources),
366 .resource = smc91x_resources,
369 #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
371 unsigned int mmc_status(struct device *dev)
373 struct amba_device *adev = container_of(dev, struct amba_device, dev);
374 u32 mask;
376 if (adev->res.start == VERSATILE_MMCI0_BASE)
377 mask = 1;
378 else
379 mask = 2;
381 return readl(VERSATILE_SYSMCI) & mask;
384 static struct mmc_platform_data mmc0_plat_data = {
385 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
386 .status = mmc_status,
390 * Clock handling
392 static const struct icst307_params versatile_oscvco_params = {
393 .ref = 24000,
394 .vco_max = 200000,
395 .vd_min = 4 + 8,
396 .vd_max = 511 + 8,
397 .rd_min = 1 + 2,
398 .rd_max = 127 + 2,
401 static void versatile_oscvco_set(struct clk *clk, struct icst307_vco vco)
403 void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
404 #if defined(CONFIG_ARCH_VERSATILE_PB)
405 void __iomem *sys_osc = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSC4_OFFSET;
406 #elif defined(CONFIG_MACH_VERSATILE_AB)
407 void __iomem *sys_osc = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSC1_OFFSET;
408 #endif
409 u32 val;
411 val = readl(sys_osc) & ~0x7ffff;
412 val |= vco.v | (vco.r << 9) | (vco.s << 16);
414 writel(0xa05f, sys_lock);
415 writel(val, sys_osc);
416 writel(0, sys_lock);
419 static struct clk versatile_clcd_clk = {
420 .name = "CLCDCLK",
421 .params = &versatile_oscvco_params,
422 .setvco = versatile_oscvco_set,
426 * CLCD support.
428 #define SYS_CLCD_MODE_MASK (3 << 0)
429 #define SYS_CLCD_MODE_888 (0 << 0)
430 #define SYS_CLCD_MODE_5551 (1 << 0)
431 #define SYS_CLCD_MODE_565_RLSB (2 << 0)
432 #define SYS_CLCD_MODE_565_BLSB (3 << 0)
433 #define SYS_CLCD_NLCDIOON (1 << 2)
434 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
435 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
436 #define SYS_CLCD_ID_MASK (0x1f << 8)
437 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
438 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
439 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
440 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
441 #define SYS_CLCD_ID_VGA (0x1f << 8)
443 static struct clcd_panel vga = {
444 .mode = {
445 .name = "VGA",
446 .refresh = 60,
447 .xres = 640,
448 .yres = 480,
449 .pixclock = 39721,
450 .left_margin = 40,
451 .right_margin = 24,
452 .upper_margin = 32,
453 .lower_margin = 11,
454 .hsync_len = 96,
455 .vsync_len = 2,
456 .sync = 0,
457 .vmode = FB_VMODE_NONINTERLACED,
459 .width = -1,
460 .height = -1,
461 .tim2 = TIM2_BCD | TIM2_IPC,
462 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
463 .bpp = 16,
466 static struct clcd_panel sanyo_3_8_in = {
467 .mode = {
468 .name = "Sanyo QVGA",
469 .refresh = 116,
470 .xres = 320,
471 .yres = 240,
472 .pixclock = 100000,
473 .left_margin = 6,
474 .right_margin = 6,
475 .upper_margin = 5,
476 .lower_margin = 5,
477 .hsync_len = 6,
478 .vsync_len = 6,
479 .sync = 0,
480 .vmode = FB_VMODE_NONINTERLACED,
482 .width = -1,
483 .height = -1,
484 .tim2 = TIM2_BCD,
485 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
486 .bpp = 16,
489 static struct clcd_panel sanyo_2_5_in = {
490 .mode = {
491 .name = "Sanyo QVGA Portrait",
492 .refresh = 116,
493 .xres = 240,
494 .yres = 320,
495 .pixclock = 100000,
496 .left_margin = 20,
497 .right_margin = 10,
498 .upper_margin = 2,
499 .lower_margin = 2,
500 .hsync_len = 10,
501 .vsync_len = 2,
502 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
503 .vmode = FB_VMODE_NONINTERLACED,
505 .width = -1,
506 .height = -1,
507 .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
508 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
509 .bpp = 16,
512 static struct clcd_panel epson_2_2_in = {
513 .mode = {
514 .name = "Epson QCIF",
515 .refresh = 390,
516 .xres = 176,
517 .yres = 220,
518 .pixclock = 62500,
519 .left_margin = 3,
520 .right_margin = 2,
521 .upper_margin = 1,
522 .lower_margin = 0,
523 .hsync_len = 3,
524 .vsync_len = 2,
525 .sync = 0,
526 .vmode = FB_VMODE_NONINTERLACED,
528 .width = -1,
529 .height = -1,
530 .tim2 = TIM2_BCD | TIM2_IPC,
531 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
532 .bpp = 16,
536 * Detect which LCD panel is connected, and return the appropriate
537 * clcd_panel structure. Note: we do not have any information on
538 * the required timings for the 8.4in panel, so we presently assume
539 * VGA timings.
541 static struct clcd_panel *versatile_clcd_panel(void)
543 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
544 struct clcd_panel *panel = &vga;
545 u32 val;
547 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
548 if (val == SYS_CLCD_ID_SANYO_3_8)
549 panel = &sanyo_3_8_in;
550 else if (val == SYS_CLCD_ID_SANYO_2_5)
551 panel = &sanyo_2_5_in;
552 else if (val == SYS_CLCD_ID_EPSON_2_2)
553 panel = &epson_2_2_in;
554 else if (val == SYS_CLCD_ID_VGA)
555 panel = &vga;
556 else {
557 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
558 val);
559 panel = &vga;
562 return panel;
566 * Disable all display connectors on the interface module.
568 static void versatile_clcd_disable(struct clcd_fb *fb)
570 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
571 u32 val;
573 val = readl(sys_clcd);
574 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
575 writel(val, sys_clcd);
577 #ifdef CONFIG_MACH_VERSATILE_AB
579 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
581 if (fb->panel == &sanyo_2_5_in) {
582 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
583 unsigned long ctrl;
585 ctrl = readl(versatile_ib2_ctrl);
586 ctrl &= ~0x01;
587 writel(ctrl, versatile_ib2_ctrl);
589 #endif
593 * Enable the relevant connector on the interface module.
595 static void versatile_clcd_enable(struct clcd_fb *fb)
597 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
598 u32 val;
600 val = readl(sys_clcd);
601 val &= ~SYS_CLCD_MODE_MASK;
603 switch (fb->fb.var.green.length) {
604 case 5:
605 val |= SYS_CLCD_MODE_5551;
606 break;
607 case 6:
608 val |= SYS_CLCD_MODE_565_RLSB;
609 break;
610 case 8:
611 val |= SYS_CLCD_MODE_888;
612 break;
616 * Set the MUX
618 writel(val, sys_clcd);
621 * And now enable the PSUs
623 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
624 writel(val, sys_clcd);
626 #ifdef CONFIG_MACH_VERSATILE_AB
628 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
630 if (fb->panel == &sanyo_2_5_in) {
631 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
632 unsigned long ctrl;
634 ctrl = readl(versatile_ib2_ctrl);
635 ctrl |= 0x01;
636 writel(ctrl, versatile_ib2_ctrl);
638 #endif
641 static unsigned long framesize = SZ_1M;
643 static int versatile_clcd_setup(struct clcd_fb *fb)
645 dma_addr_t dma;
647 fb->panel = versatile_clcd_panel();
649 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
650 &dma, GFP_KERNEL);
651 if (!fb->fb.screen_base) {
652 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
653 return -ENOMEM;
656 fb->fb.fix.smem_start = dma;
657 fb->fb.fix.smem_len = framesize;
659 return 0;
662 static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
664 return dma_mmap_writecombine(&fb->dev->dev, vma,
665 fb->fb.screen_base,
666 fb->fb.fix.smem_start,
667 fb->fb.fix.smem_len);
670 static void versatile_clcd_remove(struct clcd_fb *fb)
672 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
673 fb->fb.screen_base, fb->fb.fix.smem_start);
676 static struct clcd_board clcd_plat_data = {
677 .name = "Versatile",
678 .check = clcdfb_check,
679 .decode = clcdfb_decode,
680 .disable = versatile_clcd_disable,
681 .enable = versatile_clcd_enable,
682 .setup = versatile_clcd_setup,
683 .mmap = versatile_clcd_mmap,
684 .remove = versatile_clcd_remove,
687 #define AACI_IRQ { IRQ_AACI, NO_IRQ }
688 #define AACI_DMA { 0x80, 0x81 }
689 #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
690 #define MMCI0_DMA { 0x84, 0 }
691 #define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ }
692 #define KMI0_DMA { 0, 0 }
693 #define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ }
694 #define KMI1_DMA { 0, 0 }
697 * These devices are connected directly to the multi-layer AHB switch
699 #define SMC_IRQ { NO_IRQ, NO_IRQ }
700 #define SMC_DMA { 0, 0 }
701 #define MPMC_IRQ { NO_IRQ, NO_IRQ }
702 #define MPMC_DMA { 0, 0 }
703 #define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
704 #define CLCD_DMA { 0, 0 }
705 #define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
706 #define DMAC_DMA { 0, 0 }
709 * These devices are connected via the core APB bridge
711 #define SCTL_IRQ { NO_IRQ, NO_IRQ }
712 #define SCTL_DMA { 0, 0 }
713 #define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
714 #define WATCHDOG_DMA { 0, 0 }
715 #define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
716 #define GPIO0_DMA { 0, 0 }
717 #define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
718 #define GPIO1_DMA { 0, 0 }
719 #define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
720 #define RTC_DMA { 0, 0 }
723 * These devices are connected via the DMA APB bridge
725 #define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
726 #define SCI_DMA { 7, 6 }
727 #define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
728 #define UART0_DMA { 15, 14 }
729 #define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
730 #define UART1_DMA { 13, 12 }
731 #define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
732 #define UART2_DMA { 11, 10 }
733 #define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
734 #define SSP_DMA { 9, 8 }
736 /* FPGA Primecells */
737 AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
738 AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
739 AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
740 AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
742 /* DevChip Primecells */
743 AMBA_DEVICE(smc, "dev:00", SMC, NULL);
744 AMBA_DEVICE(mpmc, "dev:10", MPMC, NULL);
745 AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
746 AMBA_DEVICE(dmac, "dev:30", DMAC, NULL);
747 AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
748 AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
749 AMBA_DEVICE(gpio0, "dev:e4", GPIO0, NULL);
750 AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL);
751 AMBA_DEVICE(rtc, "dev:e8", RTC, NULL);
752 AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
753 AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
754 AMBA_DEVICE(uart1, "dev:f2", UART1, NULL);
755 AMBA_DEVICE(uart2, "dev:f3", UART2, NULL);
756 AMBA_DEVICE(ssp0, "dev:f4", SSP, NULL);
758 static struct amba_device *amba_devs[] __initdata = {
759 &dmac_device,
760 &uart0_device,
761 &uart1_device,
762 &uart2_device,
763 &smc_device,
764 &mpmc_device,
765 &clcd_device,
766 &sctl_device,
767 &wdog_device,
768 &gpio0_device,
769 &gpio1_device,
770 &rtc_device,
771 &sci0_device,
772 &ssp0_device,
773 &aaci_device,
774 &mmc0_device,
775 &kmi0_device,
776 &kmi1_device,
779 #ifdef CONFIG_LEDS
780 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
782 static void versatile_leds_event(led_event_t ledevt)
784 unsigned long flags;
785 u32 val;
787 local_irq_save(flags);
788 val = readl(VA_LEDS_BASE);
790 switch (ledevt) {
791 case led_idle_start:
792 val = val & ~VERSATILE_SYS_LED0;
793 break;
795 case led_idle_end:
796 val = val | VERSATILE_SYS_LED0;
797 break;
799 case led_timer:
800 val = val ^ VERSATILE_SYS_LED1;
801 break;
803 case led_halted:
804 val = 0;
805 break;
807 default:
808 break;
811 writel(val, VA_LEDS_BASE);
812 local_irq_restore(flags);
814 #endif /* CONFIG_LEDS */
816 void __init versatile_init(void)
818 int i;
820 clk_register(&versatile_clcd_clk);
822 platform_device_register(&versatile_flash_device);
823 platform_device_register(&smc91x_device);
825 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
826 struct amba_device *d = amba_devs[i];
827 amba_device_register(d, &iomem_resource);
830 #ifdef CONFIG_LEDS
831 leds_event = versatile_leds_event;
832 #endif
836 * Where is the timer (VA)?
838 #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
839 #define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
840 #define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
841 #define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
842 #define VA_IC_BASE __io_address(VERSATILE_VIC_BASE)
845 * How long is the timer interval?
847 #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
848 #if TIMER_INTERVAL >= 0x100000
849 #define TIMER_RELOAD (TIMER_INTERVAL >> 8)
850 #define TIMER_DIVISOR (TIMER_CTRL_DIV256)
851 #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
852 #elif TIMER_INTERVAL >= 0x10000
853 #define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
854 #define TIMER_DIVISOR (TIMER_CTRL_DIV16)
855 #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
856 #else
857 #define TIMER_RELOAD (TIMER_INTERVAL)
858 #define TIMER_DIVISOR (TIMER_CTRL_DIV1)
859 #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
860 #endif
863 * Returns number of ms since last clock interrupt. Note that interrupts
864 * will have been disabled by do_gettimeoffset()
866 static unsigned long versatile_gettimeoffset(void)
868 unsigned long ticks1, ticks2, status;
871 * Get the current number of ticks. Note that there is a race
872 * condition between us reading the timer and checking for
873 * an interrupt. We get around this by ensuring that the
874 * counter has not reloaded between our two reads.
876 ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
877 do {
878 ticks1 = ticks2;
879 status = __raw_readl(VA_IC_BASE + VIC_IRQ_RAW_STATUS);
880 ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
881 } while (ticks2 > ticks1);
884 * Number of ticks since last interrupt.
886 ticks1 = TIMER_RELOAD - ticks2;
889 * Interrupt pending? If so, we've reloaded once already.
891 * FIXME: Need to check this is effectively timer 0 that expires
893 if (status & IRQMASK_TIMERINT0_1)
894 ticks1 += TIMER_RELOAD;
897 * Convert the ticks to usecs
899 return TICKS2USECS(ticks1);
903 * IRQ handler for the timer
905 static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
907 write_seqlock(&xtime_lock);
909 // ...clear the interrupt
910 writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
912 timer_tick(regs);
914 write_sequnlock(&xtime_lock);
916 return IRQ_HANDLED;
919 static struct irqaction versatile_timer_irq = {
920 .name = "Versatile Timer Tick",
921 .flags = SA_INTERRUPT | SA_TIMER,
922 .handler = versatile_timer_interrupt,
926 * Set up timer interrupt, and return the current time in seconds.
928 static void __init versatile_timer_init(void)
930 u32 val;
933 * set clock frequency:
934 * VERSATILE_REFCLK is 32KHz
935 * VERSATILE_TIMCLK is 1MHz
937 val = readl(__io_address(VERSATILE_SCTL_BASE));
938 writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
939 (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
940 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
941 (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
942 __io_address(VERSATILE_SCTL_BASE));
945 * Initialise to a known state (all timers off)
947 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
948 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
949 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
950 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
952 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
953 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_VALUE);
954 writel(TIMER_DIVISOR | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC |
955 TIMER_CTRL_IE, TIMER0_VA_BASE + TIMER_CTRL);
958 * Make irqs happen for the system timer
960 setup_irq(IRQ_TIMERINT0_1, &versatile_timer_irq);
963 struct sys_timer versatile_timer = {
964 .init = versatile_timer_init,
965 .offset = versatile_gettimeoffset,