?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[PATCH] UFS: inode->i_sem is not released in error path
[linux-2.6/verdex.git] / drivers / pci / hotplug / pciehp_hpc.c
blobac1e495c314ead9d803658a0ae296f4010c56898
1 /*
2 * PCI Express PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38
39 #include "../pci.h"
40 #include "pciehp.h"
41
42 #ifdef DEBUG
43 #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */
44 #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */
45 #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */
46 #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */
47 #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)
48 #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)
49 /* Redefine this flagword to set debug level */
50 #define DEBUG_LEVEL DBG_K_STANDARD
51
52 #define DEFINE_DBG_BUFFER char __dbg_str_buf[256];
53
54 #define DBG_PRINT( dbg_flags, args... ) \
55 do { \
56 if ( DEBUG_LEVEL & ( dbg_flags ) ) \
57 { \
58 int len; \
59 len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \
60 __FILE__, __LINE__, __FUNCTION__ ); \
61 sprintf( __dbg_str_buf + len, args ); \
62 printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \
63 } \
64 } while (0)
65
66 #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");
67 #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");
68 #else
69 #define DEFINE_DBG_BUFFER
70 #define DBG_ENTER_ROUTINE
71 #define DBG_LEAVE_ROUTINE
72 #endif /* DEBUG */
73
74 struct ctrl_reg {
75 u8 cap_id;
76 u8 nxt_ptr;
77 u16 cap_reg;
78 u32 dev_cap;
79 u16 dev_ctrl;
80 u16 dev_status;
81 u32 lnk_cap;
82 u16 lnk_ctrl;
83 u16 lnk_status;
84 u32 slot_cap;
85 u16 slot_ctrl;
86 u16 slot_status;
87 u16 root_ctrl;
88 u16 rsvp;
89 u32 root_status;
90 } __attribute__ ((packed));
91
92 /* offsets to the controller registers based on the above structure layout */
93 enum ctrl_offsets {
94 PCIECAPID = offsetof(struct ctrl_reg, cap_id),
95 NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr),
96 CAPREG = offsetof(struct ctrl_reg, cap_reg),
97 DEVCAP = offsetof(struct ctrl_reg, dev_cap),
98 DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl),
99 DEVSTATUS = offsetof(struct ctrl_reg, dev_status),
100 LNKCAP = offsetof(struct ctrl_reg, lnk_cap),
101 LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl),
102 LNKSTATUS = offsetof(struct ctrl_reg, lnk_status),
103 SLOTCAP = offsetof(struct ctrl_reg, slot_cap),
104 SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl),
105 SLOTSTATUS = offsetof(struct ctrl_reg, slot_status),
106 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl),
107 ROOTSTATUS = offsetof(struct ctrl_reg, root_status),
108 };
109 static int pcie_cap_base = 0; /* Base of the PCI Express capability item structure */
110
111 #define PCIE_CAP_ID(cb) ( cb + PCIECAPID )
112 #define NXT_CAP_PTR(cb) ( cb + NXTCAPPTR )
113 #define CAP_REG(cb) ( cb + CAPREG )
114 #define DEV_CAP(cb) ( cb + DEVCAP )
115 #define DEV_CTRL(cb) ( cb + DEVCTRL )
116 #define DEV_STATUS(cb) ( cb + DEVSTATUS )
117 #define LNK_CAP(cb) ( cb + LNKCAP )
118 #define LNK_CTRL(cb) ( cb + LNKCTRL )
119 #define LNK_STATUS(cb) ( cb + LNKSTATUS )
120 #define SLOT_CAP(cb) ( cb + SLOTCAP )
121 #define SLOT_CTRL(cb) ( cb + SLOTCTRL )
122 #define SLOT_STATUS(cb) ( cb + SLOTSTATUS )
123 #define ROOT_CTRL(cb) ( cb + ROOTCTRL )
124 #define ROOT_STATUS(cb) ( cb + ROOTSTATUS )
125
126 #define hp_register_read_word(pdev, reg , value) \
127 pci_read_config_word(pdev, reg, &value)
128
129 #define hp_register_read_dword(pdev, reg , value) \
130 pci_read_config_dword(pdev, reg, &value)
131
132 #define hp_register_write_word(pdev, reg , value) \
133 pci_write_config_word(pdev, reg, value)
134
135 #define hp_register_dwrite_word(pdev, reg , value) \
136 pci_write_config_dword(pdev, reg, value)
137
138 /* Field definitions in PCI Express Capabilities Register */
139 #define CAP_VER 0x000F
140 #define DEV_PORT_TYPE 0x00F0
141 #define SLOT_IMPL 0x0100
142 #define MSG_NUM 0x3E00
143
144 /* Device or Port Type */
145 #define NAT_ENDPT 0x00
146 #define LEG_ENDPT 0x01
147 #define ROOT_PORT 0x04
148 #define UP_STREAM 0x05
149 #define DN_STREAM 0x06
150 #define PCIE_PCI_BRDG 0x07
151 #define PCI_PCIE_BRDG 0x10
152
153 /* Field definitions in Device Capabilities Register */
154 #define DATTN_BUTTN_PRSN 0x1000
155 #define DATTN_LED_PRSN 0x2000
156 #define DPWR_LED_PRSN 0x4000
157
158 /* Field definitions in Link Capabilities Register */
159 #define MAX_LNK_SPEED 0x000F
160 #define MAX_LNK_WIDTH 0x03F0
161
162 /* Link Width Encoding */
163 #define LNK_X1 0x01
164 #define LNK_X2 0x02
165 #define LNK_X4 0x04
166 #define LNK_X8 0x08
167 #define LNK_X12 0x0C
168 #define LNK_X16 0x10
169 #define LNK_X32 0x20
170
171 /*Field definitions of Link Status Register */
172 #define LNK_SPEED 0x000F
173 #define NEG_LINK_WD 0x03F0
174 #define LNK_TRN_ERR 0x0400
175 #define LNK_TRN 0x0800
176 #define SLOT_CLK_CONF 0x1000
177
178 /* Field definitions in Slot Capabilities Register */
179 #define ATTN_BUTTN_PRSN 0x00000001
180 #define PWR_CTRL_PRSN 0x00000002
181 #define MRL_SENS_PRSN 0x00000004
182 #define ATTN_LED_PRSN 0x00000008
183 #define PWR_LED_PRSN 0x00000010
184 #define HP_SUPR_RM_SUP 0x00000020
185 #define HP_CAP 0x00000040
186 #define SLOT_PWR_VALUE 0x000003F8
187 #define SLOT_PWR_LIMIT 0x00000C00
188 #define PSN 0xFFF80000 /* PSN: Physical Slot Number */
189
190 /* Field definitions in Slot Control Register */
191 #define ATTN_BUTTN_ENABLE 0x0001
192 #define PWR_FAULT_DETECT_ENABLE 0x0002
193 #define MRL_DETECT_ENABLE 0x0004
194 #define PRSN_DETECT_ENABLE 0x0008
195 #define CMD_CMPL_INTR_ENABLE 0x0010
196 #define HP_INTR_ENABLE 0x0020
197 #define ATTN_LED_CTRL 0x00C0
198 #define PWR_LED_CTRL 0x0300
199 #define PWR_CTRL 0x0400
200
201 /* Attention indicator and Power indicator states */
202 #define LED_ON 0x01
203 #define LED_BLINK 0x10
204 #define LED_OFF 0x11
205
206 /* Power Control Command */
207 #define POWER_ON 0
208 #define POWER_OFF 0x0400
209
210 /* Field definitions in Slot Status Register */
211 #define ATTN_BUTTN_PRESSED 0x0001
212 #define PWR_FAULT_DETECTED 0x0002
213 #define MRL_SENS_CHANGED 0x0004
214 #define PRSN_DETECT_CHANGED 0x0008
215 #define CMD_COMPLETED 0x0010
216 #define MRL_STATE 0x0020
217 #define PRSN_STATE 0x0040
218
219 static spinlock_t hpc_event_lock;
220
221 DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */
222 static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */
223 static int ctlr_seq_num = 0; /* Controller sequence # */
224 static spinlock_t list_lock;
225
226 static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs);
227
228 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds);
229
230 /* This is the interrupt polling timeout function. */
231 static void int_poll_timeout(unsigned long lphp_ctlr)
232 {
233 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *)lphp_ctlr;
234
235 DBG_ENTER_ROUTINE
236
237 if ( !php_ctlr ) {
238 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
239 return;
240 }
241
242 /* Poll for interrupt events. regs == NULL => polling */
243 pcie_isr( 0, (void *)php_ctlr, NULL );
244
245 init_timer(&php_ctlr->int_poll_timer);
246
247 if (!pciehp_poll_time)
248 pciehp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/
249
250 start_int_poll_timer(php_ctlr, pciehp_poll_time);
251
252 return;
253 }
254
255 /* This function starts the interrupt polling timer. */
256 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds)
257 {
258 if (!php_ctlr) {
259 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
260 return;
261 }
262
263 if ( ( seconds <= 0 ) || ( seconds > 60 ) )
264 seconds = 2; /* Clamp to sane value */
265
266 php_ctlr->int_poll_timer.function = &int_poll_timeout;
267 php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr; /* Instance data */
268 php_ctlr->int_poll_timer.expires = jiffies + seconds * HZ;
269 add_timer(&php_ctlr->int_poll_timer);
270
271 return;
272 }
273
274 static int pcie_write_cmd(struct slot *slot, u16 cmd)
275 {
276 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
277 int retval = 0;
278 u16 slot_status;
279
280 DBG_ENTER_ROUTINE
281
282 if (!php_ctlr) {
283 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
284 return -1;
285 }
286
287 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
288 if (retval) {
289 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
290 return retval;
291 }
292
293 if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) {
294 /* After 1 sec and CMD_COMPLETED still not set, just proceed forward to issue
295 the next command according to spec. Just print out the error message */
296 dbg("%s : CMD_COMPLETED not clear after 1 sec.\n", __FUNCTION__);
297 }
298
299 retval = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), cmd | CMD_CMPL_INTR_ENABLE);
300 if (retval) {
301 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
302 return retval;
303 }
304
305 DBG_LEAVE_ROUTINE
306 return retval;
307 }
308
309 static int hpc_check_lnk_status(struct controller *ctrl)
310 {
311 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
312 u16 lnk_status;
313 int retval = 0;
314
315 DBG_ENTER_ROUTINE
316
317 if (!php_ctlr) {
318 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
319 return -1;
320 }
321
322 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(ctrl->cap_base), lnk_status);
323
324 if (retval) {
325 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
326 return retval;
327 }
328
329 dbg("%s: lnk_status = %x\n", __FUNCTION__, lnk_status);
330 if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) ||
331 !(lnk_status & NEG_LINK_WD)) {
332 err("%s : Link Training Error occurs \n", __FUNCTION__);
333 retval = -1;
334 return retval;
335 }
336
337 DBG_LEAVE_ROUTINE
338 return retval;
339 }
340
341
342 static int hpc_get_attention_status(struct slot *slot, u8 *status)
343 {
344 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
345 u16 slot_ctrl;
346 u8 atten_led_state;
347 int retval = 0;
348
349 DBG_ENTER_ROUTINE
350
351 if (!php_ctlr) {
352 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
353 return -1;
354 }
355
356 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
357
358 if (retval) {
359 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
360 return retval;
361 }
362
363 dbg("%s: SLOT_CTRL %x, value read %x\n", __FUNCTION__,SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
364
365 atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
366
367 switch (atten_led_state) {
368 case 0:
369 *status = 0xFF; /* Reserved */
370 break;
371 case 1:
372 *status = 1; /* On */
373 break;
374 case 2:
375 *status = 2; /* Blink */
376 break;
377 case 3:
378 *status = 0; /* Off */
379 break;
380 default:
381 *status = 0xFF;
382 break;
383 }
384
385 DBG_LEAVE_ROUTINE
386 return 0;
387 }
388
389 static int hpc_get_power_status(struct slot * slot, u8 *status)
390 {
391 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
392 u16 slot_ctrl;
393 u8 pwr_state;
394 int retval = 0;
395
396 DBG_ENTER_ROUTINE
397
398 if (!php_ctlr) {
399 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
400 return -1;
401 }
402
403 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
404
405 if (retval) {
406 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
407 return retval;
408 }
409 dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
410
411 pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
412
413 switch (pwr_state) {
414 case 0:
415 *status = 1;
416 break;
417 case 1:
418 *status = 0;
419 break;
420 default:
421 *status = 0xFF;
422 break;
423 }
424
425 DBG_LEAVE_ROUTINE
426 return retval;
427 }
428
429
430 static int hpc_get_latch_status(struct slot *slot, u8 *status)
431 {
432 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
433 u16 slot_status;
434 int retval = 0;
435
436 DBG_ENTER_ROUTINE
437
438 if (!php_ctlr) {
439 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
440 return -1;
441 }
442
443 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
444
445 if (retval) {
446 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
447 return retval;
448 }
449
450 *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;
451
452 DBG_LEAVE_ROUTINE
453 return 0;
454 }
455
456 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
457 {
458 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
459 u16 slot_status;
460 u8 card_state;
461 int retval = 0;
462
463 DBG_ENTER_ROUTINE
464
465 if (!php_ctlr) {
466 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
467 return -1;
468 }
469
470 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
471
472 if (retval) {
473 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
474 return retval;
475 }
476 card_state = (u8)((slot_status & PRSN_STATE) >> 6);
477 *status = (card_state == 1) ? 1 : 0;
478
479 DBG_LEAVE_ROUTINE
480 return 0;
481 }
482
483 static int hpc_query_power_fault(struct slot * slot)
484 {
485 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
486 u16 slot_status;
487 u8 pwr_fault;
488 int retval = 0;
489
490 DBG_ENTER_ROUTINE
491
492 if (!php_ctlr) {
493 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
494 return -1;
495 }
496
497 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
498
499 if (retval) {
500 err("%s : Cannot check for power fault\n", __FUNCTION__);
501 return retval;
502 }
503 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
504
505 DBG_LEAVE_ROUTINE
506 return pwr_fault;
507 }
508
509 static int hpc_set_attention_status(struct slot *slot, u8 value)
510 {
511 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
512 u16 slot_cmd = 0;
513 u16 slot_ctrl;
514 int rc = 0;
515
516 DBG_ENTER_ROUTINE
517
518 if (!php_ctlr) {
519 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
520 return -1;
521 }
522
523 if (slot->hp_slot >= php_ctlr->num_slots) {
524 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
525 return -1;
526 }
527 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
528
529 if (rc) {
530 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
531 return rc;
532 }
533
534 switch (value) {
535 case 0 : /* turn off */
536 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x00C0;
537 break;
538 case 1: /* turn on */
539 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0040;
540 break;
541 case 2: /* turn blink */
542 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0080;
543 break;
544 default:
545 return -1;
546 }
547 if (!pciehp_poll_mode)
548 slot_cmd = slot_cmd | HP_INTR_ENABLE;
549
550 pcie_write_cmd(slot, slot_cmd);
551 dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
552
553 DBG_LEAVE_ROUTINE
554 return rc;
555 }
556
557
558 static void hpc_set_green_led_on(struct slot *slot)
559 {
560 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
561 u16 slot_cmd;
562 u16 slot_ctrl;
563 int rc = 0;
564
565 DBG_ENTER_ROUTINE
566
567 if (!php_ctlr) {
568 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
569 return ;
570 }
571
572 if (slot->hp_slot >= php_ctlr->num_slots) {
573 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
574 return ;
575 }
576
577 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
578
579 if (rc) {
580 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
581 return;
582 }
583 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0100;
584 if (!pciehp_poll_mode)
585 slot_cmd = slot_cmd | HP_INTR_ENABLE;
586
587 pcie_write_cmd(slot, slot_cmd);
588
589 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
590 DBG_LEAVE_ROUTINE
591 return;
592 }
593
594 static void hpc_set_green_led_off(struct slot *slot)
595 {
596 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
597 u16 slot_cmd;
598 u16 slot_ctrl;
599 int rc = 0;
600
601 DBG_ENTER_ROUTINE
602
603 if (!php_ctlr) {
604 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
605 return ;
606 }
607
608 if (slot->hp_slot >= php_ctlr->num_slots) {
609 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
610 return ;
611 }
612
613 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
614
615 if (rc) {
616 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
617 return;
618 }
619
620 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0300;
621
622 if (!pciehp_poll_mode)
623 slot_cmd = slot_cmd | HP_INTR_ENABLE;
624 pcie_write_cmd(slot, slot_cmd);
625 dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
626
627 DBG_LEAVE_ROUTINE
628 return;
629 }
630
631 static void hpc_set_green_led_blink(struct slot *slot)
632 {
633 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
634 u16 slot_cmd;
635 u16 slot_ctrl;
636 int rc = 0;
637
638 DBG_ENTER_ROUTINE
639
640 if (!php_ctlr) {
641 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
642 return ;
643 }
644
645 if (slot->hp_slot >= php_ctlr->num_slots) {
646 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
647 return ;
648 }
649
650 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
651
652 if (rc) {
653 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
654 return;
655 }
656
657 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0200;
658
659 if (!pciehp_poll_mode)
660 slot_cmd = slot_cmd | HP_INTR_ENABLE;
661 pcie_write_cmd(slot, slot_cmd);
662
663 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
664 DBG_LEAVE_ROUTINE
665 return;
666 }
667
668 int pcie_get_ctlr_slot_config(struct controller *ctrl,
669 int *num_ctlr_slots, /* number of slots in this HPC; only 1 in PCIE */
670 int *first_device_num, /* PCI dev num of the first slot in this PCIE */
671 int *physical_slot_num, /* phy slot num of the first slot in this PCIE */
672 u8 *ctrlcap)
673 {
674 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
675 u32 slot_cap;
676 int rc = 0;
677
678 DBG_ENTER_ROUTINE
679
680 if (!php_ctlr) {
681 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
682 return -1;
683 }
684
685 *first_device_num = 0;
686 *num_ctlr_slots = 1;
687
688 rc = hp_register_read_dword(php_ctlr->pci_dev, SLOT_CAP(ctrl->cap_base), slot_cap);
689
690 if (rc) {
691 err("%s : hp_register_read_dword SLOT_CAP failed\n", __FUNCTION__);
692 return -1;
693 }
694
695 *physical_slot_num = slot_cap >> 19;
696 dbg("%s: PSN %d \n", __FUNCTION__, *physical_slot_num);
697
698 *ctrlcap = slot_cap & 0x0000007f;
699
700 DBG_LEAVE_ROUTINE
701 return 0;
702 }
703
704 static void hpc_release_ctlr(struct controller *ctrl)
705 {
706 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
707 struct php_ctlr_state_s *p, *p_prev;
708
709 DBG_ENTER_ROUTINE
710
711 if (!php_ctlr) {
712 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
713 return ;
714 }
715
716 if (pciehp_poll_mode) {
717 del_timer(&php_ctlr->int_poll_timer);
718 } else {
719 if (php_ctlr->irq) {
720 free_irq(php_ctlr->irq, ctrl);
721 php_ctlr->irq = 0;
722 if (!pcie_mch_quirk)
723 pci_disable_msi(php_ctlr->pci_dev);
724 }
725 }
726 if (php_ctlr->pci_dev)
727 php_ctlr->pci_dev = NULL;
728
729 spin_lock(&list_lock);
730 p = php_ctlr_list_head;
731 p_prev = NULL;
732 while (p) {
733 if (p == php_ctlr) {
734 if (p_prev)
735 p_prev->pnext = p->pnext;
736 else
737 php_ctlr_list_head = p->pnext;
738 break;
739 } else {
740 p_prev = p;
741 p = p->pnext;
742 }
743 }
744 spin_unlock(&list_lock);
745
746 kfree(php_ctlr);
747
748 DBG_LEAVE_ROUTINE
749
750 }
751
752 static int hpc_power_on_slot(struct slot * slot)
753 {
754 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
755 u16 slot_cmd;
756 u16 slot_ctrl, slot_status;
757
758 int retval = 0;
759
760 DBG_ENTER_ROUTINE
761
762 if (!php_ctlr) {
763 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
764 return -1;
765 }
766
767 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
768 if (slot->hp_slot >= php_ctlr->num_slots) {
769 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
770 return -1;
771 }
772
773 /* Clear sticky power-fault bit from previous power failures */
774 hp_register_read_word(php_ctlr->pci_dev,
775 SLOT_STATUS(slot->ctrl->cap_base), slot_status);
776 slot_status &= PWR_FAULT_DETECTED;
777 if (slot_status)
778 hp_register_write_word(php_ctlr->pci_dev,
779 SLOT_STATUS(slot->ctrl->cap_base), slot_status);
780
781 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
782
783 if (retval) {
784 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
785 return retval;
786 }
787
788 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_ON;
789
790 if (!pciehp_poll_mode)
791 slot_cmd = slot_cmd | HP_INTR_ENABLE;
792
793 retval = pcie_write_cmd(slot, slot_cmd);
794
795 if (retval) {
796 err("%s: Write %x command failed!\n", __FUNCTION__, slot_cmd);
797 return -1;
798 }
799 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
800
801 DBG_LEAVE_ROUTINE
802
803 return retval;
804 }
805
806 static int hpc_power_off_slot(struct slot * slot)
807 {
808 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
809 u16 slot_cmd;
810 u16 slot_ctrl;
811
812 int retval = 0;
813
814 DBG_ENTER_ROUTINE
815
816 if (!php_ctlr) {
817 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
818 return -1;
819 }
820
821 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
822 slot->hp_slot = 0;
823 if (slot->hp_slot >= php_ctlr->num_slots) {
824 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
825 return -1;
826 }
827 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
828
829 if (retval) {
830 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
831 return retval;
832 }
833
834 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_OFF;
835
836 if (!pciehp_poll_mode)
837 slot_cmd = slot_cmd | HP_INTR_ENABLE;
838
839 retval = pcie_write_cmd(slot, slot_cmd);
840
841 if (retval) {
842 err("%s: Write command failed!\n", __FUNCTION__);
843 return -1;
844 }
845 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
846
847 DBG_LEAVE_ROUTINE
848
849 return retval;
850 }
851
852 static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs)
853 {
854 struct controller *ctrl = NULL;
855 struct php_ctlr_state_s *php_ctlr;
856 u8 schedule_flag = 0;
857 u16 slot_status, intr_detect, intr_loc;
858 u16 temp_word;
859 int hp_slot = 0; /* only 1 slot per PCI Express port */
860 int rc = 0;
861
862 if (!dev_id)
863 return IRQ_NONE;
864
865 if (!pciehp_poll_mode) {
866 ctrl = dev_id;
867 php_ctlr = ctrl->hpc_ctlr_handle;
868 } else {
869 php_ctlr = dev_id;
870 ctrl = (struct controller *)php_ctlr->callback_instance_id;
871 }
872
873 if (!ctrl) {
874 dbg("%s: dev_id %p ctlr == NULL\n", __FUNCTION__, (void*) dev_id);
875 return IRQ_NONE;
876 }
877
878 if (!php_ctlr) {
879 dbg("%s: php_ctlr == NULL\n", __FUNCTION__);
880 return IRQ_NONE;
881 }
882
883 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
884 if (rc) {
885 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
886 return IRQ_NONE;
887 }
888
889 intr_detect = ( ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | MRL_SENS_CHANGED |
890 PRSN_DETECT_CHANGED | CMD_COMPLETED );
891
892 intr_loc = slot_status & intr_detect;
893
894 /* Check to see if it was our interrupt */
895 if ( !intr_loc )
896 return IRQ_NONE;
897
898 dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
899 /* Mask Hot-plug Interrupt Enable */
900 if (!pciehp_poll_mode) {
901 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
902 if (rc) {
903 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
904 return IRQ_NONE;
905 }
906
907 dbg("%s: hp_register_read_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word);
908 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
909
910 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
911 if (rc) {
912 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
913 return IRQ_NONE;
914 }
915
916 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
917 if (rc) {
918 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
919 return IRQ_NONE;
920 }
921 dbg("%s: hp_register_read_word SLOT_STATUS with value %x\n", __FUNCTION__, slot_status);
922
923 /* Clear command complete interrupt caused by this write */
924 temp_word = 0x1f;
925 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
926 if (rc) {
927 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
928 return IRQ_NONE;
929 }
930 }
931
932 if (intr_loc & CMD_COMPLETED) {
933 /*
934 * Command Complete Interrupt Pending
935 */
936 wake_up_interruptible(&ctrl->queue);
937 }
938
939 if ((php_ctlr->switch_change_callback) && (intr_loc & MRL_SENS_CHANGED))
940 schedule_flag += php_ctlr->switch_change_callback(
941 hp_slot, php_ctlr->callback_instance_id);
942 if ((php_ctlr->attention_button_callback) && (intr_loc & ATTN_BUTTN_PRESSED))
943 schedule_flag += php_ctlr->attention_button_callback(
944 hp_slot, php_ctlr->callback_instance_id);
945 if ((php_ctlr->presence_change_callback) && (intr_loc & PRSN_DETECT_CHANGED))
946 schedule_flag += php_ctlr->presence_change_callback(
947 hp_slot , php_ctlr->callback_instance_id);
948 if ((php_ctlr->power_fault_callback) && (intr_loc & PWR_FAULT_DETECTED))
949 schedule_flag += php_ctlr->power_fault_callback(
950 hp_slot, php_ctlr->callback_instance_id);
951
952 /* Clear all events after serving them */
953 temp_word = 0x1F;
954 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
955 if (rc) {
956 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
957 return IRQ_NONE;
958 }
959 /* Unmask Hot-plug Interrupt Enable */
960 if (!pciehp_poll_mode) {
961 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
962 if (rc) {
963 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
964 return IRQ_NONE;
965 }
966
967 dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__);
968 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
969
970 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
971 if (rc) {
972 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
973 return IRQ_NONE;
974 }
975
976 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
977 if (rc) {
978 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
979 return IRQ_NONE;
980 }
981
982 /* Clear command complete interrupt caused by this write */
983 temp_word = 0x1F;
984 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
985 if (rc) {
986 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
987 return IRQ_NONE;
988 }
989 dbg("%s: hp_register_write_word SLOT_STATUS with value %x\n", __FUNCTION__, temp_word);
990 }
991
992 return IRQ_HANDLED;
993 }
994
995 static int hpc_get_max_lnk_speed (struct slot *slot, enum pci_bus_speed *value)
996 {
997 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
998 enum pcie_link_speed lnk_speed;
999 u32 lnk_cap;
1000 int retval = 0;
1001
1002 DBG_ENTER_ROUTINE
1003
1004 if (!php_ctlr) {
1005 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1006 return -1;
1007 }
1008
1009 if (slot->hp_slot >= php_ctlr->num_slots) {
1010 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1011 return -1;
1012 }
1013
1014 retval = hp_register_read_dword(php_ctlr->pci_dev, LNK_CAP(slot->ctrl->cap_base), lnk_cap);
1015
1016 if (retval) {
1017 err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__);
1018 return retval;
1019 }
1020
1021 switch (lnk_cap & 0x000F) {
1022 case 1:
1023 lnk_speed = PCIE_2PT5GB;
1024 break;
1025 default:
1026 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
1027 break;
1028 }
1029
1030 *value = lnk_speed;
1031 dbg("Max link speed = %d\n", lnk_speed);
1032 DBG_LEAVE_ROUTINE
1033 return retval;
1034 }
1035
1036 static int hpc_get_max_lnk_width (struct slot *slot, enum pcie_link_width *value)
1037 {
1038 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1039 enum pcie_link_width lnk_wdth;
1040 u32 lnk_cap;
1041 int retval = 0;
1042
1043 DBG_ENTER_ROUTINE
1044
1045 if (!php_ctlr) {
1046 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1047 return -1;
1048 }
1049
1050 if (slot->hp_slot >= php_ctlr->num_slots) {
1051 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1052 return -1;
1053 }
1054
1055 retval = hp_register_read_dword(php_ctlr->pci_dev, LNK_CAP(slot->ctrl->cap_base), lnk_cap);
1056
1057 if (retval) {
1058 err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__);
1059 return retval;
1060 }
1061
1062 switch ((lnk_cap & 0x03F0) >> 4){
1063 case 0:
1064 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
1065 break;
1066 case 1:
1067 lnk_wdth = PCIE_LNK_X1;
1068 break;
1069 case 2:
1070 lnk_wdth = PCIE_LNK_X2;
1071 break;
1072 case 4:
1073 lnk_wdth = PCIE_LNK_X4;
1074 break;
1075 case 8:
1076 lnk_wdth = PCIE_LNK_X8;
1077 break;
1078 case 12:
1079 lnk_wdth = PCIE_LNK_X12;
1080 break;
1081 case 16:
1082 lnk_wdth = PCIE_LNK_X16;
1083 break;
1084 case 32:
1085 lnk_wdth = PCIE_LNK_X32;
1086 break;
1087 default:
1088 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1089 break;
1090 }
1091
1092 *value = lnk_wdth;
1093 dbg("Max link width = %d\n", lnk_wdth);
1094 DBG_LEAVE_ROUTINE
1095 return retval;
1096 }
1097
1098 static int hpc_get_cur_lnk_speed (struct slot *slot, enum pci_bus_speed *value)
1099 {
1100 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1101 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
1102 int retval = 0;
1103 u16 lnk_status;
1104
1105 DBG_ENTER_ROUTINE
1106
1107 if (!php_ctlr) {
1108 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1109 return -1;
1110 }
1111
1112 if (slot->hp_slot >= php_ctlr->num_slots) {
1113 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1114 return -1;
1115 }
1116
1117 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(slot->ctrl->cap_base), lnk_status);
1118
1119 if (retval) {
1120 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
1121 return retval;
1122 }
1123
1124 switch (lnk_status & 0x0F) {
1125 case 1:
1126 lnk_speed = PCIE_2PT5GB;
1127 break;
1128 default:
1129 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
1130 break;
1131 }
1132
1133 *value = lnk_speed;
1134 dbg("Current link speed = %d\n", lnk_speed);
1135 DBG_LEAVE_ROUTINE
1136 return retval;
1137 }
1138
1139 static int hpc_get_cur_lnk_width (struct slot *slot, enum pcie_link_width *value)
1140 {
1141 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1142 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1143 int retval = 0;
1144 u16 lnk_status;
1145
1146 DBG_ENTER_ROUTINE
1147
1148 if (!php_ctlr) {
1149 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1150 return -1;
1151 }
1152
1153 if (slot->hp_slot >= php_ctlr->num_slots) {
1154 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1155 return -1;
1156 }
1157
1158 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(slot->ctrl->cap_base), lnk_status);
1159
1160 if (retval) {
1161 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
1162 return retval;
1163 }
1164
1165 switch ((lnk_status & 0x03F0) >> 4){
1166 case 0:
1167 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
1168 break;
1169 case 1:
1170 lnk_wdth = PCIE_LNK_X1;
1171 break;
1172 case 2:
1173 lnk_wdth = PCIE_LNK_X2;
1174 break;
1175 case 4:
1176 lnk_wdth = PCIE_LNK_X4;
1177 break;
1178 case 8:
1179 lnk_wdth = PCIE_LNK_X8;
1180 break;
1181 case 12:
1182 lnk_wdth = PCIE_LNK_X12;
1183 break;
1184 case 16:
1185 lnk_wdth = PCIE_LNK_X16;
1186 break;
1187 case 32:
1188 lnk_wdth = PCIE_LNK_X32;
1189 break;
1190 default:
1191 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1192 break;
1193 }
1194
1195 *value = lnk_wdth;
1196 dbg("Current link width = %d\n", lnk_wdth);
1197 DBG_LEAVE_ROUTINE
1198 return retval;
1199 }
1200
1201 static struct hpc_ops pciehp_hpc_ops = {
1202 .power_on_slot = hpc_power_on_slot,
1203 .power_off_slot = hpc_power_off_slot,
1204 .set_attention_status = hpc_set_attention_status,
1205 .get_power_status = hpc_get_power_status,
1206 .get_attention_status = hpc_get_attention_status,
1207 .get_latch_status = hpc_get_latch_status,
1208 .get_adapter_status = hpc_get_adapter_status,
1209
1210 .get_max_bus_speed = hpc_get_max_lnk_speed,
1211 .get_cur_bus_speed = hpc_get_cur_lnk_speed,
1212 .get_max_lnk_width = hpc_get_max_lnk_width,
1213 .get_cur_lnk_width = hpc_get_cur_lnk_width,
1214
1215 .query_power_fault = hpc_query_power_fault,
1216 .green_led_on = hpc_set_green_led_on,
1217 .green_led_off = hpc_set_green_led_off,
1218 .green_led_blink = hpc_set_green_led_blink,
1219
1220 .release_ctlr = hpc_release_ctlr,
1221 .check_lnk_status = hpc_check_lnk_status,
1222 };
1223
1224 int pcie_init(struct controller * ctrl, struct pcie_device *dev)
1225 {
1226 struct php_ctlr_state_s *php_ctlr, *p;
1227 void *instance_id = ctrl;
1228 int rc;
1229 static int first = 1;
1230 u16 temp_word;
1231 u16 cap_reg;
1232 u16 intr_enable = 0;
1233 u32 slot_cap;
1234 int cap_base, saved_cap_base;
1235 u16 slot_status, slot_ctrl;
1236 struct pci_dev *pdev;
1237
1238 DBG_ENTER_ROUTINE
1239
1240 spin_lock_init(&list_lock);
1241 php_ctlr = (struct php_ctlr_state_s *) kmalloc(sizeof(struct php_ctlr_state_s), GFP_KERNEL);
1242
1243 if (!php_ctlr) { /* allocate controller state data */
1244 err("%s: HPC controller memory allocation error!\n", __FUNCTION__);
1245 goto abort;
1246 }
1247
1248 memset(php_ctlr, 0, sizeof(struct php_ctlr_state_s));
1249
1250 pdev = dev->port;
1251 php_ctlr->pci_dev = pdev; /* save pci_dev in context */
1252
1253 dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n",
1254 __FUNCTION__, pdev->vendor, pdev->device);
1255
1256 saved_cap_base = pcie_cap_base;
1257
1258 if ((cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP)) == 0) {
1259 dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__);
1260 goto abort_free_ctlr;
1261 }
1262
1263 ctrl->cap_base = cap_base;
1264
1265 dbg("%s: pcie_cap_base %x\n", __FUNCTION__, pcie_cap_base);
1266
1267 rc = hp_register_read_word(pdev, CAP_REG(ctrl->cap_base), cap_reg);
1268 if (rc) {
1269 err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__);
1270 goto abort_free_ctlr;
1271 }
1272 dbg("%s: CAP_REG offset %x cap_reg %x\n", __FUNCTION__, CAP_REG(ctrl->cap_base), cap_reg);
1273
1274 if (((cap_reg & SLOT_IMPL) == 0) || (((cap_reg & DEV_PORT_TYPE) != 0x0040)
1275 && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) {
1276 dbg("%s : This is not a root port or the port is not connected to a slot\n", __FUNCTION__);
1277 goto abort_free_ctlr;
1278 }
1279
1280 rc = hp_register_read_dword(php_ctlr->pci_dev, SLOT_CAP(ctrl->cap_base), slot_cap);
1281 if (rc) {
1282 err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__);
1283 goto abort_free_ctlr;
1284 }
1285 dbg("%s: SLOT_CAP offset %x slot_cap %x\n", __FUNCTION__, SLOT_CAP(ctrl->cap_base), slot_cap);
1286
1287 if (!(slot_cap & HP_CAP)) {
1288 dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__);
1289 goto abort_free_ctlr;
1290 }
1291 /* For debugging purpose */
1292 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1293 if (rc) {
1294 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1295 goto abort_free_ctlr;
1296 }
1297 dbg("%s: SLOT_STATUS offset %x slot_status %x\n", __FUNCTION__, SLOT_STATUS(ctrl->cap_base), slot_status);
1298
1299 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), slot_ctrl);
1300 if (rc) {
1301 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1302 goto abort_free_ctlr;
1303 }
1304 dbg("%s: SLOT_CTRL offset %x slot_ctrl %x\n", __FUNCTION__, SLOT_CTRL(ctrl->cap_base), slot_ctrl);
1305
1306 if (first) {
1307 spin_lock_init(&hpc_event_lock);
1308 first = 0;
1309 }
1310
1311 for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
1312 if (pci_resource_len(pdev, rc) > 0)
1313 dbg("pci resource[%d] start=0x%lx(len=0x%lx)\n", rc,
1314 pci_resource_start(pdev, rc), pci_resource_len(pdev, rc));
1315
1316 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device,
1317 pdev->subsystem_vendor, pdev->subsystem_device);
1318
1319 if (pci_enable_device(pdev))
1320 goto abort_free_ctlr;
1321
1322 init_MUTEX(&ctrl->crit_sect);
1323 /* setup wait queue */
1324 init_waitqueue_head(&ctrl->queue);
1325
1326 /* find the IRQ */
1327 php_ctlr->irq = dev->irq;
1328
1329 /* Save interrupt callback info */
1330 php_ctlr->attention_button_callback = pciehp_handle_attention_button;
1331 php_ctlr->switch_change_callback = pciehp_handle_switch_change;
1332 php_ctlr->presence_change_callback = pciehp_handle_presence_change;
1333 php_ctlr->power_fault_callback = pciehp_handle_power_fault;
1334 php_ctlr->callback_instance_id = instance_id;
1335
1336 /* return PCI Controller Info */
1337 php_ctlr->slot_device_offset = 0;
1338 php_ctlr->num_slots = 1;
1339
1340 /* Mask Hot-plug Interrupt Enable */
1341 rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1342 if (rc) {
1343 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1344 goto abort_free_ctlr;
1345 }
1346
1347 dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL(ctrl->cap_base), temp_word);
1348 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
1349
1350 rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1351 if (rc) {
1352 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
1353 goto abort_free_ctlr;
1354 }
1355
1356 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1357 if (rc) {
1358 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1359 goto abort_free_ctlr;
1360 }
1361
1362 temp_word = 0x1F; /* Clear all events */
1363 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
1364 if (rc) {
1365 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
1366 goto abort_free_ctlr;
1367 }
1368
1369 if (pciehp_poll_mode) {/* Install interrupt polling code */
1370 /* Install and start the interrupt polling timer */
1371 init_timer(&php_ctlr->int_poll_timer);
1372 start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */
1373 } else {
1374 /* Installs the interrupt handler */
1375 rc = request_irq(php_ctlr->irq, pcie_isr, SA_SHIRQ, MY_NAME, (void *) ctrl);
1376 dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc);
1377 if (rc) {
1378 err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq);
1379 goto abort_free_ctlr;
1380 }
1381 }
1382
1383 dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number,
1384 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq);
1385
1386 rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1387 if (rc) {
1388 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1389 goto abort_free_ctlr;
1390 }
1391
1392 intr_enable = intr_enable | PRSN_DETECT_ENABLE;
1393
1394 if (ATTN_BUTTN(slot_cap))
1395 intr_enable = intr_enable | ATTN_BUTTN_ENABLE;
1396
1397 if (POWER_CTRL(slot_cap))
1398 intr_enable = intr_enable | PWR_FAULT_DETECT_ENABLE;
1399
1400 if (MRL_SENS(slot_cap))
1401 intr_enable = intr_enable | MRL_DETECT_ENABLE;
1402
1403 temp_word = (temp_word & ~intr_enable) | intr_enable;
1404
1405 if (pciehp_poll_mode) {
1406 temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0;
1407 } else {
1408 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
1409 }
1410
1411 /* Unmask Hot-plug Interrupt Enable for the interrupt notification mechanism case */
1412 rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1413 if (rc) {
1414 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
1415 goto abort_free_ctlr;
1416 }
1417 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1418 if (rc) {
1419 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1420 goto abort_free_ctlr;
1421 }
1422
1423 temp_word = 0x1F; /* Clear all events */
1424 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
1425 if (rc) {
1426 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
1427 goto abort_free_ctlr;
1428 }
1429
1430 if (pciehp_force) {
1431 dbg("Bypassing BIOS check for pciehp use on %s\n",
1432 pci_name(ctrl->pci_dev));
1433 } else {
1434 rc = pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev);
1435 if (rc)
1436 goto abort_free_ctlr;
1437 }
1438
1439 /* Add this HPC instance into the HPC list */
1440 spin_lock(&list_lock);
1441 if (php_ctlr_list_head == 0) {
1442 php_ctlr_list_head = php_ctlr;
1443 p = php_ctlr_list_head;
1444 p->pnext = NULL;
1445 } else {
1446 p = php_ctlr_list_head;
1447
1448 while (p->pnext)
1449 p = p->pnext;
1450
1451 p->pnext = php_ctlr;
1452 }
1453 spin_unlock(&list_lock);
1454
1455 ctlr_seq_num++;
1456 ctrl->hpc_ctlr_handle = php_ctlr;
1457 ctrl->hpc_ops = &pciehp_hpc_ops;
1458
1459 DBG_LEAVE_ROUTINE
1460 return 0;
1461
1462 /* We end up here for the many possible ways to fail this API. */
1463 abort_free_ctlr:
1464 pcie_cap_base = saved_cap_base;
1465 kfree(php_ctlr);
1466 abort:
1467 DBG_LEAVE_ROUTINE
1468 return -1;
1469 }
Verdex Pro support