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[PATCH] UFS: inode->i_sem is not released in error path
[linux-2.6/verdex.git] / drivers / serial / s3c2410.c
blobfe83ce6fef52a5ad3a64fb0df9154fe337c2d50e
1 /*
2 * linux/drivers/serial/s3c2410.c
3 *
4 * Driver for onboard UARTs on the Samsung S3C24XX
5 *
6 * Based on drivers/char/serial.c and drivers/char/21285.c
7 *
8 * Ben Dooks, (c) 2003-2005 Simtec Electronics
9 * http://www.simtec.co.uk/products/SWLINUX/
10 *
11 * Changelog:
12 *
13 * 22-Jul-2004 BJD Finished off device rewrite
14 *
15 * 21-Jul-2004 BJD Thanks to <herbet@13thfloor.at> for pointing out
16 * problems with baud rate and loss of IR settings. Update
17 * to add configuration via platform_device structure
18 *
19 * 28-Sep-2004 BJD Re-write for the following items
20 * - S3C2410 and S3C2440 serial support
21 * - Power Management support
22 * - Fix console via IrDA devices
23 * - SysReq (Herbert Pötzl)
24 * - Break character handling (Herbert Pötzl)
25 * - spin-lock initialisation (Dimitry Andric)
26 * - added clock control
27 * - updated init code to use platform_device info
28 *
29 * 06-Mar-2005 BJD Add s3c2440 fclk clock source
30 *
31 * 09-Mar-2005 BJD Add s3c2400 support
32 *
33 * 10-Mar-2005 LCVR Changed S3C2410_VA_UART to S3C24XX_VA_UART
34 */
35
36 /* Note on 2440 fclk clock source handling
37 *
38 * Whilst it is possible to use the fclk as clock source, the method
39 * of properly switching too/from this is currently un-implemented, so
40 * whichever way is configured at startup is the one that will be used.
41 */
42
43 /* Hote on 2410 error handling
44 *
45 * The s3c2410 manual has a love/hate affair with the contents of the
46 * UERSTAT register in the UART blocks, and keeps marking some of the
47 * error bits as reserved. Having checked with the s3c2410x01,
48 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
49 * feature from the latter versions of the manual.
50 *
51 * If it becomes aparrent that latter versions of the 2410 remove these
52 * bits, then action will have to be taken to differentiate the versions
53 * and change the policy on BREAK
54 *
55 * BJD, 04-Nov-2004
56 */
57
58 #include <linux/config.h>
59
60 #if defined(CONFIG_SERIAL_S3C2410_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
61 #define SUPPORT_SYSRQ
62 #endif
63
64 #include <linux/module.h>
65 #include <linux/ioport.h>
66 #include <linux/platform_device.h>
67 #include <linux/init.h>
68 #include <linux/sysrq.h>
69 #include <linux/console.h>
70 #include <linux/tty.h>
71 #include <linux/tty_flip.h>
72 #include <linux/serial_core.h>
73 #include <linux/serial.h>
74 #include <linux/delay.h>
75 #include <linux/clk.h>
76
77 #include <asm/io.h>
78 #include <asm/irq.h>
79
80 #include <asm/hardware.h>
81
82 #include <asm/arch/regs-serial.h>
83 #include <asm/arch/regs-gpio.h>
84
85 /* structures */
86
87 struct s3c24xx_uart_info {
88 char *name;
89 unsigned int type;
90 unsigned int fifosize;
91 unsigned long rx_fifomask;
92 unsigned long rx_fifoshift;
93 unsigned long rx_fifofull;
94 unsigned long tx_fifomask;
95 unsigned long tx_fifoshift;
96 unsigned long tx_fifofull;
97
98 /* clock source control */
99
100 int (*get_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
101 int (*set_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
102
103 /* uart controls */
104 int (*reset_port)(struct uart_port *, struct s3c2410_uartcfg *);
105 };
106
107 struct s3c24xx_uart_port {
108 unsigned char rx_claimed;
109 unsigned char tx_claimed;
110
111 struct s3c24xx_uart_info *info;
112 struct s3c24xx_uart_clksrc *clksrc;
113 struct clk *clk;
114 struct clk *baudclk;
115 struct uart_port port;
116 };
117
118
119 /* configuration defines */
120
121 #if 0
122 #if 1
123 /* send debug to the low-level output routines */
124
125 extern void printascii(const char *);
126
127 static void
128 s3c24xx_serial_dbg(const char *fmt, ...)
129 {
130 va_list va;
131 char buff[256];
132
133 va_start(va, fmt);
134 vsprintf(buff, fmt, va);
135 va_end(va);
136
137 printascii(buff);
138 }
139
140 #define dbg(x...) s3c24xx_serial_dbg(x)
141
142 #else
143 #define dbg(x...) printk(KERN_DEBUG "s3c24xx: ");
144 #endif
145 #else /* no debug */
146 #define dbg(x...) do {} while(0)
147 #endif
148
149 /* UART name and device definitions */
150
151 #define S3C24XX_SERIAL_NAME "ttySAC"
152 #define S3C24XX_SERIAL_DEVFS "tts/"
153 #define S3C24XX_SERIAL_MAJOR 204
154 #define S3C24XX_SERIAL_MINOR 64
155
156
157 /* conversion functions */
158
159 #define s3c24xx_dev_to_port(__dev) (struct uart_port *)dev_get_drvdata(__dev)
160 #define s3c24xx_dev_to_cfg(__dev) (struct s3c2410_uartcfg *)((__dev)->platform_data)
161
162 /* we can support 3 uarts, but not always use them */
163
164 #define NR_PORTS (3)
165
166 /* port irq numbers */
167
168 #define TX_IRQ(port) ((port)->irq + 1)
169 #define RX_IRQ(port) ((port)->irq)
170
171 /* register access controls */
172
173 #define portaddr(port, reg) ((port)->membase + (reg))
174
175 #define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
176 #define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
177
178 #define wr_regb(port, reg, val) \
179 do { __raw_writeb(val, portaddr(port, reg)); } while(0)
180
181 #define wr_regl(port, reg, val) \
182 do { __raw_writel(val, portaddr(port, reg)); } while(0)
183
184 /* macros to change one thing to another */
185
186 #define tx_enabled(port) ((port)->unused[0])
187 #define rx_enabled(port) ((port)->unused[1])
188
189 /* flag to ignore all characters comming in */
190 #define RXSTAT_DUMMY_READ (0x10000000)
191
192 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
193 {
194 return container_of(port, struct s3c24xx_uart_port, port);
195 }
196
197 /* translate a port to the device name */
198
199 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
200 {
201 return to_platform_device(port->dev)->name;
202 }
203
204 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
205 {
206 return (rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE);
207 }
208
209 static void s3c24xx_serial_rx_enable(struct uart_port *port)
210 {
211 unsigned long flags;
212 unsigned int ucon, ufcon;
213 int count = 10000;
214
215 spin_lock_irqsave(&port->lock, flags);
216
217 while (--count && !s3c24xx_serial_txempty_nofifo(port))
218 udelay(100);
219
220 ufcon = rd_regl(port, S3C2410_UFCON);
221 ufcon |= S3C2410_UFCON_RESETRX;
222 wr_regl(port, S3C2410_UFCON, ufcon);
223
224 ucon = rd_regl(port, S3C2410_UCON);
225 ucon |= S3C2410_UCON_RXIRQMODE;
226 wr_regl(port, S3C2410_UCON, ucon);
227
228 rx_enabled(port) = 1;
229 spin_unlock_irqrestore(&port->lock, flags);
230 }
231
232 static void s3c24xx_serial_rx_disable(struct uart_port *port)
233 {
234 unsigned long flags;
235 unsigned int ucon;
236
237 spin_lock_irqsave(&port->lock, flags);
238
239 ucon = rd_regl(port, S3C2410_UCON);
240 ucon &= ~S3C2410_UCON_RXIRQMODE;
241 wr_regl(port, S3C2410_UCON, ucon);
242
243 rx_enabled(port) = 0;
244 spin_unlock_irqrestore(&port->lock, flags);
245 }
246
247 static void s3c24xx_serial_stop_tx(struct uart_port *port)
248 {
249 if (tx_enabled(port)) {
250 disable_irq(TX_IRQ(port));
251 tx_enabled(port) = 0;
252 if (port->flags & UPF_CONS_FLOW)
253 s3c24xx_serial_rx_enable(port);
254 }
255 }
256
257 static void s3c24xx_serial_start_tx(struct uart_port *port)
258 {
259 if (!tx_enabled(port)) {
260 if (port->flags & UPF_CONS_FLOW)
261 s3c24xx_serial_rx_disable(port);
262
263 enable_irq(TX_IRQ(port));
264 tx_enabled(port) = 1;
265 }
266 }
267
268
269 static void s3c24xx_serial_stop_rx(struct uart_port *port)
270 {
271 if (rx_enabled(port)) {
272 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
273 disable_irq(RX_IRQ(port));
274 rx_enabled(port) = 0;
275 }
276 }
277
278 static void s3c24xx_serial_enable_ms(struct uart_port *port)
279 {
280 }
281
282 static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
283 {
284 return to_ourport(port)->info;
285 }
286
287 static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
288 {
289 if (port->dev == NULL)
290 return NULL;
291
292 return (struct s3c2410_uartcfg *)port->dev->platform_data;
293 }
294
295 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
296 unsigned long ufstat)
297 {
298 struct s3c24xx_uart_info *info = ourport->info;
299
300 if (ufstat & info->rx_fifofull)
301 return info->fifosize;
302
303 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
304 }
305
306
307 /* ? - where has parity gone?? */
308 #define S3C2410_UERSTAT_PARITY (0x1000)
309
310 static irqreturn_t
311 s3c24xx_serial_rx_chars(int irq, void *dev_id, struct pt_regs *regs)
312 {
313 struct s3c24xx_uart_port *ourport = dev_id;
314 struct uart_port *port = &ourport->port;
315 struct tty_struct *tty = port->info->tty;
316 unsigned int ufcon, ch, flag, ufstat, uerstat;
317 int max_count = 64;
318
319 while (max_count-- > 0) {
320 ufcon = rd_regl(port, S3C2410_UFCON);
321 ufstat = rd_regl(port, S3C2410_UFSTAT);
322
323 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
324 break;
325
326 if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
327 if (tty->low_latency)
328 tty_flip_buffer_push(tty);
329
330 /*
331 * If this failed then we will throw away the
332 * bytes but must do so to clear interrupts
333 */
334 }
335
336 uerstat = rd_regl(port, S3C2410_UERSTAT);
337 ch = rd_regb(port, S3C2410_URXH);
338
339 if (port->flags & UPF_CONS_FLOW) {
340 int txe = s3c24xx_serial_txempty_nofifo(port);
341
342 if (rx_enabled(port)) {
343 if (!txe) {
344 rx_enabled(port) = 0;
345 continue;
346 }
347 } else {
348 if (txe) {
349 ufcon |= S3C2410_UFCON_RESETRX;
350 wr_regl(port, S3C2410_UFCON, ufcon);
351 rx_enabled(port) = 1;
352 goto out;
353 }
354 continue;
355 }
356 }
357
358 /* insert the character into the buffer */
359
360 flag = TTY_NORMAL;
361 port->icount.rx++;
362
363 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
364 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
365 ch, uerstat);
366
367 /* check for break */
368 if (uerstat & S3C2410_UERSTAT_BREAK) {
369 dbg("break!\n");
370 port->icount.brk++;
371 if (uart_handle_break(port))
372 goto ignore_char;
373 }
374
375 if (uerstat & S3C2410_UERSTAT_FRAME)
376 port->icount.frame++;
377 if (uerstat & S3C2410_UERSTAT_OVERRUN)
378 port->icount.overrun++;
379
380 uerstat &= port->read_status_mask;
381
382 if (uerstat & S3C2410_UERSTAT_BREAK)
383 flag = TTY_BREAK;
384 else if (uerstat & S3C2410_UERSTAT_PARITY)
385 flag = TTY_PARITY;
386 else if (uerstat & ( S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_OVERRUN))
387 flag = TTY_FRAME;
388 }
389
390 if (uart_handle_sysrq_char(port, ch, regs))
391 goto ignore_char;
392
393 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN, ch, flag);
394
395 ignore_char:
396 continue;
397 }
398 tty_flip_buffer_push(tty);
399
400 out:
401 return IRQ_HANDLED;
402 }
403
404 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id, struct pt_regs *regs)
405 {
406 struct s3c24xx_uart_port *ourport = id;
407 struct uart_port *port = &ourport->port;
408 struct circ_buf *xmit = &port->info->xmit;
409 int count = 256;
410
411 if (port->x_char) {
412 wr_regb(port, S3C2410_UTXH, port->x_char);
413 port->icount.tx++;
414 port->x_char = 0;
415 goto out;
416 }
417
418 /* if there isnt anything more to transmit, or the uart is now
419 * stopped, disable the uart and exit
420 */
421
422 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
423 s3c24xx_serial_stop_tx(port);
424 goto out;
425 }
426
427 /* try and drain the buffer... */
428
429 while (!uart_circ_empty(xmit) && count-- > 0) {
430 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
431 break;
432
433 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
434 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
435 port->icount.tx++;
436 }
437
438 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
439 uart_write_wakeup(port);
440
441 if (uart_circ_empty(xmit))
442 s3c24xx_serial_stop_tx(port);
443
444 out:
445 return IRQ_HANDLED;
446 }
447
448 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
449 {
450 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
451 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
452 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
453
454 if (ufcon & S3C2410_UFCON_FIFOMODE) {
455 if ((ufstat & info->tx_fifomask) != 0 ||
456 (ufstat & info->tx_fifofull))
457 return 0;
458
459 return 1;
460 }
461
462 return s3c24xx_serial_txempty_nofifo(port);
463 }
464
465 /* no modem control lines */
466 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
467 {
468 unsigned int umstat = rd_regb(port,S3C2410_UMSTAT);
469
470 if (umstat & S3C2410_UMSTAT_CTS)
471 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
472 else
473 return TIOCM_CAR | TIOCM_DSR;
474 }
475
476 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
477 {
478 /* todo - possibly remove AFC and do manual CTS */
479 }
480
481 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
482 {
483 unsigned long flags;
484 unsigned int ucon;
485
486 spin_lock_irqsave(&port->lock, flags);
487
488 ucon = rd_regl(port, S3C2410_UCON);
489
490 if (break_state)
491 ucon |= S3C2410_UCON_SBREAK;
492 else
493 ucon &= ~S3C2410_UCON_SBREAK;
494
495 wr_regl(port, S3C2410_UCON, ucon);
496
497 spin_unlock_irqrestore(&port->lock, flags);
498 }
499
500 static void s3c24xx_serial_shutdown(struct uart_port *port)
501 {
502 struct s3c24xx_uart_port *ourport = to_ourport(port);
503
504 if (ourport->tx_claimed) {
505 free_irq(TX_IRQ(port), ourport);
506 tx_enabled(port) = 0;
507 ourport->tx_claimed = 0;
508 }
509
510 if (ourport->rx_claimed) {
511 free_irq(RX_IRQ(port), ourport);
512 ourport->rx_claimed = 0;
513 rx_enabled(port) = 0;
514 }
515 }
516
517
518 static int s3c24xx_serial_startup(struct uart_port *port)
519 {
520 struct s3c24xx_uart_port *ourport = to_ourport(port);
521 int ret;
522
523 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
524 port->mapbase, port->membase);
525
526 rx_enabled(port) = 1;
527
528 ret = request_irq(RX_IRQ(port),
529 s3c24xx_serial_rx_chars, 0,
530 s3c24xx_serial_portname(port), ourport);
531
532 if (ret != 0) {
533 printk(KERN_ERR "cannot get irq %d\n", RX_IRQ(port));
534 return ret;
535 }
536
537 ourport->rx_claimed = 1;
538
539 dbg("requesting tx irq...\n");
540
541 tx_enabled(port) = 1;
542
543 ret = request_irq(TX_IRQ(port),
544 s3c24xx_serial_tx_chars, 0,
545 s3c24xx_serial_portname(port), ourport);
546
547 if (ret) {
548 printk(KERN_ERR "cannot get irq %d\n", TX_IRQ(port));
549 goto err;
550 }
551
552 ourport->tx_claimed = 1;
553
554 dbg("s3c24xx_serial_startup ok\n");
555
556 /* the port reset code should have done the correct
557 * register setup for the port controls */
558
559 return ret;
560
561 err:
562 s3c24xx_serial_shutdown(port);
563 return ret;
564 }
565
566 /* power power management control */
567
568 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
569 unsigned int old)
570 {
571 struct s3c24xx_uart_port *ourport = to_ourport(port);
572
573 switch (level) {
574 case 3:
575 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
576 clk_disable(ourport->baudclk);
577
578 clk_disable(ourport->clk);
579 break;
580
581 case 0:
582 clk_enable(ourport->clk);
583
584 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
585 clk_enable(ourport->baudclk);
586
587 break;
588 default:
589 printk(KERN_ERR "s3c24xx_serial: unknown pm %d\n", level);
590 }
591 }
592
593 /* baud rate calculation
594 *
595 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
596 * of different sources, including the peripheral clock ("pclk") and an
597 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
598 * with a programmable extra divisor.
599 *
600 * The following code goes through the clock sources, and calculates the
601 * baud clocks (and the resultant actual baud rates) and then tries to
602 * pick the closest one and select that.
603 *
604 */
605
606
607 #define MAX_CLKS (8)
608
609 static struct s3c24xx_uart_clksrc tmp_clksrc = {
610 .name = "pclk",
611 .min_baud = 0,
612 .max_baud = 0,
613 .divisor = 1,
614 };
615
616 static inline int
617 s3c24xx_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
618 {
619 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
620
621 return (info->get_clksrc)(port, c);
622 }
623
624 static inline int
625 s3c24xx_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
626 {
627 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
628
629 return (info->set_clksrc)(port, c);
630 }
631
632 struct baud_calc {
633 struct s3c24xx_uart_clksrc *clksrc;
634 unsigned int calc;
635 unsigned int quot;
636 struct clk *src;
637 };
638
639 static int s3c24xx_serial_calcbaud(struct baud_calc *calc,
640 struct uart_port *port,
641 struct s3c24xx_uart_clksrc *clksrc,
642 unsigned int baud)
643 {
644 unsigned long rate;
645
646 calc->src = clk_get(port->dev, clksrc->name);
647 if (calc->src == NULL || IS_ERR(calc->src))
648 return 0;
649
650 rate = clk_get_rate(calc->src);
651 rate /= clksrc->divisor;
652
653 calc->clksrc = clksrc;
654 calc->quot = (rate + (8 * baud)) / (16 * baud);
655 calc->calc = (rate / (calc->quot * 16));
656
657 calc->quot--;
658 return 1;
659 }
660
661 static unsigned int s3c24xx_serial_getclk(struct uart_port *port,
662 struct s3c24xx_uart_clksrc **clksrc,
663 struct clk **clk,
664 unsigned int baud)
665 {
666 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
667 struct s3c24xx_uart_clksrc *clkp;
668 struct baud_calc res[MAX_CLKS];
669 struct baud_calc *resptr, *best, *sptr;
670 int i;
671
672 clkp = cfg->clocks;
673 best = NULL;
674
675 if (cfg->clocks_size < 2) {
676 if (cfg->clocks_size == 0)
677 clkp = &tmp_clksrc;
678
679 /* check to see if we're sourcing fclk, and if so we're
680 * going to have to update the clock source
681 */
682
683 if (strcmp(clkp->name, "fclk") == 0) {
684 struct s3c24xx_uart_clksrc src;
685
686 s3c24xx_serial_getsource(port, &src);
687
688 /* check that the port already using fclk, and if
689 * not, then re-select fclk
690 */
691
692 if (strcmp(src.name, clkp->name) == 0) {
693 s3c24xx_serial_setsource(port, clkp);
694 s3c24xx_serial_getsource(port, &src);
695 }
696
697 clkp->divisor = src.divisor;
698 }
699
700 s3c24xx_serial_calcbaud(res, port, clkp, baud);
701 best = res;
702 resptr = best + 1;
703 } else {
704 resptr = res;
705
706 for (i = 0; i < cfg->clocks_size; i++, clkp++) {
707 if (s3c24xx_serial_calcbaud(resptr, port, clkp, baud))
708 resptr++;
709 }
710 }
711
712 /* ok, we now need to select the best clock we found */
713
714 if (!best) {
715 unsigned int deviation = (1<<30)|((1<<30)-1);
716 int calc_deviation;
717
718 for (sptr = res; sptr < resptr; sptr++) {
719 printk(KERN_DEBUG
720 "found clk %p (%s) quot %d, calc %d\n",
721 sptr->clksrc, sptr->clksrc->name,
722 sptr->quot, sptr->calc);
723
724 calc_deviation = baud - sptr->calc;
725 if (calc_deviation < 0)
726 calc_deviation = -calc_deviation;
727
728 if (calc_deviation < deviation) {
729 best = sptr;
730 deviation = calc_deviation;
731 }
732 }
733
734 printk(KERN_DEBUG "best %p (deviation %d)\n", best, deviation);
735 }
736
737 printk(KERN_DEBUG "selected clock %p (%s) quot %d, calc %d\n",
738 best->clksrc, best->clksrc->name, best->quot, best->calc);
739
740 /* store results to pass back */
741
742 *clksrc = best->clksrc;
743 *clk = best->src;
744
745 return best->quot;
746 }
747
748 static void s3c24xx_serial_set_termios(struct uart_port *port,
749 struct termios *termios,
750 struct termios *old)
751 {
752 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
753 struct s3c24xx_uart_port *ourport = to_ourport(port);
754 struct s3c24xx_uart_clksrc *clksrc = NULL;
755 struct clk *clk = NULL;
756 unsigned long flags;
757 unsigned int baud, quot;
758 unsigned int ulcon;
759 unsigned int umcon;
760
761 /*
762 * We don't support modem control lines.
763 */
764 termios->c_cflag &= ~(HUPCL | CMSPAR);
765 termios->c_cflag |= CLOCAL;
766
767 /*
768 * Ask the core to calculate the divisor for us.
769 */
770
771 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
772
773 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
774 quot = port->custom_divisor;
775 else
776 quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud);
777
778 /* check to see if we need to change clock source */
779
780 if (ourport->clksrc != clksrc || ourport->baudclk != clk) {
781 s3c24xx_serial_setsource(port, clksrc);
782
783 if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
784 clk_disable(ourport->baudclk);
785 ourport->baudclk = NULL;
786 }
787
788 clk_enable(clk);
789
790 ourport->clksrc = clksrc;
791 ourport->baudclk = clk;
792 }
793
794 switch (termios->c_cflag & CSIZE) {
795 case CS5:
796 dbg("config: 5bits/char\n");
797 ulcon = S3C2410_LCON_CS5;
798 break;
799 case CS6:
800 dbg("config: 6bits/char\n");
801 ulcon = S3C2410_LCON_CS6;
802 break;
803 case CS7:
804 dbg("config: 7bits/char\n");
805 ulcon = S3C2410_LCON_CS7;
806 break;
807 case CS8:
808 default:
809 dbg("config: 8bits/char\n");
810 ulcon = S3C2410_LCON_CS8;
811 break;
812 }
813
814 /* preserve original lcon IR settings */
815 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
816
817 if (termios->c_cflag & CSTOPB)
818 ulcon |= S3C2410_LCON_STOPB;
819
820 umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
821
822 if (termios->c_cflag & PARENB) {
823 if (termios->c_cflag & PARODD)
824 ulcon |= S3C2410_LCON_PODD;
825 else
826 ulcon |= S3C2410_LCON_PEVEN;
827 } else {
828 ulcon |= S3C2410_LCON_PNONE;
829 }
830
831 spin_lock_irqsave(&port->lock, flags);
832
833 dbg("setting ulcon to %08x, brddiv to %d\n", ulcon, quot);
834
835 wr_regl(port, S3C2410_ULCON, ulcon);
836 wr_regl(port, S3C2410_UBRDIV, quot);
837 wr_regl(port, S3C2410_UMCON, umcon);
838
839 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
840 rd_regl(port, S3C2410_ULCON),
841 rd_regl(port, S3C2410_UCON),
842 rd_regl(port, S3C2410_UFCON));
843
844 /*
845 * Update the per-port timeout.
846 */
847 uart_update_timeout(port, termios->c_cflag, baud);
848
849 /*
850 * Which character status flags are we interested in?
851 */
852 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
853 if (termios->c_iflag & INPCK)
854 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
855
856 /*
857 * Which character status flags should we ignore?
858 */
859 port->ignore_status_mask = 0;
860 if (termios->c_iflag & IGNPAR)
861 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
862 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
863 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
864
865 /*
866 * Ignore all characters if CREAD is not set.
867 */
868 if ((termios->c_cflag & CREAD) == 0)
869 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
870
871 spin_unlock_irqrestore(&port->lock, flags);
872 }
873
874 static const char *s3c24xx_serial_type(struct uart_port *port)
875 {
876 switch (port->type) {
877 case PORT_S3C2410:
878 return "S3C2410";
879 case PORT_S3C2440:
880 return "S3C2440";
881 default:
882 return NULL;
883 }
884 }
885
886 #define MAP_SIZE (0x100)
887
888 static void s3c24xx_serial_release_port(struct uart_port *port)
889 {
890 release_mem_region(port->mapbase, MAP_SIZE);
891 }
892
893 static int s3c24xx_serial_request_port(struct uart_port *port)
894 {
895 const char *name = s3c24xx_serial_portname(port);
896 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
897 }
898
899 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
900 {
901 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
902
903 if (flags & UART_CONFIG_TYPE &&
904 s3c24xx_serial_request_port(port) == 0)
905 port->type = info->type;
906 }
907
908 /*
909 * verify the new serial_struct (for TIOCSSERIAL).
910 */
911 static int
912 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
913 {
914 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
915
916 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
917 return -EINVAL;
918
919 return 0;
920 }
921
922
923 #ifdef CONFIG_SERIAL_S3C2410_CONSOLE
924
925 static struct console s3c24xx_serial_console;
926
927 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
928 #else
929 #define S3C24XX_SERIAL_CONSOLE NULL
930 #endif
931
932 static struct uart_ops s3c24xx_serial_ops = {
933 .pm = s3c24xx_serial_pm,
934 .tx_empty = s3c24xx_serial_tx_empty,
935 .get_mctrl = s3c24xx_serial_get_mctrl,
936 .set_mctrl = s3c24xx_serial_set_mctrl,
937 .stop_tx = s3c24xx_serial_stop_tx,
938 .start_tx = s3c24xx_serial_start_tx,
939 .stop_rx = s3c24xx_serial_stop_rx,
940 .enable_ms = s3c24xx_serial_enable_ms,
941 .break_ctl = s3c24xx_serial_break_ctl,
942 .startup = s3c24xx_serial_startup,
943 .shutdown = s3c24xx_serial_shutdown,
944 .set_termios = s3c24xx_serial_set_termios,
945 .type = s3c24xx_serial_type,
946 .release_port = s3c24xx_serial_release_port,
947 .request_port = s3c24xx_serial_request_port,
948 .config_port = s3c24xx_serial_config_port,
949 .verify_port = s3c24xx_serial_verify_port,
950 };
951
952
953 static struct uart_driver s3c24xx_uart_drv = {
954 .owner = THIS_MODULE,
955 .dev_name = "s3c2410_serial",
956 .nr = 3,
957 .cons = S3C24XX_SERIAL_CONSOLE,
958 .driver_name = S3C24XX_SERIAL_NAME,
959 .devfs_name = S3C24XX_SERIAL_DEVFS,
960 .major = S3C24XX_SERIAL_MAJOR,
961 .minor = S3C24XX_SERIAL_MINOR,
962 };
963
964 static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = {
965 [0] = {
966 .port = {
967 .lock = SPIN_LOCK_UNLOCKED,
968 .iotype = UPIO_MEM,
969 .irq = IRQ_S3CUART_RX0,
970 .uartclk = 0,
971 .fifosize = 16,
972 .ops = &s3c24xx_serial_ops,
973 .flags = UPF_BOOT_AUTOCONF,
974 .line = 0,
975 }
976 },
977 [1] = {
978 .port = {
979 .lock = SPIN_LOCK_UNLOCKED,
980 .iotype = UPIO_MEM,
981 .irq = IRQ_S3CUART_RX1,
982 .uartclk = 0,
983 .fifosize = 16,
984 .ops = &s3c24xx_serial_ops,
985 .flags = UPF_BOOT_AUTOCONF,
986 .line = 1,
987 }
988 },
989 #if NR_PORTS > 2
990
991 [2] = {
992 .port = {
993 .lock = SPIN_LOCK_UNLOCKED,
994 .iotype = UPIO_MEM,
995 .irq = IRQ_S3CUART_RX2,
996 .uartclk = 0,
997 .fifosize = 16,
998 .ops = &s3c24xx_serial_ops,
999 .flags = UPF_BOOT_AUTOCONF,
1000 .line = 2,
1001 }
1002 }
1003 #endif
1004 };
1005
1006 /* s3c24xx_serial_resetport
1007 *
1008 * wrapper to call the specific reset for this port (reset the fifos
1009 * and the settings)
1010 */
1011
1012 static inline int s3c24xx_serial_resetport(struct uart_port * port,
1013 struct s3c2410_uartcfg *cfg)
1014 {
1015 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1016
1017 return (info->reset_port)(port, cfg);
1018 }
1019
1020 /* s3c24xx_serial_init_port
1021 *
1022 * initialise a single serial port from the platform device given
1023 */
1024
1025 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1026 struct s3c24xx_uart_info *info,
1027 struct platform_device *platdev)
1028 {
1029 struct uart_port *port = &ourport->port;
1030 struct s3c2410_uartcfg *cfg;
1031 struct resource *res;
1032
1033 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1034
1035 if (platdev == NULL)
1036 return -ENODEV;
1037
1038 cfg = s3c24xx_dev_to_cfg(&platdev->dev);
1039
1040 if (port->mapbase != 0)
1041 return 0;
1042
1043 if (cfg->hwport > 3)
1044 return -EINVAL;
1045
1046 /* setup info for port */
1047 port->dev = &platdev->dev;
1048 ourport->info = info;
1049
1050 /* copy the info in from provided structure */
1051 ourport->port.fifosize = info->fifosize;
1052
1053 dbg("s3c24xx_serial_init_port: %p (hw %d)...\n", port, cfg->hwport);
1054
1055 port->uartclk = 1;
1056
1057 if (cfg->uart_flags & UPF_CONS_FLOW) {
1058 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1059 port->flags |= UPF_CONS_FLOW;
1060 }
1061
1062 /* sort our the physical and virtual addresses for each UART */
1063
1064 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1065 if (res == NULL) {
1066 printk(KERN_ERR "failed to find memory resource for uart\n");
1067 return -EINVAL;
1068 }
1069
1070 dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1071
1072 port->mapbase = res->start;
1073 port->membase = S3C24XX_VA_UART + (res->start - S3C2410_PA_UART);
1074 port->irq = platform_get_irq(platdev, 0);
1075
1076 ourport->clk = clk_get(&platdev->dev, "uart");
1077
1078 dbg("port: map=%08x, mem=%08x, irq=%d, clock=%ld\n",
1079 port->mapbase, port->membase, port->irq, port->uartclk);
1080
1081 /* reset the fifos (and setup the uart) */
1082 s3c24xx_serial_resetport(port, cfg);
1083 return 0;
1084 }
1085
1086 /* Device driver serial port probe */
1087
1088 static int probe_index = 0;
1089
1090 static int s3c24xx_serial_probe(struct platform_device *dev,
1091 struct s3c24xx_uart_info *info)
1092 {
1093 struct s3c24xx_uart_port *ourport;
1094 int ret;
1095
1096 dbg("s3c24xx_serial_probe(%p, %p) %d\n", dev, info, probe_index);
1097
1098 ourport = &s3c24xx_serial_ports[probe_index];
1099 probe_index++;
1100
1101 dbg("%s: initialising port %p...\n", __FUNCTION__, ourport);
1102
1103 ret = s3c24xx_serial_init_port(ourport, info, dev);
1104 if (ret < 0)
1105 goto probe_err;
1106
1107 dbg("%s: adding port\n", __FUNCTION__);
1108 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1109 platform_set_drvdata(dev, &ourport->port);
1110
1111 return 0;
1112
1113 probe_err:
1114 return ret;
1115 }
1116
1117 static int s3c24xx_serial_remove(struct platform_device *dev)
1118 {
1119 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1120
1121 if (port)
1122 uart_remove_one_port(&s3c24xx_uart_drv, port);
1123
1124 return 0;
1125 }
1126
1127 /* UART power management code */
1128
1129 #ifdef CONFIG_PM
1130
1131 static int s3c24xx_serial_suspend(struct platform_device *dev, pm_message_t state)
1132 {
1133 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1134
1135 if (port)
1136 uart_suspend_port(&s3c24xx_uart_drv, port);
1137
1138 return 0;
1139 }
1140
1141 static int s3c24xx_serial_resume(struct platform_device *dev)
1142 {
1143 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1144 struct s3c24xx_uart_port *ourport = to_ourport(port);
1145
1146 if (port) {
1147 clk_enable(ourport->clk);
1148 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1149 clk_disable(ourport->clk);
1150
1151 uart_resume_port(&s3c24xx_uart_drv, port);
1152 }
1153
1154 return 0;
1155 }
1156
1157 #else
1158 #define s3c24xx_serial_suspend NULL
1159 #define s3c24xx_serial_resume NULL
1160 #endif
1161
1162 static int s3c24xx_serial_init(struct platform_driver *drv,
1163 struct s3c24xx_uart_info *info)
1164 {
1165 dbg("s3c24xx_serial_init(%p,%p)\n", drv, info);
1166 return platform_driver_register(drv);
1167 }
1168
1169
1170 /* now comes the code to initialise either the s3c2410 or s3c2440 serial
1171 * port information
1172 */
1173
1174 /* cpu specific variations on the serial port support */
1175
1176 #ifdef CONFIG_CPU_S3C2400
1177
1178 static int s3c2400_serial_getsource(struct uart_port *port,
1179 struct s3c24xx_uart_clksrc *clk)
1180 {
1181 clk->divisor = 1;
1182 clk->name = "pclk";
1183
1184 return 0;
1185 }
1186
1187 static int s3c2400_serial_setsource(struct uart_port *port,
1188 struct s3c24xx_uart_clksrc *clk)
1189 {
1190 return 0;
1191 }
1192
1193 static int s3c2400_serial_resetport(struct uart_port *port,
1194 struct s3c2410_uartcfg *cfg)
1195 {
1196 dbg("s3c2400_serial_resetport: port=%p (%08lx), cfg=%p\n",
1197 port, port->mapbase, cfg);
1198
1199 wr_regl(port, S3C2410_UCON, cfg->ucon);
1200 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1201
1202 /* reset both fifos */
1203
1204 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1205 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1206
1207 return 0;
1208 }
1209
1210 static struct s3c24xx_uart_info s3c2400_uart_inf = {
1211 .name = "Samsung S3C2400 UART",
1212 .type = PORT_S3C2400,
1213 .fifosize = 16,
1214 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1215 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1216 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1217 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1218 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1219 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1220 .get_clksrc = s3c2400_serial_getsource,
1221 .set_clksrc = s3c2400_serial_setsource,
1222 .reset_port = s3c2400_serial_resetport,
1223 };
1224
1225 static int s3c2400_serial_probe(struct platform_device *dev)
1226 {
1227 return s3c24xx_serial_probe(dev, &s3c2400_uart_inf);
1228 }
1229
1230 static struct platform_driver s3c2400_serial_drv = {
1231 .probe = s3c2400_serial_probe,
1232 .remove = s3c24xx_serial_remove,
1233 .suspend = s3c24xx_serial_suspend,
1234 .resume = s3c24xx_serial_resume,
1235 .driver = {
1236 .name = "s3c2400-uart",
1237 .owner = THIS_MODULE,
1238 },
1239 };
1240
1241 static inline int s3c2400_serial_init(void)
1242 {
1243 return s3c24xx_serial_init(&s3c2400_serial_drv, &s3c2400_uart_inf);
1244 }
1245
1246 static inline void s3c2400_serial_exit(void)
1247 {
1248 platform_driver_unregister(&s3c2400_serial_drv);
1249 }
1250
1251 #define s3c2400_uart_inf_at &s3c2400_uart_inf
1252 #else
1253
1254 static inline int s3c2400_serial_init(void)
1255 {
1256 return 0;
1257 }
1258
1259 static inline void s3c2400_serial_exit(void)
1260 {
1261 }
1262
1263 #define s3c2400_uart_inf_at NULL
1264
1265 #endif /* CONFIG_CPU_S3C2400 */
1266
1267 /* S3C2410 support */
1268
1269 #ifdef CONFIG_CPU_S3C2410
1270
1271 static int s3c2410_serial_setsource(struct uart_port *port,
1272 struct s3c24xx_uart_clksrc *clk)
1273 {
1274 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1275
1276 if (strcmp(clk->name, "uclk") == 0)
1277 ucon |= S3C2410_UCON_UCLK;
1278 else
1279 ucon &= ~S3C2410_UCON_UCLK;
1280
1281 wr_regl(port, S3C2410_UCON, ucon);
1282 return 0;
1283 }
1284
1285 static int s3c2410_serial_getsource(struct uart_port *port,
1286 struct s3c24xx_uart_clksrc *clk)
1287 {
1288 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1289
1290 clk->divisor = 1;
1291 clk->name = (ucon & S3C2410_UCON_UCLK) ? "uclk" : "pclk";
1292
1293 return 0;
1294 }
1295
1296 static int s3c2410_serial_resetport(struct uart_port *port,
1297 struct s3c2410_uartcfg *cfg)
1298 {
1299 dbg("s3c2410_serial_resetport: port=%p (%08lx), cfg=%p\n",
1300 port, port->mapbase, cfg);
1301
1302 wr_regl(port, S3C2410_UCON, cfg->ucon);
1303 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1304
1305 /* reset both fifos */
1306
1307 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1308 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1309
1310 return 0;
1311 }
1312
1313 static struct s3c24xx_uart_info s3c2410_uart_inf = {
1314 .name = "Samsung S3C2410 UART",
1315 .type = PORT_S3C2410,
1316 .fifosize = 16,
1317 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1318 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1319 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1320 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1321 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1322 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1323 .get_clksrc = s3c2410_serial_getsource,
1324 .set_clksrc = s3c2410_serial_setsource,
1325 .reset_port = s3c2410_serial_resetport,
1326 };
1327
1328 /* device management */
1329
1330 static int s3c2410_serial_probe(struct platform_device *dev)
1331 {
1332 return s3c24xx_serial_probe(dev, &s3c2410_uart_inf);
1333 }
1334
1335 static struct platform_driver s3c2410_serial_drv = {
1336 .probe = s3c2410_serial_probe,
1337 .remove = s3c24xx_serial_remove,
1338 .suspend = s3c24xx_serial_suspend,
1339 .resume = s3c24xx_serial_resume,
1340 .driver = {
1341 .name = "s3c2410-uart",
1342 .owner = THIS_MODULE,
1343 },
1344 };
1345
1346 static inline int s3c2410_serial_init(void)
1347 {
1348 return s3c24xx_serial_init(&s3c2410_serial_drv, &s3c2410_uart_inf);
1349 }
1350
1351 static inline void s3c2410_serial_exit(void)
1352 {
1353 platform_driver_unregister(&s3c2410_serial_drv);
1354 }
1355
1356 #define s3c2410_uart_inf_at &s3c2410_uart_inf
1357 #else
1358
1359 static inline int s3c2410_serial_init(void)
1360 {
1361 return 0;
1362 }
1363
1364 static inline void s3c2410_serial_exit(void)
1365 {
1366 }
1367
1368 #define s3c2410_uart_inf_at NULL
1369
1370 #endif /* CONFIG_CPU_S3C2410 */
1371
1372 #ifdef CONFIG_CPU_S3C2440
1373
1374 static int s3c2440_serial_setsource(struct uart_port *port,
1375 struct s3c24xx_uart_clksrc *clk)
1376 {
1377 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1378
1379 // todo - proper fclk<>nonfclk switch //
1380
1381 ucon &= ~S3C2440_UCON_CLKMASK;
1382
1383 if (strcmp(clk->name, "uclk") == 0)
1384 ucon |= S3C2440_UCON_UCLK;
1385 else if (strcmp(clk->name, "pclk") == 0)
1386 ucon |= S3C2440_UCON_PCLK;
1387 else if (strcmp(clk->name, "fclk") == 0)
1388 ucon |= S3C2440_UCON_FCLK;
1389 else {
1390 printk(KERN_ERR "unknown clock source %s\n", clk->name);
1391 return -EINVAL;
1392 }
1393
1394 wr_regl(port, S3C2410_UCON, ucon);
1395 return 0;
1396 }
1397
1398
1399 static int s3c2440_serial_getsource(struct uart_port *port,
1400 struct s3c24xx_uart_clksrc *clk)
1401 {
1402 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1403 unsigned long ucon0, ucon1, ucon2;
1404
1405 switch (ucon & S3C2440_UCON_CLKMASK) {
1406 case S3C2440_UCON_UCLK:
1407 clk->divisor = 1;
1408 clk->name = "uclk";
1409 break;
1410
1411 case S3C2440_UCON_PCLK:
1412 case S3C2440_UCON_PCLK2:
1413 clk->divisor = 1;
1414 clk->name = "pclk";
1415 break;
1416
1417 case S3C2440_UCON_FCLK:
1418 /* the fun of calculating the uart divisors on
1419 * the s3c2440 */
1420
1421 ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
1422 ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
1423 ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
1424
1425 printk("ucons: %08lx, %08lx, %08lx\n", ucon0, ucon1, ucon2);
1426
1427 ucon0 &= S3C2440_UCON0_DIVMASK;
1428 ucon1 &= S3C2440_UCON1_DIVMASK;
1429 ucon2 &= S3C2440_UCON2_DIVMASK;
1430
1431 if (ucon0 != 0) {
1432 clk->divisor = ucon0 >> S3C2440_UCON_DIVSHIFT;
1433 clk->divisor += 6;
1434 } else if (ucon1 != 0) {
1435 clk->divisor = ucon1 >> S3C2440_UCON_DIVSHIFT;
1436 clk->divisor += 21;
1437 } else if (ucon2 != 0) {
1438 clk->divisor = ucon2 >> S3C2440_UCON_DIVSHIFT;
1439 clk->divisor += 36;
1440 } else {
1441 /* manual calims 44, seems to be 9 */
1442 clk->divisor = 9;
1443 }
1444
1445 clk->name = "fclk";
1446 break;
1447 }
1448
1449 return 0;
1450 }
1451
1452 static int s3c2440_serial_resetport(struct uart_port *port,
1453 struct s3c2410_uartcfg *cfg)
1454 {
1455 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1456
1457 dbg("s3c2440_serial_resetport: port=%p (%08lx), cfg=%p\n",
1458 port, port->mapbase, cfg);
1459
1460 /* ensure we don't change the clock settings... */
1461
1462 ucon &= (S3C2440_UCON0_DIVMASK | (3<<10));
1463
1464 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1465 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1466
1467 /* reset both fifos */
1468
1469 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1470 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1471
1472 return 0;
1473 }
1474
1475 static struct s3c24xx_uart_info s3c2440_uart_inf = {
1476 .name = "Samsung S3C2440 UART",
1477 .type = PORT_S3C2440,
1478 .fifosize = 64,
1479 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1480 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1481 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1482 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1483 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1484 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1485 .get_clksrc = s3c2440_serial_getsource,
1486 .set_clksrc = s3c2440_serial_setsource,
1487 .reset_port = s3c2440_serial_resetport,
1488 };
1489
1490 /* device management */
1491
1492 static int s3c2440_serial_probe(struct platform_device *dev)
1493 {
1494 dbg("s3c2440_serial_probe: dev=%p\n", dev);
1495 return s3c24xx_serial_probe(dev, &s3c2440_uart_inf);
1496 }
1497
1498 static struct platform_driver s3c2440_serial_drv = {
1499 .probe = s3c2440_serial_probe,
1500 .remove = s3c24xx_serial_remove,
1501 .suspend = s3c24xx_serial_suspend,
1502 .resume = s3c24xx_serial_resume,
1503 .driver = {
1504 .name = "s3c2440-uart",
1505 .owner = THIS_MODULE,
1506 },
1507 };
1508
1509
1510 static inline int s3c2440_serial_init(void)
1511 {
1512 return s3c24xx_serial_init(&s3c2440_serial_drv, &s3c2440_uart_inf);
1513 }
1514
1515 static inline void s3c2440_serial_exit(void)
1516 {
1517 platform_driver_unregister(&s3c2440_serial_drv);
1518 }
1519
1520 #define s3c2440_uart_inf_at &s3c2440_uart_inf
1521 #else
1522
1523 static inline int s3c2440_serial_init(void)
1524 {
1525 return 0;
1526 }
1527
1528 static inline void s3c2440_serial_exit(void)
1529 {
1530 }
1531
1532 #define s3c2440_uart_inf_at NULL
1533 #endif /* CONFIG_CPU_S3C2440 */
1534
1535 /* module initialisation code */
1536
1537 static int __init s3c24xx_serial_modinit(void)
1538 {
1539 int ret;
1540
1541 ret = uart_register_driver(&s3c24xx_uart_drv);
1542 if (ret < 0) {
1543 printk(KERN_ERR "failed to register UART driver\n");
1544 return -1;
1545 }
1546
1547 s3c2400_serial_init();
1548 s3c2410_serial_init();
1549 s3c2440_serial_init();
1550
1551 return 0;
1552 }
1553
1554 static void __exit s3c24xx_serial_modexit(void)
1555 {
1556 s3c2400_serial_exit();
1557 s3c2410_serial_exit();
1558 s3c2440_serial_exit();
1559
1560 uart_unregister_driver(&s3c24xx_uart_drv);
1561 }
1562
1563
1564 module_init(s3c24xx_serial_modinit);
1565 module_exit(s3c24xx_serial_modexit);
1566
1567 /* Console code */
1568
1569 #ifdef CONFIG_SERIAL_S3C2410_CONSOLE
1570
1571 static struct uart_port *cons_uart;
1572
1573 static int
1574 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1575 {
1576 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1577 unsigned long ufstat, utrstat;
1578
1579 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1580 /* fifo mode - check ammount of data in fifo registers... */
1581
1582 ufstat = rd_regl(port, S3C2410_UFSTAT);
1583 return (ufstat & info->tx_fifofull) ? 0 : 1;
1584 }
1585
1586 /* in non-fifo mode, we go and use the tx buffer empty */
1587
1588 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1589 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1590 }
1591
1592 static void
1593 s3c24xx_serial_console_write(struct console *co, const char *s,
1594 unsigned int count)
1595 {
1596 int i;
1597 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1598
1599 for (i = 0; i < count; i++) {
1600 while (!s3c24xx_serial_console_txrdy(cons_uart, ufcon))
1601 barrier();
1602
1603 wr_regb(cons_uart, S3C2410_UTXH, s[i]);
1604
1605 if (s[i] == '\n') {
1606 while (!s3c24xx_serial_console_txrdy(cons_uart, ufcon))
1607 barrier();
1608
1609 wr_regb(cons_uart, S3C2410_UTXH, '\r');
1610 }
1611 }
1612 }
1613
1614 static void __init
1615 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1616 int *parity, int *bits)
1617 {
1618 struct s3c24xx_uart_clksrc clksrc;
1619 struct clk *clk;
1620 unsigned int ulcon;
1621 unsigned int ucon;
1622 unsigned int ubrdiv;
1623 unsigned long rate;
1624
1625 ulcon = rd_regl(port, S3C2410_ULCON);
1626 ucon = rd_regl(port, S3C2410_UCON);
1627 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1628
1629 dbg("s3c24xx_serial_get_options: port=%p\n"
1630 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1631 port, ulcon, ucon, ubrdiv);
1632
1633 if ((ucon & 0xf) != 0) {
1634 /* consider the serial port configured if the tx/rx mode set */
1635
1636 switch (ulcon & S3C2410_LCON_CSMASK) {
1637 case S3C2410_LCON_CS5:
1638 *bits = 5;
1639 break;
1640 case S3C2410_LCON_CS6:
1641 *bits = 6;
1642 break;
1643 case S3C2410_LCON_CS7:
1644 *bits = 7;
1645 break;
1646 default:
1647 case S3C2410_LCON_CS8:
1648 *bits = 8;
1649 break;
1650 }
1651
1652 switch (ulcon & S3C2410_LCON_PMASK) {
1653 case S3C2410_LCON_PEVEN:
1654 *parity = 'e';
1655 break;
1656
1657 case S3C2410_LCON_PODD:
1658 *parity = 'o';
1659 break;
1660
1661 case S3C2410_LCON_PNONE:
1662 default:
1663 *parity = 'n';
1664 }
1665
1666 /* now calculate the baud rate */
1667
1668 s3c24xx_serial_getsource(port, &clksrc);
1669
1670 clk = clk_get(port->dev, clksrc.name);
1671 if (!IS_ERR(clk) && clk != NULL)
1672 rate = clk_get_rate(clk) / clksrc.divisor;
1673 else
1674 rate = 1;
1675
1676
1677 *baud = rate / ( 16 * (ubrdiv + 1));
1678 dbg("calculated baud %d\n", *baud);
1679 }
1680
1681 }
1682
1683 /* s3c24xx_serial_init_ports
1684 *
1685 * initialise the serial ports from the machine provided initialisation
1686 * data.
1687 */
1688
1689 static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info)
1690 {
1691 struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports;
1692 struct platform_device **platdev_ptr;
1693 int i;
1694
1695 dbg("s3c24xx_serial_init_ports: initialising ports...\n");
1696
1697 platdev_ptr = s3c24xx_uart_devs;
1698
1699 for (i = 0; i < NR_PORTS; i++, ptr++, platdev_ptr++) {
1700 s3c24xx_serial_init_port(ptr, info, *platdev_ptr);
1701 }
1702
1703 return 0;
1704 }
1705
1706 static int __init
1707 s3c24xx_serial_console_setup(struct console *co, char *options)
1708 {
1709 struct uart_port *port;
1710 int baud = 9600;
1711 int bits = 8;
1712 int parity = 'n';
1713 int flow = 'n';
1714
1715 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1716 co, co->index, options);
1717
1718 /* is this a valid port */
1719
1720 if (co->index == -1 || co->index >= NR_PORTS)
1721 co->index = 0;
1722
1723 port = &s3c24xx_serial_ports[co->index].port;
1724
1725 /* is the port configured? */
1726
1727 if (port->mapbase == 0x0) {
1728 co->index = 0;
1729 port = &s3c24xx_serial_ports[co->index].port;
1730 }
1731
1732 cons_uart = port;
1733
1734 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1735
1736 /*
1737 * Check whether an invalid uart number has been specified, and
1738 * if so, search for the first available port that does have
1739 * console support.
1740 */
1741 if (options)
1742 uart_parse_options(options, &baud, &parity, &bits, &flow);
1743 else
1744 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1745
1746 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1747
1748 return uart_set_options(port, co, baud, parity, bits, flow);
1749 }
1750
1751 /* s3c24xx_serial_initconsole
1752 *
1753 * initialise the console from one of the uart drivers
1754 */
1755
1756 static struct console s3c24xx_serial_console =
1757 {
1758 .name = S3C24XX_SERIAL_NAME,
1759 .device = uart_console_device,
1760 .flags = CON_PRINTBUFFER,
1761 .index = -1,
1762 .write = s3c24xx_serial_console_write,
1763 .setup = s3c24xx_serial_console_setup
1764 };
1765
1766 static int s3c24xx_serial_initconsole(void)
1767 {
1768 struct s3c24xx_uart_info *info;
1769 struct platform_device *dev = s3c24xx_uart_devs[0];
1770
1771 dbg("s3c24xx_serial_initconsole\n");
1772
1773 /* select driver based on the cpu */
1774
1775 if (dev == NULL) {
1776 printk(KERN_ERR "s3c24xx: no devices for console init\n");
1777 return 0;
1778 }
1779
1780 if (strcmp(dev->name, "s3c2400-uart") == 0) {
1781 info = s3c2400_uart_inf_at;
1782 } else if (strcmp(dev->name, "s3c2410-uart") == 0) {
1783 info = s3c2410_uart_inf_at;
1784 } else if (strcmp(dev->name, "s3c2440-uart") == 0) {
1785 info = s3c2440_uart_inf_at;
1786 } else {
1787 printk(KERN_ERR "s3c24xx: no driver for %s\n", dev->name);
1788 return 0;
1789 }
1790
1791 if (info == NULL) {
1792 printk(KERN_ERR "s3c24xx: no driver for console\n");
1793 return 0;
1794 }
1795
1796 s3c24xx_serial_console.data = &s3c24xx_uart_drv;
1797 s3c24xx_serial_init_ports(info);
1798
1799 register_console(&s3c24xx_serial_console);
1800 return 0;
1801 }
1802
1803 console_initcall(s3c24xx_serial_initconsole);
1804
1805 #endif /* CONFIG_SERIAL_S3C2410_CONSOLE */
1806
1807 MODULE_LICENSE("GPL");
1808 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1809 MODULE_DESCRIPTION("Samsung S3C2410/S3C2440 Serial port driver");
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