drivers/usb/host/uhci-hcd.h

   1 #ifndef __LINUX_UHCI_HCD_H
   2 #define __LINUX_UHCI_HCD_H
   3
   4 #include <linux/list.h>
   5 #include <linux/usb.h>
   6
   7 #define usb_packetid(pipe)      (usb_pipein(pipe) ? USB_PID_IN : USB_PID_OUT)
   8 #define PIPE_DEVEP_MASK         0x0007ff00
   9
  10
  11 /*
  12  * Universal Host Controller Interface data structures and defines
  13  */
  14
  15 /* Command register */
  16 #define USBCMD          0
  17 #define   USBCMD_RS             0x0001  /* Run/Stop */
  18 #define   USBCMD_HCRESET        0x0002  /* Host reset */
  19 #define   USBCMD_GRESET         0x0004  /* Global reset */
  20 #define   USBCMD_EGSM           0x0008  /* Global Suspend Mode */
  21 #define   USBCMD_FGR            0x0010  /* Force Global Resume */
  22 #define   USBCMD_SWDBG          0x0020  /* SW Debug mode */
  23 #define   USBCMD_CF             0x0040  /* Config Flag (sw only) */
  24 #define   USBCMD_MAXP           0x0080  /* Max Packet (0 = 32, 1 = 64) */
  25
  26 /* Status register */
  27 #define USBSTS          2
  28 #define   USBSTS_USBINT         0x0001  /* Interrupt due to IOC */
  29 #define   USBSTS_ERROR          0x0002  /* Interrupt due to error */
  30 #define   USBSTS_RD             0x0004  /* Resume Detect */
  31 #define   USBSTS_HSE            0x0008  /* Host System Error - basically PCI problems */
  32 #define   USBSTS_HCPE           0x0010  /* Host Controller Process Error - the scripts were buggy */
  33 #define   USBSTS_HCH            0x0020  /* HC Halted */
  34
  35 /* Interrupt enable register */
  36 #define USBINTR         4
  37 #define   USBINTR_TIMEOUT       0x0001  /* Timeout/CRC error enable */
  38 #define   USBINTR_RESUME        0x0002  /* Resume interrupt enable */
  39 #define   USBINTR_IOC           0x0004  /* Interrupt On Complete enable */
  40 #define   USBINTR_SP            0x0008  /* Short packet interrupt enable */
  41
  42 #define USBFRNUM        6
  43 #define USBFLBASEADD    8
  44 #define USBSOF          12
  45 #define   USBSOF_DEFAULT        64      /* Frame length is exactly 1 ms */
  46
  47 /* USB port status and control registers */
  48 #define USBPORTSC1      16
  49 #define USBPORTSC2      18
  50 #define   USBPORTSC_CCS         0x0001  /* Current Connect Status ("device present") */
  51 #define   USBPORTSC_CSC         0x0002  /* Connect Status Change */
  52 #define   USBPORTSC_PE          0x0004  /* Port Enable */
  53 #define   USBPORTSC_PEC         0x0008  /* Port Enable Change */
  54 #define   USBPORTSC_DPLUS       0x0010  /* D+ high (line status) */
  55 #define   USBPORTSC_DMINUS      0x0020  /* D- high (line status) */
  56 #define   USBPORTSC_RD          0x0040  /* Resume Detect */
  57 #define   USBPORTSC_RES1        0x0080  /* reserved, always 1 */
  58 #define   USBPORTSC_LSDA        0x0100  /* Low Speed Device Attached */
  59 #define   USBPORTSC_PR          0x0200  /* Port Reset */
  60 /* OC and OCC from Intel 430TX and later (not UHCI 1.1d spec) */
  61 #define   USBPORTSC_OC          0x0400  /* Over Current condition */
  62 #define   USBPORTSC_OCC         0x0800  /* Over Current Change R/WC */
  63 #define   USBPORTSC_SUSP        0x1000  /* Suspend */
  64 #define   USBPORTSC_RES2        0x2000  /* reserved, write zeroes */
  65 #define   USBPORTSC_RES3        0x4000  /* reserved, write zeroes */
  66 #define   USBPORTSC_RES4        0x8000  /* reserved, write zeroes */
  67
  68 /* Legacy support register */
  69 #define USBLEGSUP               0xc0
  70 #define   USBLEGSUP_DEFAULT     0x2000  /* only PIRQ enable set */
  71 #define   USBLEGSUP_RWC         0x8f00  /* the R/WC bits */
  72 #define   USBLEGSUP_RO          0x5040  /* R/O and reserved bits */
  73
  74 #define UHCI_PTR_BITS           cpu_to_le32(0x000F)
  75 #define UHCI_PTR_TERM           cpu_to_le32(0x0001)
  76 #define UHCI_PTR_QH             cpu_to_le32(0x0002)
  77 #define UHCI_PTR_DEPTH          cpu_to_le32(0x0004)
  78 #define UHCI_PTR_BREADTH        cpu_to_le32(0x0000)
  79
  80 #define UHCI_NUMFRAMES          1024    /* in the frame list [array] */
  81 #define UHCI_MAX_SOF_NUMBER     2047    /* in an SOF packet */
  82 #define CAN_SCHEDULE_FRAMES     1000    /* how far future frames can be scheduled */
  83
  84
  85 /*
  86  *      Queue Headers
  87  */
  88
  89 /*
  90  * One role of a QH is to hold a queue of TDs for some endpoint.  Each QH is
  91  * used with one URB, and qh->element (updated by the HC) is either:
  92  *   - the next unprocessed TD for the URB, or
  93  *   - UHCI_PTR_TERM (when there's no more traffic for this endpoint), or
  94  *   - the QH for the next URB queued to the same endpoint.
  95  *
  96  * The other role of a QH is to serve as a "skeleton" framelist entry, so we
  97  * can easily splice a QH for some endpoint into the schedule at the right
  98  * place.  Then qh->element is UHCI_PTR_TERM.
  99  *
 100  * In the frame list, qh->link maintains a list of QHs seen by the HC:
 101  *     skel1 --> ep1-qh --> ep2-qh --> ... --> skel2 --> ...
 102  */
 103 struct uhci_qh {
 104         /* Hardware fields */
 105         __le32 link;                    /* Next queue */
 106         __le32 element;                 /* Queue element pointer */
 107
 108         /* Software fields */
 109         dma_addr_t dma_handle;
 110
 111         struct urb_priv *urbp;
 112
 113         struct list_head list;
 114         struct list_head remove_list;
 115 } __attribute__((aligned(16)));
 116
 117 /*
 118  * We need a special accessor for the element pointer because it is
 119  * subject to asynchronous updates by the controller.
 120  */
 121 static __le32 inline qh_element(struct uhci_qh *qh) {
 122         __le32 element = qh->element;
 123
 124         barrier();
 125         return element;
 126 }
 127
 128
 129 /*
 130  *      Transfer Descriptors
 131  */
 132
 133 /*
 134  * for TD <status>:
 135  */
 136 #define TD_CTRL_SPD             (1 << 29)       /* Short Packet Detect */
 137 #define TD_CTRL_C_ERR_MASK      (3 << 27)       /* Error Counter bits */
 138 #define TD_CTRL_C_ERR_SHIFT     27
 139 #define TD_CTRL_LS              (1 << 26)       /* Low Speed Device */
 140 #define TD_CTRL_IOS             (1 << 25)       /* Isochronous Select */
 141 #define TD_CTRL_IOC             (1 << 24)       /* Interrupt on Complete */
 142 #define TD_CTRL_ACTIVE          (1 << 23)       /* TD Active */
 143 #define TD_CTRL_STALLED         (1 << 22)       /* TD Stalled */
 144 #define TD_CTRL_DBUFERR         (1 << 21)       /* Data Buffer Error */
 145 #define TD_CTRL_BABBLE          (1 << 20)       /* Babble Detected */
 146 #define TD_CTRL_NAK             (1 << 19)       /* NAK Received */
 147 #define TD_CTRL_CRCTIMEO        (1 << 18)       /* CRC/Time Out Error */
 148 #define TD_CTRL_BITSTUFF        (1 << 17)       /* Bit Stuff Error */
 149 #define TD_CTRL_ACTLEN_MASK     0x7FF   /* actual length, encoded as n - 1 */
 150
 151 #define TD_CTRL_ANY_ERROR       (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
 152                                  TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF)
 153
 154 #define uhci_maxerr(err)                ((err) << TD_CTRL_C_ERR_SHIFT)
 155 #define uhci_status_bits(ctrl_sts)      ((ctrl_sts) & 0xF60000)
 156 #define uhci_actual_length(ctrl_sts)    (((ctrl_sts) + 1) & TD_CTRL_ACTLEN_MASK) /* 1-based */
 157
 158 /*
 159  * for TD <info>: (a.k.a. Token)
 160  */
 161 #define td_token(td)            le32_to_cpu((td)->token)
 162 #define TD_TOKEN_DEVADDR_SHIFT  8
 163 #define TD_TOKEN_TOGGLE_SHIFT   19
 164 #define TD_TOKEN_TOGGLE         (1 << 19)
 165 #define TD_TOKEN_EXPLEN_SHIFT   21
 166 #define TD_TOKEN_EXPLEN_MASK    0x7FF           /* expected length, encoded as n - 1 */
 167 #define TD_TOKEN_PID_MASK       0xFF
 168
 169 #define uhci_explen(len)        ((((len) - 1) & TD_TOKEN_EXPLEN_MASK) << \
 170                                         TD_TOKEN_EXPLEN_SHIFT)
 171
 172 #define uhci_expected_length(token) ((((token) >> TD_TOKEN_EXPLEN_SHIFT) + \
 173                                         1) & TD_TOKEN_EXPLEN_MASK)
 174 #define uhci_toggle(token)      (((token) >> TD_TOKEN_TOGGLE_SHIFT) & 1)
 175 #define uhci_endpoint(token)    (((token) >> 15) & 0xf)
 176 #define uhci_devaddr(token)     (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7f)
 177 #define uhci_devep(token)       (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7ff)
 178 #define uhci_packetid(token)    ((token) & TD_TOKEN_PID_MASK)
 179 #define uhci_packetout(token)   (uhci_packetid(token) != USB_PID_IN)
 180 #define uhci_packetin(token)    (uhci_packetid(token) == USB_PID_IN)
 181
 182 /*
 183  * The documentation says "4 words for hardware, 4 words for software".
 184  *
 185  * That's silly, the hardware doesn't care. The hardware only cares that
 186  * the hardware words are 16-byte aligned, and we can have any amount of
 187  * sw space after the TD entry.
 188  *
 189  * td->link points to either another TD (not necessarily for the same urb or
 190  * even the same endpoint), or nothing (PTR_TERM), or a QH (for queued urbs).
 191  */
 192 struct uhci_td {
 193         /* Hardware fields */
 194         __le32 link;
 195         __le32 status;
 196         __le32 token;
 197         __le32 buffer;
 198
 199         /* Software fields */
 200         dma_addr_t dma_handle;
 201
 202         struct list_head list;
 203         struct list_head remove_list;
 204
 205         int frame;                      /* for iso: what frame? */
 206         struct list_head fl_list;
 207 } __attribute__((aligned(16)));
 208
 209 /*
 210  * We need a special accessor for the control/status word because it is
 211  * subject to asynchronous updates by the controller.
 212  */
 213 static u32 inline td_status(struct uhci_td *td) {
 214         __le32 status = td->status;
 215
 216         barrier();
 217         return le32_to_cpu(status);
 218 }
 219
 220
 221 /*
 222  *      Skeleton Queue Headers
 223  */
 224
 225 /*
 226  * The UHCI driver places Interrupt, Control and Bulk into QHs both
 227  * to group together TDs for one transfer, and also to facilitate queuing
 228  * of URBs. To make it easy to insert entries into the schedule, we have
 229  * a skeleton of QHs for each predefined Interrupt latency, low-speed
 230  * control, full-speed control and terminating QH (see explanation for
 231  * the terminating QH below).
 232  *
 233  * When we want to add a new QH, we add it to the end of the list for the
 234  * skeleton QH.
 235  *
 236  * For instance, the queue can look like this:
 237  *
 238  * skel int128 QH
 239  * dev 1 interrupt QH
 240  * dev 5 interrupt QH
 241  * skel int64 QH
 242  * skel int32 QH
 243  * ...
 244  * skel int1 QH
 245  * skel low-speed control QH
 246  * dev 5 control QH
 247  * skel full-speed control QH
 248  * skel bulk QH
 249  * dev 1 bulk QH
 250  * dev 2 bulk QH
 251  * skel terminating QH
 252  *
 253  * The terminating QH is used for 2 reasons:
 254  * - To place a terminating TD which is used to workaround a PIIX bug
 255  *   (see Intel errata for explanation), and
 256  * - To loop back to the full-speed control queue for full-speed bandwidth
 257  *   reclamation.
 258  *
 259  * Isochronous transfers are stored before the start of the skeleton
 260  * schedule and don't use QHs. While the UHCI spec doesn't forbid the
 261  * use of QHs for Isochronous, it doesn't use them either. And the spec
 262  * says that queues never advance on an error completion status, which
 263  * makes them totally unsuitable for Isochronous transfers.
 264  */
 265
 266 #define UHCI_NUM_SKELQH         12
 267 #define skel_int128_qh          skelqh[0]
 268 #define skel_int64_qh           skelqh[1]
 269 #define skel_int32_qh           skelqh[2]
 270 #define skel_int16_qh           skelqh[3]
 271 #define skel_int8_qh            skelqh[4]
 272 #define skel_int4_qh            skelqh[5]
 273 #define skel_int2_qh            skelqh[6]
 274 #define skel_int1_qh            skelqh[7]
 275 #define skel_ls_control_qh      skelqh[8]
 276 #define skel_fs_control_qh      skelqh[9]
 277 #define skel_bulk_qh            skelqh[10]
 278 #define skel_term_qh            skelqh[11]
 279
 280 /*
 281  * Search tree for determining where <interval> fits in the skelqh[]
 282  * skeleton.
 283  *
 284  * An interrupt request should be placed into the slowest skelqh[]
 285  * which meets the interval/period/frequency requirement.
 286  * An interrupt request is allowed to be faster than <interval> but not slower.
 287  *
 288  * For a given <interval>, this function returns the appropriate/matching
 289  * skelqh[] index value.
 290  */
 291 static inline int __interval_to_skel(int interval)
 292 {
 293         if (interval < 16) {
 294                 if (interval < 4) {
 295                         if (interval < 2)
 296                                 return 7;       /* int1 for 0-1 ms */
 297                         return 6;               /* int2 for 2-3 ms */
 298                 }
 299                 if (interval < 8)
 300                         return 5;               /* int4 for 4-7 ms */
 301                 return 4;                       /* int8 for 8-15 ms */
 302         }
 303         if (interval < 64) {
 304                 if (interval < 32)
 305                         return 3;               /* int16 for 16-31 ms */
 306                 return 2;                       /* int32 for 32-63 ms */
 307         }
 308         if (interval < 128)
 309                 return 1;                       /* int64 for 64-127 ms */
 310         return 0;                               /* int128 for 128-255 ms (Max.) */
 311 }
 312
 313
 314 /*
 315  *      The UHCI controller and root hub
 316  */
 317
 318 /*
 319  * States for the root hub:
 320  *
 321  * To prevent "bouncing" in the presence of electrical noise,
 322  * when there are no devices attached we delay for 1 second in the
 323  * RUNNING_NODEVS state before switching to the AUTO_STOPPED state.
 324  *
 325  * (Note that the AUTO_STOPPED state won't be necessary once the hub
 326  * driver learns to autosuspend.)
 327  */
 328 enum uhci_rh_state {
 329         /* In the following states the HC must be halted.
 330          * These two must come first. */
 331         UHCI_RH_RESET,
 332         UHCI_RH_SUSPENDED,
 333
 334         UHCI_RH_AUTO_STOPPED,
 335         UHCI_RH_RESUMING,
 336
 337         /* In this state the HC changes from running to halted,
 338          * so it can legally appear either way. */
 339         UHCI_RH_SUSPENDING,
 340
 341         /* In the following states it's an error if the HC is halted.
 342          * These two must come last. */
 343         UHCI_RH_RUNNING,                /* The normal state */
 344         UHCI_RH_RUNNING_NODEVS,         /* Running with no devices attached */
 345 };
 346
 347 /*
 348  * The full UHCI controller information:
 349  */
 350 struct uhci_hcd {
 351
 352         /* debugfs */
 353         struct dentry *dentry;
 354
 355         /* Grabbed from PCI */
 356         unsigned long io_addr;
 357
 358         struct dma_pool *qh_pool;
 359         struct dma_pool *td_pool;
 360
 361         struct uhci_td *term_td;        /* Terminating TD, see UHCI bug */
 362         struct uhci_qh *skelqh[UHCI_NUM_SKELQH];        /* Skeleton QHs */
 363
 364         spinlock_t lock;
 365
 366         dma_addr_t frame_dma_handle;            /* Hardware frame list */
 367         __le32 *frame;
 368         void **frame_cpu;                       /* CPU's frame list */
 369
 370         int fsbr;                               /* Full-speed bandwidth reclamation */
 371         unsigned long fsbrtimeout;              /* FSBR delay */
 372
 373         enum uhci_rh_state rh_state;
 374         unsigned long auto_stop_time;           /* When to AUTO_STOP */
 375
 376         unsigned int frame_number;              /* As of last check */
 377         unsigned int is_stopped;
 378 #define UHCI_IS_STOPPED         9999            /* Larger than a frame # */
 379
 380         unsigned int scan_in_progress:1;        /* Schedule scan is running */
 381         unsigned int need_rescan:1;             /* Redo the schedule scan */
 382         unsigned int hc_inaccessible:1;         /* HC is suspended or dead */
 383         unsigned int working_RD:1;              /* Suspended root hub doesn't
 384                                                    need to be polled */
 385
 386         /* Support for port suspend/resume/reset */
 387         unsigned long port_c_suspend;           /* Bit-arrays of ports */
 388         unsigned long suspended_ports;
 389         unsigned long resuming_ports;
 390         unsigned long ports_timeout;            /* Time to stop signalling */
 391
 392         /* Main list of URBs currently controlled by this HC */
 393         struct list_head urb_list;
 394
 395         /* List of QHs that are done, but waiting to be unlinked (race) */
 396         struct list_head qh_remove_list;
 397         unsigned int qh_remove_age;             /* Age in frames */
 398
 399         /* List of TDs that are done, but waiting to be freed (race) */
 400         struct list_head td_remove_list;
 401         unsigned int td_remove_age;             /* Age in frames */
 402
 403         /* List of asynchronously unlinked URBs */
 404         struct list_head urb_remove_list;
 405         unsigned int urb_remove_age;            /* Age in frames */
 406
 407         /* List of URBs awaiting completion callback */
 408         struct list_head complete_list;
 409
 410         int rh_numports;                        /* Number of root-hub ports */
 411
 412         wait_queue_head_t waitqh;               /* endpoint_disable waiters */
 413 };
 414
 415 /* Convert between a usb_hcd pointer and the corresponding uhci_hcd */
 416 static inline struct uhci_hcd *hcd_to_uhci(struct usb_hcd *hcd)
 417 {
 418         return (struct uhci_hcd *) (hcd->hcd_priv);
 419 }
 420 static inline struct usb_hcd *uhci_to_hcd(struct uhci_hcd *uhci)
 421 {
 422         return container_of((void *) uhci, struct usb_hcd, hcd_priv);
 423 }
 424
 425 #define uhci_dev(u)     (uhci_to_hcd(u)->self.controller)
 426
 427
 428 /*
 429  *      Private per-URB data
 430  */
 431 struct urb_priv {
 432         struct list_head urb_list;
 433
 434         struct urb *urb;
 435
 436         struct uhci_qh *qh;             /* QH for this URB */
 437         struct list_head td_list;
 438
 439         unsigned fsbr : 1;              /* URB turned on FSBR */
 440         unsigned fsbr_timeout : 1;      /* URB timed out on FSBR */
 441         unsigned queued : 1;            /* QH was queued (not linked in) */
 442         unsigned short_control_packet : 1;      /* If we get a short packet during */
 443                                                 /*  a control transfer, retrigger */
 444                                                 /*  the status phase */
 445
 446         unsigned long fsbrtime;         /* In jiffies */
 447
 448         struct list_head queue_list;
 449 };
 450
 451
 452 /*
 453  * Locking in uhci.c
 454  *
 455  * Almost everything relating to the hardware schedule and processing
 456  * of URBs is protected by uhci->lock.  urb->status is protected by
 457  * urb->lock; that's the one exception.
 458  *
 459  * To prevent deadlocks, never lock uhci->lock while holding urb->lock.
 460  * The safe order of locking is:
 461  *
 462  * #1 uhci->lock
 463  * #2 urb->lock
 464  */
 465
 466
 467 /* Some special IDs */
 468
 469 #define PCI_VENDOR_ID_GENESYS           0x17a0
 470 #define PCI_DEVICE_ID_GL880S_UHCI       0x8083
 471
 472 #endif