2 * linux/arch/arm/common/icst525.c
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Support functions for calculating clocks/divisors for the ICST525
11 * clock generators. See http://www.icst.com/ for more information
14 #include <linux/module.h>
15 #include <linux/kernel.h>
17 #include <asm/hardware/icst525.h>
20 * Divisors for each OD setting.
22 static unsigned char s2div
[8] = { 10, 2, 8, 4, 5, 7, 9, 6 };
24 unsigned long icst525_khz(const struct icst525_params
*p
, struct icst525_vco vco
)
26 return p
->ref
* 2 * (vco
.v
+ 8) / ((vco
.r
+ 2) * s2div
[vco
.s
]);
29 EXPORT_SYMBOL(icst525_khz
);
32 * Ascending divisor S values.
34 static unsigned char idx2s
[] = { 1, 3, 4, 7, 5, 2, 6, 0 };
37 icst525_khz_to_vco(const struct icst525_params
*p
, unsigned long freq
)
39 struct icst525_vco vco
= { .s
= 1, .v
= p
->vd_max
, .r
= p
->rd_max
};
41 unsigned int i
= 0, rd
, best
= (unsigned int)-1;
44 * First, find the PLL output divisor such
45 * that the PLL output is within spec.
48 f
= freq
* s2div
[idx2s
[i
]];
51 * f must be between 10MHz and
52 * 320MHz (5V) or 200MHz (3V)
54 if (f
> 10000 && f
<= p
->vco_max
)
56 } while (i
< ARRAY_SIZE(idx2s
));
58 if (i
> ARRAY_SIZE(idx2s
))
64 * Now find the closest divisor combination
65 * which gives a PLL output of 'f'.
67 for (rd
= p
->rd_min
; rd
<= p
->rd_max
; rd
++) {
68 unsigned long fref_div
, f_pll
;
72 fref_div
= (2 * p
->ref
) / rd
;
74 vd
= (f
+ fref_div
/ 2) / fref_div
;
75 if (vd
< p
->vd_min
|| vd
> p
->vd_max
)
78 f_pll
= fref_div
* vd
;
83 if ((unsigned)f_diff
< best
) {
95 EXPORT_SYMBOL(icst525_khz_to_vco
);
98 icst525_ps_to_vco(const struct icst525_params
*p
, unsigned long period
)
100 struct icst525_vco vco
= { .s
= 1, .v
= p
->vd_max
, .r
= p
->rd_max
};
102 unsigned int i
= 0, rd
, best
= (unsigned int)-1;
104 ps
= 1000000000UL / p
->vco_max
;
107 * First, find the PLL output divisor such
108 * that the PLL output is within spec.
111 f
= period
/ s2div
[idx2s
[i
]];
114 * f must be between 10MHz and
115 * 320MHz (5V) or 200MHz (3V)
117 if (f
>= ps
&& f
< 100000)
119 } while (i
< ARRAY_SIZE(idx2s
));
121 if (i
> ARRAY_SIZE(idx2s
))
126 ps
= 500000000UL / p
->ref
;
129 * Now find the closest divisor combination
130 * which gives a PLL output of 'f'.
132 for (rd
= p
->rd_min
; rd
<= p
->rd_max
; rd
++) {
133 unsigned long f_in_div
, f_pll
;
139 vd
= (f_in_div
+ f
/ 2) / f
;
140 if (vd
< p
->vd_min
|| vd
> p
->vd_max
)
143 f_pll
= (f_in_div
+ vd
/ 2) / vd
;
148 if ((unsigned)f_diff
< best
) {
160 EXPORT_SYMBOL(icst525_ps_to_vco
);