arch/arm/lib/io-readsw-armv3.S

   1 /*
   2  *  linux/arch/arm/lib/io-readsw-armv3.S
   3  *
   4  *  Copyright (C) 1995-2000 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/linkage.h>
  11 #include <asm/assembler.h>
  12 #include <asm/hardware.h>
  13
  14 .insw_bad_alignment:
  15                 adr     r0, .insw_bad_align_msg
  16                 mov     r2, lr
  17                 b       panic
  18 .insw_bad_align_msg:
  19                 .asciz  "insw: bad buffer alignment (0x%p, lr=0x%08lX)\n"
  20                 .align
  21
  22 .insw_align:    tst     r1, #1
  23                 bne     .insw_bad_alignment
  24
  25                 ldr     r3, [r0]
  26                 strb    r3, [r1], #1
  27                 mov     r3, r3, lsr #8
  28                 strb    r3, [r1], #1
  29
  30                 subs    r2, r2, #1
  31                 RETINSTR(moveq, pc, lr)
  32
  33 ENTRY(__raw_readsw)
  34                 teq     r2, #0          @ do we have to check for the zero len?
  35                 moveq   pc, lr
  36                 tst     r1, #3
  37                 bne     .insw_align
  38
  39 .insw_aligned:  mov     ip, #0xff
  40                 orr     ip, ip, ip, lsl #8
  41                 stmfd   sp!, {r4, r5, r6, lr}
  42
  43                 subs    r2, r2, #8
  44                 bmi     .no_insw_8
  45
  46 .insw_8_lp:     ldr     r3, [r0]
  47                 and     r3, r3, ip
  48                 ldr     r4, [r0]
  49                 orr     r3, r3, r4, lsl #16
  50
  51                 ldr     r4, [r0]
  52                 and     r4, r4, ip
  53                 ldr     r5, [r0]
  54                 orr     r4, r4, r5, lsl #16
  55
  56                 ldr     r5, [r0]
  57                 and     r5, r5, ip
  58                 ldr     r6, [r0]
  59                 orr     r5, r5, r6, lsl #16
  60
  61                 ldr     r6, [r0]
  62                 and     r6, r6, ip
  63                 ldr     lr, [r0]
  64                 orr     r6, r6, lr, lsl #16
  65
  66                 stmia   r1!, {r3 - r6}
  67
  68                 subs    r2, r2, #8
  69                 bpl     .insw_8_lp
  70
  71                 tst     r2, #7
  72                 LOADREGS(eqfd, sp!, {r4, r5, r6, pc})
  73
  74 .no_insw_8:     tst     r2, #4
  75                 beq     .no_insw_4
  76
  77                 ldr     r3, [r0]
  78                 and     r3, r3, ip
  79                 ldr     r4, [r0]
  80                 orr     r3, r3, r4, lsl #16
  81
  82                 ldr     r4, [r0]
  83                 and     r4, r4, ip
  84                 ldr     r5, [r0]
  85                 orr     r4, r4, r5, lsl #16
  86
  87                 stmia   r1!, {r3, r4}
  88
  89 .no_insw_4:     tst     r2, #2
  90                 beq     .no_insw_2
  91
  92                 ldr     r3, [r0]
  93                 and     r3, r3, ip
  94                 ldr     r4, [r0]
  95                 orr     r3, r3, r4, lsl #16
  96
  97                 str     r3, [r1], #4
  98
  99 .no_insw_2:     tst     r2, #1
 100                 ldrne   r3, [r0]
 101                 strneb  r3, [r1], #1
 102                 movne   r3, r3, lsr #8
 103                 strneb  r3, [r1]
 104
 105                 LOADREGS(fd, sp!, {r4, r5, r6, pc})
 106
 107