arch/arm/mach-iop3xx/iop321-pci.c

   1 /*
   2  * arch/arm/mach-iop3xx/iop321-pci.c
   3  *
   4  * PCI support for the Intel IOP321 chipset
   5  *
   6  * Author: Rory Bolt <rorybolt@pacbell.net>
   7  * Copyright (C) 2002 Rory Bolt
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  */
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/slab.h>
  17 #include <linux/mm.h>
  18 #include <linux/init.h>
  19 #include <linux/ioport.h>
  20
  21 #include <asm/io.h>
  22 #include <asm/irq.h>
  23 #include <asm/system.h>
  24 #include <asm/hardware.h>
  25 #include <asm/mach/pci.h>
  26
  27 #include <asm/arch/iop321.h>
  28
  29 // #define DEBUG
  30
  31 #ifdef DEBUG
  32 #define  DBG(x...) printk(x)
  33 #else
  34 #define  DBG(x...) do { } while (0)
  35 #endif
  36
  37 /*
  38  * This routine builds either a type0 or type1 configuration command.  If the
  39  * bus is on the 80321 then a type0 made, else a type1 is created.
  40  */
  41 static u32 iop321_cfg_address(struct pci_bus *bus, int devfn, int where)
  42 {
  43         struct pci_sys_data *sys = bus->sysdata;
  44         u32 addr;
  45
  46         if (sys->busnr == bus->number)
  47                 addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
  48         else
  49                 addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
  50
  51         addr |= PCI_FUNC(devfn) << 8 | (where & ~3);
  52
  53         return addr;
  54 }
  55
  56 /*
  57  * This routine checks the status of the last configuration cycle.  If an error
  58  * was detected it returns a 1, else it returns a 0.  The errors being checked
  59  * are parity, master abort, target abort (master and target).  These types of
  60  * errors occure during a config cycle where there is no device, like during
  61  * the discovery stage.
  62  */
  63 static int iop321_pci_status(void)
  64 {
  65         unsigned int status;
  66         int ret = 0;
  67
  68         /*
  69          * Check the status registers.
  70          */
  71         status = *IOP321_ATUSR;
  72         if (status & 0xf900)
  73         {
  74                 DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status);
  75                 *IOP321_ATUSR = status & 0xf900;
  76                 ret = 1;
  77         }
  78         status = *IOP321_ATUISR;
  79         if (status & 0x679f)
  80         {
  81                 DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status);
  82                 *IOP321_ATUISR = status & 0x679f;
  83                 ret = 1;
  84         }
  85         return ret;
  86 }
  87
  88 /*
  89  * Simply write the address register and read the configuration
  90  * data.  Note that the 4 nop's ensure that we are able to handle
  91  * a delayed abort (in theory.)
  92  */
  93 static inline u32 iop321_read(unsigned long addr)
  94 {
  95         u32 val;
  96
  97         __asm__ __volatile__(
  98                 "str    %1, [%2]\n\t"
  99                 "ldr    %0, [%3]\n\t"
 100                 "nop\n\t"
 101                 "nop\n\t"
 102                 "nop\n\t"
 103                 "nop\n\t"
 104                 : "=r" (val)
 105                 : "r" (addr), "r" (IOP321_OCCAR), "r" (IOP321_OCCDR));
 106
 107         return val;
 108 }
 109
 110 /*
 111  * The read routines must check the error status of the last configuration
 112  * cycle.  If there was an error, the routine returns all hex f's.
 113  */
 114 static int
 115 iop321_read_config(struct pci_bus *bus, unsigned int devfn, int where,
 116                 int size, u32 *value)
 117 {
 118         unsigned long addr = iop321_cfg_address(bus, devfn, where);
 119         u32 val = iop321_read(addr) >> ((where & 3) * 8);
 120
 121         if( iop321_pci_status() )
 122                 val = 0xffffffff;
 123
 124         *value = val;
 125
 126         return PCIBIOS_SUCCESSFUL;
 127 }
 128
 129 static int
 130 iop321_write_config(struct pci_bus *bus, unsigned int devfn, int where,
 131                 int size, u32 value)
 132 {
 133         unsigned long addr = iop321_cfg_address(bus, devfn, where);
 134         u32 val;
 135
 136         if (size != 4) {
 137                 val = iop321_read(addr);
 138                 if (!iop321_pci_status() == 0)
 139                         return PCIBIOS_SUCCESSFUL;
 140
 141                 where = (where & 3) * 8;
 142
 143                 if (size == 1)
 144                         val &= ~(0xff << where);
 145                 else
 146                         val &= ~(0xffff << where);
 147
 148                 *IOP321_OCCDR = val | value << where;
 149         } else {
 150                 asm volatile(
 151                         "str    %1, [%2]\n\t"
 152                         "str    %0, [%3]\n\t"
 153                         "nop\n\t"
 154                         "nop\n\t"
 155                         "nop\n\t"
 156                         "nop\n\t"
 157                         :
 158                         : "r" (value), "r" (addr),
 159                           "r" (IOP321_OCCAR), "r" (IOP321_OCCDR));
 160         }
 161
 162         return PCIBIOS_SUCCESSFUL;
 163 }
 164
 165 static struct pci_ops iop321_ops = {
 166         .read   = iop321_read_config,
 167         .write  = iop321_write_config,
 168 };
 169
 170 /*
 171  * When a PCI device does not exist during config cycles, the 80200 gets a
 172  * bus error instead of returning 0xffffffff. This handler simply returns.
 173  */
 174 int
 175 iop321_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
 176 {
 177         DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n",
 178                 addr, fsr, regs->ARM_pc, regs->ARM_lr);
 179
 180         /*
 181          * If it was an imprecise abort, then we need to correct the
 182          * return address to be _after_ the instruction.
 183          */
 184         if (fsr & (1 << 10))
 185                 regs->ARM_pc += 4;
 186
 187         return 0;
 188 }
 189
 190 /*
 191  * Scan an IOP321 PCI bus.  sys->bus defines which bus we scan.
 192  */
 193 struct pci_bus *iop321_scan_bus(int nr, struct pci_sys_data *sys)
 194 {
 195         return pci_scan_bus(sys->busnr, &iop321_ops, sys);
 196 }
 197
 198 void iop321_init(void)
 199 {
 200         DBG("PCI:  Intel 80321 PCI init code.\n");
 201         DBG("ATU: IOP321_ATUCMD=0x%04x\n", *IOP321_ATUCMD);
 202         DBG("ATU: IOP321_OMWTVR0=0x%04x, IOP321_OIOWTVR=0x%04x\n",
 203                         *IOP321_OMWTVR0,
 204                         *IOP321_OIOWTVR);
 205         DBG("ATU: IOP321_ATUCR=0x%08x\n", *IOP321_ATUCR);
 206         DBG("ATU: IOP321_IABAR0=0x%08x IOP321_IALR0=0x%08x IOP321_IATVR0=%08x\n",
 207                         *IOP321_IABAR0, *IOP321_IALR0, *IOP321_IATVR0);
 208         DBG("ATU: IOP321_OMWTVR0=0x%08x\n", *IOP321_OMWTVR0);
 209         DBG("ATU: IOP321_IABAR1=0x%08x IOP321_IALR1=0x%08x\n",
 210                         *IOP321_IABAR1, *IOP321_IALR1);
 211         DBG("ATU: IOP321_ERBAR=0x%08x IOP321_ERLR=0x%08x IOP321_ERTVR=%08x\n",
 212                         *IOP321_ERBAR, *IOP321_ERLR, *IOP321_ERTVR);
 213         DBG("ATU: IOP321_IABAR2=0x%08x IOP321_IALR2=0x%08x IOP321_IATVR2=%08x\n",
 214                         *IOP321_IABAR2, *IOP321_IALR2, *IOP321_IATVR2);
 215         DBG("ATU: IOP321_IABAR3=0x%08x IOP321_IALR3=0x%08x IOP321_IATVR3=%08x\n",
 216                         *IOP321_IABAR3, *IOP321_IALR3, *IOP321_IATVR3);
 217
 218         hook_fault_code(16+6, iop321_pci_abort, SIGBUS, "imprecise external abort");
 219 }
 220