[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / arch / arm / mach-lh7a40x / irq-kev7a400.c
blob691bb09232a56a51fdc36ea6c4ef6f3109d0df9b
1 /* arch/arm/mach-lh7a40x/irq-kev7a400.c
3 * Copyright (C) 2004 Coastal Environmental Systems
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
9 */
11 #include <linux/interrupt.h>
12 #include <linux/init.h>
14 #include <asm/irq.h>
15 #include <asm/mach/irq.h>
16 #include <asm/mach/hardware.h>
17 #include <asm/mach/irqs.h>
20 /* KEV7a400 CPLD IRQ handling */
22 static u16 CPLD_IRQ_mask; /* Mask for CPLD IRQs, 1 == unmasked */
24 static void
25 lh7a400_ack_cpld_irq (u32 irq)
27 CPLD_CL_INT = 1 << (irq - IRQ_KEV7A400_CPLD);
30 static void
31 lh7a400_mask_cpld_irq (u32 irq)
33 CPLD_IRQ_mask &= ~(1 << (irq - IRQ_KEV7A400_CPLD));
34 CPLD_WR_PB_INT_MASK = CPLD_IRQ_mask;
37 static void
38 lh7a400_unmask_cpld_irq (u32 irq)
40 CPLD_IRQ_mask |= 1 << (irq - IRQ_KEV7A400_CPLD);
41 CPLD_WR_PB_INT_MASK = CPLD_IRQ_mask;
44 static struct
45 irqchip lh7a400_cpld_chip = {
46 .ack = lh7a400_ack_cpld_irq,
47 .mask = lh7a400_mask_cpld_irq,
48 .unmask = lh7a400_unmask_cpld_irq,
51 static void
52 lh7a400_cpld_handler (unsigned int irq, struct irqdesc *desc,
53 struct pt_regs *regs)
55 u32 mask = CPLD_LATCHED_INTS;
56 irq = IRQ_KEV_7A400_CPLD;
57 for (; mask; mask >>= 1, ++irq) {
58 if (mask & 1)
59 desc[irq].handle (irq, desc, regs);
63 /* IRQ initialization */
65 void __init
66 lh7a400_init_board_irq (void)
68 int irq;
70 for (irq = IRQ_KEV7A400_CPLD;
71 irq < IRQ_KEV7A400_CPLD + NR_IRQ_KEV7A400_CPLD; ++irq) {
72 set_irq_chip (irq, &lh7a400_cpld_chip);
73 set_irq_handler (irq, do_edge_IRQ);
74 set_irq_flags (irq, IRQF_VALID);
76 set_irq_chained_handler (IRQ_CPLD, kev7a400_cpld_handler);
78 /* Clear all CPLD interrupts */
79 CPLD_CL_INT = 0xff; /* CPLD_INTR_MMC_CD | CPLD_INTR_ETH_INT; */
81 /* *** FIXME CF enabled in ide-probe.c */
83 GPIO_GPIOINTEN = 0; /* Disable all GPIO interrupts */
84 barrier();
85 GPIO_INTTYPE1
86 = (GPIO_INTR_PCC1_CD | GPIO_INTR_PCC1_CD); /* Edge trig. */
87 GPIO_INTTYPE2 = 0; /* Falling edge & low-level */
88 GPIO_GPIOFEOI = 0xff; /* Clear all GPIO interrupts */
89 GPIO_GPIOINTEN = 0xff; /* Enable all GPIO interrupts */
91 init_FIQ();