[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / arch / arm / mach-omap / clock.h
blob08c0ddde1835b7046ebe01bcaad5ffd741f25ccc
1 /*
2 * linux/arch/arm/mach-omap/clock.h
4 * Copyright (C) 2004 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __ARCH_ARM_OMAP_CLOCK_H
14 #define __ARCH_ARM_OMAP_CLOCK_H
16 struct module;
18 struct clk {
19 struct list_head node;
20 struct module *owner;
21 const char *name;
22 struct clk *parent;
23 unsigned long rate;
24 __s8 usecount;
25 __u16 flags;
26 __u32 enable_reg;
27 __u8 enable_bit;
28 __u8 rate_offset;
29 void (*recalc)(struct clk *);
30 int (*set_rate)(struct clk *, unsigned long);
31 long (*round_rate)(struct clk *, unsigned long);
32 void (*init)(struct clk *);
36 struct mpu_rate {
37 unsigned long rate;
38 unsigned long xtal;
39 unsigned long pll_rate;
40 __u16 ckctl_val;
41 __u16 dpllctl_val;
45 /* Clock flags */
46 #define RATE_CKCTL 1
47 #define RATE_FIXED 2
48 #define RATE_PROPAGATES 4
49 #define VIRTUAL_CLOCK 8
50 #define ALWAYS_ENABLED 16
51 #define ENABLE_REG_32BIT 32
52 #define CLOCK_IN_OMAP16XX 64
53 #define CLOCK_IN_OMAP1510 128
54 #define CLOCK_IN_OMAP730 256
56 /* ARM_CKCTL bit shifts */
57 #define CKCTL_PERDIV_OFFSET 0
58 #define CKCTL_LCDDIV_OFFSET 2
59 #define CKCTL_ARMDIV_OFFSET 4
60 #define CKCTL_DSPDIV_OFFSET 6
61 #define CKCTL_TCDIV_OFFSET 8
62 #define CKCTL_DSPMMUDIV_OFFSET 10
63 /*#define ARM_TIMXO 12*/
64 #define EN_DSPCK 13
65 /*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */
67 /* ARM_IDLECT1 bit shifts */
68 /*#define IDLWDT_ARM 0*/
69 /*#define IDLXORP_ARM 1*/
70 /*#define IDLPER_ARM 2*/
71 /*#define IDLLCD_ARM 3*/
72 /*#define IDLLB_ARM 4*/
73 /*#define IDLHSAB_ARM 5*/
74 /*#define IDLIF_ARM 6*/
75 /*#define IDLDPLL_ARM 7*/
76 /*#define IDLAPI_ARM 8*/
77 /*#define IDLTIM_ARM 9*/
78 /*#define SETARM_IDLE 11*/
80 /* ARM_IDLECT2 bit shifts */
81 #define EN_WDTCK 0
82 #define EN_XORPCK 1
83 #define EN_PERCK 2
84 #define EN_LCDCK 3
85 #define EN_LBCK 4 /* Not on 1610/1710 */
86 /*#define EN_HSABCK 5*/
87 #define EN_APICK 6
88 #define EN_TIMCK 7
89 #define DMACK_REQ 8
90 #define EN_GPIOCK 9 /* Not on 1610/1710 */
91 /*#define EN_LBFREECK 10*/
92 #define EN_CKOUT_ARM 11
94 /* ARM_IDLECT3 bit shifts */
95 #define EN_OCPI_CK 0
96 #define EN_TC1_CK 2
97 #define EN_TC2_CK 4
99 /* Various register defines for clock controls scattered around OMAP chip */
100 #define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */
101 #define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */
102 #define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */
103 #define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */
104 #define SWD_CLK_DIV_CTRL_SEL 0xfffe0874
105 #define COM_CLK_DIV_CTRL_SEL 0xfffe0878
108 int clk_register(struct clk *clk);
109 void clk_unregister(struct clk *clk);
110 int clk_init(void);
112 #endif