?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / arch / arm / mach-s3c2410 / mach-bast.c
blob3bb97eb6e6932788551d70e451c0e5205442f634
1 /* linux/arch/arm/mach-s3c2410/mach-bast.c
2 *
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://www.simtec.co.uk/products/EB2410ITX/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Modifications:
13 * 14-Sep-2004 BJD USB power control
14 * 20-Aug-2004 BJD Added s3c2410_board struct
15 * 18-Aug-2004 BJD Added platform devices from default set
16 * 16-May-2003 BJD Created initial version
17 * 16-Aug-2003 BJD Fixed header files and copyright, added URL
18 * 05-Sep-2003 BJD Moved to v2.6 kernel
19 * 06-Jan-2003 BJD Updates for <arch/map.h>
20 * 18-Jan-2003 BJD Added serial port configuration
21 * 05-Oct-2004 BJD Power management code
22 * 04-Nov-2004 BJD Updated serial port clocks
23 * 04-Jan-2005 BJD New uart init call
24 * 10-Jan-2005 BJD Removed include of s3c2410.h
25 * 14-Jan-2005 BJD Add support for muitlple NAND devices
26 * 03-Mar-2005 BJD Ensured that bast-cpld.h is included
27 * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
28 * 14-Mar-2006 BJD Updated for __iomem changes
29 */
30
31 #include <linux/kernel.h>
32 #include <linux/types.h>
33 #include <linux/interrupt.h>
34 #include <linux/list.h>
35 #include <linux/timer.h>
36 #include <linux/init.h>
37 #include <linux/device.h>
38
39 #include <asm/mach/arch.h>
40 #include <asm/mach/map.h>
41 #include <asm/mach/irq.h>
42
43 #include <asm/arch/bast-map.h>
44 #include <asm/arch/bast-irq.h>
45 #include <asm/arch/bast-cpld.h>
46
47 #include <asm/hardware.h>
48 #include <asm/io.h>
49 #include <asm/irq.h>
50 #include <asm/mach-types.h>
51
52 //#include <asm/debug-ll.h>
53 #include <asm/arch/regs-serial.h>
54 #include <asm/arch/regs-gpio.h>
55 #include <asm/arch/regs-mem.h>
56 #include <asm/arch/nand.h>
57
58 #include <linux/mtd/mtd.h>
59 #include <linux/mtd/nand.h>
60 #include <linux/mtd/nand_ecc.h>
61 #include <linux/mtd/partitions.h>
62
63 #include "clock.h"
64 #include "devs.h"
65 #include "cpu.h"
66 #include "usb-simtec.h"
67 #include "pm.h"
68
69 #define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
70
71 /* macros for virtual address mods for the io space entries */
72 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
73 #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
74 #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
75 #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
76
77 /* macros to modify the physical addresses for io space */
78
79 #define PA_CS2(item) ((item) + S3C2410_CS2)
80 #define PA_CS3(item) ((item) + S3C2410_CS3)
81 #define PA_CS4(item) ((item) + S3C2410_CS4)
82 #define PA_CS5(item) ((item) + S3C2410_CS5)
83
84 static struct map_desc bast_iodesc[] __initdata = {
85 /* ISA IO areas */
86
87 { (u32)S3C24XX_VA_ISA_BYTE, PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
88 { (u32)S3C24XX_VA_ISA_WORD, PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
89
90 /* we could possibly compress the next set down into a set of smaller tables
91 * pagetables, but that would mean using an L2 section, and it still means
92 * we cannot actually feed the same register to an LDR due to 16K spacing
93 */
94
95 /* bast CPLD control registers, and external interrupt controls */
96 { (u32)BAST_VA_CTRL1, BAST_PA_CTRL1, SZ_1M, MT_DEVICE },
97 { (u32)BAST_VA_CTRL2, BAST_PA_CTRL2, SZ_1M, MT_DEVICE },
98 { (u32)BAST_VA_CTRL3, BAST_PA_CTRL3, SZ_1M, MT_DEVICE },
99 { (u32)BAST_VA_CTRL4, BAST_PA_CTRL4, SZ_1M, MT_DEVICE },
100
101 /* PC104 IRQ mux */
102 { (u32)BAST_VA_PC104_IRQREQ, BAST_PA_PC104_IRQREQ, SZ_1M, MT_DEVICE },
103 { (u32)BAST_VA_PC104_IRQRAW, BAST_PA_PC104_IRQRAW, SZ_1M, MT_DEVICE },
104 { (u32)BAST_VA_PC104_IRQMASK, BAST_PA_PC104_IRQMASK, SZ_1M, MT_DEVICE },
105
106 /* peripheral space... one for each of fast/slow/byte/16bit */
107 /* note, ide is only decoded in word space, even though some registers
108 * are only 8bit */
109
110 /* slow, byte */
111 { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
112 { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
113 { VA_C2(BAST_VA_ASIXNET), PA_CS3(BAST_PA_ASIXNET), SZ_1M, MT_DEVICE },
114 { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
115 { VA_C2(BAST_VA_DM9000), PA_CS2(BAST_PA_DM9000), SZ_1M, MT_DEVICE },
116 { VA_C2(BAST_VA_IDEPRI), PA_CS3(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
117 { VA_C2(BAST_VA_IDESEC), PA_CS3(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
118 { VA_C2(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
119 { VA_C2(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
120
121 /* slow, word */
122 { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
123 { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
124 { VA_C3(BAST_VA_ASIXNET), PA_CS3(BAST_PA_ASIXNET), SZ_1M, MT_DEVICE },
125 { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
126 { VA_C3(BAST_VA_DM9000), PA_CS3(BAST_PA_DM9000), SZ_1M, MT_DEVICE },
127 { VA_C3(BAST_VA_IDEPRI), PA_CS3(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
128 { VA_C3(BAST_VA_IDESEC), PA_CS3(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
129 { VA_C3(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
130 { VA_C3(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
131
132 /* fast, byte */
133 { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
134 { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
135 { VA_C4(BAST_VA_ASIXNET), PA_CS5(BAST_PA_ASIXNET), SZ_1M, MT_DEVICE },
136 { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
137 { VA_C4(BAST_VA_DM9000), PA_CS4(BAST_PA_DM9000), SZ_1M, MT_DEVICE },
138 { VA_C4(BAST_VA_IDEPRI), PA_CS5(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
139 { VA_C4(BAST_VA_IDESEC), PA_CS5(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
140 { VA_C4(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
141 { VA_C4(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
142
143 /* fast, word */
144 { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
145 { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
146 { VA_C5(BAST_VA_ASIXNET), PA_CS5(BAST_PA_ASIXNET), SZ_1M, MT_DEVICE },
147 { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
148 { VA_C5(BAST_VA_DM9000), PA_CS5(BAST_PA_DM9000), SZ_1M, MT_DEVICE },
149 { VA_C5(BAST_VA_IDEPRI), PA_CS5(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
150 { VA_C5(BAST_VA_IDESEC), PA_CS5(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
151 { VA_C5(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
152 { VA_C5(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
153 };
154
155 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
156 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
157 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
158
159 static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
160 [0] = {
161 .name = "uclk",
162 .divisor = 1,
163 .min_baud = 0,
164 .max_baud = 0,
165 },
166 [1] = {
167 .name = "pclk",
168 .divisor = 1,
169 .min_baud = 0,
170 .max_baud = 0.
171 }
172 };
173
174
175 static struct s3c2410_uartcfg bast_uartcfgs[] = {
176 [0] = {
177 .hwport = 0,
178 .flags = 0,
179 .ucon = UCON,
180 .ulcon = ULCON,
181 .ufcon = UFCON,
182 .clocks = bast_serial_clocks,
183 .clocks_size = ARRAY_SIZE(bast_serial_clocks)
184 },
185 [1] = {
186 .hwport = 1,
187 .flags = 0,
188 .ucon = UCON,
189 .ulcon = ULCON,
190 .ufcon = UFCON,
191 .clocks = bast_serial_clocks,
192 .clocks_size = ARRAY_SIZE(bast_serial_clocks)
193 },
194 /* port 2 is not actually used */
195 [2] = {
196 .hwport = 2,
197 .flags = 0,
198 .ucon = UCON,
199 .ulcon = ULCON,
200 .ufcon = UFCON,
201 .clocks = bast_serial_clocks,
202 .clocks_size = ARRAY_SIZE(bast_serial_clocks)
203 }
204 };
205
206 /* NOR Flash on BAST board */
207
208 static struct resource bast_nor_resource[] = {
209 [0] = {
210 .start = S3C2410_CS1 + 0x4000000,
211 .end = S3C2410_CS1 + 0x4000000 + (32*1024*1024) - 1,
212 .flags = IORESOURCE_MEM,
213 }
214 };
215
216 static struct platform_device bast_device_nor = {
217 .name = "bast-nor",
218 .id = -1,
219 .num_resources = ARRAY_SIZE(bast_nor_resource),
220 .resource = bast_nor_resource,
221 };
222
223 /* NAND Flash on BAST board */
224
225
226 static int smartmedia_map[] = { 0 };
227 static int chip0_map[] = { 1 };
228 static int chip1_map[] = { 2 };
229 static int chip2_map[] = { 3 };
230
231 struct mtd_partition bast_default_nand_part[] = {
232 [0] = {
233 .name = "Boot Agent",
234 .size = SZ_16K,
235 .offset = 0
236 },
237 [1] = {
238 .name = "/boot",
239 .size = SZ_4M - SZ_16K,
240 .offset = SZ_16K,
241 },
242 [2] = {
243 .name = "user",
244 .offset = SZ_4M,
245 .size = MTDPART_SIZ_FULL,
246 }
247 };
248
249 /* the bast has 4 selectable slots for nand-flash, the three
250 * on-board chip areas, as well as the external SmartMedia
251 * slot.
252 *
253 * Note, there is no current hot-plug support for the SmartMedia
254 * socket.
255 */
256
257 static struct s3c2410_nand_set bast_nand_sets[] = {
258 [0] = {
259 .name = "SmartMedia",
260 .nr_chips = 1,
261 .nr_map = smartmedia_map,
262 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
263 .partitions = bast_default_nand_part
264 },
265 [1] = {
266 .name = "chip0",
267 .nr_chips = 1,
268 .nr_map = chip0_map,
269 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
270 .partitions = bast_default_nand_part
271 },
272 [2] = {
273 .name = "chip1",
274 .nr_chips = 1,
275 .nr_map = chip1_map,
276 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
277 .partitions = bast_default_nand_part
278 },
279 [3] = {
280 .name = "chip2",
281 .nr_chips = 1,
282 .nr_map = chip2_map,
283 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
284 .partitions = bast_default_nand_part
285 }
286 };
287
288 static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
289 {
290 unsigned int tmp;
291
292 slot = set->nr_map[slot] & 3;
293
294 pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
295 slot, set, set->nr_map);
296
297 tmp = __raw_readb(BAST_VA_CTRL2);
298 tmp &= BAST_CPLD_CTLR2_IDERST;
299 tmp |= slot;
300 tmp |= BAST_CPLD_CTRL2_WNAND;
301
302 pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
303
304 __raw_writeb(tmp, BAST_VA_CTRL2);
305 }
306
307 static struct s3c2410_platform_nand bast_nand_info = {
308 .tacls = 80,
309 .twrph0 = 80,
310 .twrph1 = 80,
311 .nr_sets = ARRAY_SIZE(bast_nand_sets),
312 .sets = bast_nand_sets,
313 .select_chip = bast_nand_select,
314 };
315
316
317 /* Standard BAST devices */
318
319 static struct platform_device *bast_devices[] __initdata = {
320 &s3c_device_usb,
321 &s3c_device_lcd,
322 &s3c_device_wdt,
323 &s3c_device_i2c,
324 &s3c_device_iis,
325 &s3c_device_rtc,
326 &s3c_device_nand,
327 &bast_device_nor
328 };
329
330 static struct clk *bast_clocks[] = {
331 &s3c24xx_dclk0,
332 &s3c24xx_dclk1,
333 &s3c24xx_clkout0,
334 &s3c24xx_clkout1,
335 &s3c24xx_uclk,
336 };
337
338 static struct s3c24xx_board bast_board __initdata = {
339 .devices = bast_devices,
340 .devices_count = ARRAY_SIZE(bast_devices),
341 .clocks = bast_clocks,
342 .clocks_count = ARRAY_SIZE(bast_clocks)
343 };
344
345 void __init bast_map_io(void)
346 {
347 /* initialise the clocks */
348
349 s3c24xx_dclk0.parent = NULL;
350 s3c24xx_dclk0.rate = 12*1000*1000;
351
352 s3c24xx_dclk1.parent = NULL;
353 s3c24xx_dclk1.rate = 24*1000*1000;
354
355 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
356 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
357
358 s3c24xx_uclk.parent = &s3c24xx_clkout1;
359
360 s3c_device_nand.dev.platform_data = &bast_nand_info;
361
362 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
363 s3c24xx_init_clocks(0);
364 s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
365 s3c24xx_set_board(&bast_board);
366 usb_simtec_init();
367 }
368
369 void __init bast_init_irq(void)
370 {
371 s3c24xx_init_irq();
372 }
373
374 #ifdef CONFIG_PM
375
376 /* bast_init_machine
377 *
378 * enable the power management functions for the EB2410ITX
379 */
380
381 static __init void bast_init_machine(void)
382 {
383 unsigned long gstatus4;
384
385 printk(KERN_INFO "BAST Power Manangement" COPYRIGHT "\n");
386
387 gstatus4 = (__raw_readl(S3C2410_BANKCON7) & 0x3) << 30;
388 gstatus4 |= (__raw_readl(S3C2410_BANKCON6) & 0x3) << 28;
389 gstatus4 |= (__raw_readl(S3C2410_BANKSIZE) & S3C2410_BANKSIZE_MASK);
390
391 __raw_writel(gstatus4, S3C2410_GSTATUS4);
392
393 s3c2410_pm_init();
394 }
395
396 #else
397 #define bast_init_machine NULL
398 #endif
399
400
401 MACHINE_START(BAST, "Simtec-BAST")
402 MAINTAINER("Ben Dooks <ben@simtec.co.uk>")
403 BOOT_MEM(S3C2410_SDRAM_PA, S3C2410_PA_UART, (u32)S3C24XX_VA_UART)
404 BOOT_PARAMS(S3C2410_SDRAM_PA + 0x100)
405 MAPIO(bast_map_io)
406 INITIRQ(bast_init_irq)
407 .init_machine = bast_init_machine,
408 .timer = &s3c24xx_timer,
409 MACHINE_END
Verdex Pro support