arch/arm/mm/copypage-v4mc.c

   1 /*
   2  *  linux/arch/arm/lib/copypage-armv4mc.S
   3  *
   4  *  Copyright (C) 1995-2005 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This handles the mini data cache, as found on SA11x0 and XScale
  11  * processors.  When we copy a user page page, we map it in such a way
  12  * that accesses to this page will not touch the main data cache, but
  13  * will be cached in the mini data cache.  This prevents us thrashing
  14  * the main data cache on page faults.
  15  */
  16 #include <linux/init.h>
  17 #include <linux/mm.h>
  18
  19 #include <asm/page.h>
  20 #include <asm/pgtable.h>
  21 #include <asm/tlbflush.h>
  22
  23 /*
  24  * 0xffff8000 to 0xffffffff is reserved for any ARM architecture
  25  * specific hacks for copying pages efficiently.
  26  */
  27 #define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \
  28                                   L_PTE_CACHEABLE)
  29
  30 #define TOP_PTE(x)      pte_offset_kernel(top_pmd, x)
  31
  32 static DEFINE_SPINLOCK(minicache_lock);
  33
  34 /*
  35  * ARMv4 mini-dcache optimised copy_user_page
  36  *
  37  * We flush the destination cache lines just before we write the data into the
  38  * corresponding address.  Since the Dcache is read-allocate, this removes the
  39  * Dcache aliasing issue.  The writes will be forwarded to the write buffer,
  40  * and merged as appropriate.
  41  *
  42  * Note: We rely on all ARMv4 processors implementing the "invalidate D line"
  43  * instruction.  If your processor does not supply this, you have to write your
  44  * own copy_user_page that does the right thing.
  45  */
  46 static void __attribute__((naked))
  47 mc_copy_user_page(void *from, void *to)
  48 {
  49         asm volatile(
  50         "stmfd  sp!, {r4, lr}                   @ 2\n\
  51         mov     r4, %2                          @ 1\n\
  52         ldmia   %0!, {r2, r3, ip, lr}           @ 4\n\
  53 1:      mcr     p15, 0, %1, c7, c6, 1           @ 1   invalidate D line\n\
  54         stmia   %1!, {r2, r3, ip, lr}           @ 4\n\
  55         ldmia   %0!, {r2, r3, ip, lr}           @ 4+1\n\
  56         stmia   %1!, {r2, r3, ip, lr}           @ 4\n\
  57         ldmia   %0!, {r2, r3, ip, lr}           @ 4\n\
  58         mcr     p15, 0, %1, c7, c6, 1           @ 1   invalidate D line\n\
  59         stmia   %1!, {r2, r3, ip, lr}           @ 4\n\
  60         ldmia   %0!, {r2, r3, ip, lr}           @ 4\n\
  61         subs    r4, r4, #1                      @ 1\n\
  62         stmia   %1!, {r2, r3, ip, lr}           @ 4\n\
  63         ldmneia %0!, {r2, r3, ip, lr}           @ 4\n\
  64         bne     1b                              @ 1\n\
  65         ldmfd   sp!, {r4, pc}                   @ 3"
  66         :
  67         : "r" (from), "r" (to), "I" (PAGE_SIZE / 64));
  68 }
  69
  70 void v4_mc_copy_user_page(void *kto, const void *kfrom, unsigned long vaddr)
  71 {
  72         spin_lock(&minicache_lock);
  73
  74         set_pte(TOP_PTE(0xffff8000), pfn_pte(__pa(kfrom) >> PAGE_SHIFT, minicache_pgprot));
  75         flush_tlb_kernel_page(0xffff8000);
  76
  77         mc_copy_user_page((void *)0xffff8000, kto);
  78
  79         spin_unlock(&minicache_lock);
  80 }
  81
  82 /*
  83  * ARMv4 optimised clear_user_page
  84  */
  85 void __attribute__((naked))
  86 v4_mc_clear_user_page(void *kaddr, unsigned long vaddr)
  87 {
  88         asm volatile(
  89         "str    lr, [sp, #-4]!\n\
  90         mov     r1, %0                          @ 1\n\
  91         mov     r2, #0                          @ 1\n\
  92         mov     r3, #0                          @ 1\n\
  93         mov     ip, #0                          @ 1\n\
  94         mov     lr, #0                          @ 1\n\
  95 1:      mcr     p15, 0, r0, c7, c6, 1           @ 1   invalidate D line\n\
  96         stmia   r0!, {r2, r3, ip, lr}           @ 4\n\
  97         stmia   r0!, {r2, r3, ip, lr}           @ 4\n\
  98         mcr     p15, 0, r0, c7, c6, 1           @ 1   invalidate D line\n\
  99         stmia   r0!, {r2, r3, ip, lr}           @ 4\n\
 100         stmia   r0!, {r2, r3, ip, lr}           @ 4\n\
 101         subs    r1, r1, #1                      @ 1\n\
 102         bne     1b                              @ 1\n\
 103         ldr     pc, [sp], #4"
 104         :
 105         : "I" (PAGE_SIZE / 64));
 106 }
 107
 108 struct cpu_user_fns v4_mc_user_fns __initdata = {
 109         .cpu_clear_user_page    = v4_mc_clear_user_page,
 110         .cpu_copy_user_page     = v4_mc_copy_user_page,
 111 };