[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / arch / arm26 / lib / io-writesl.S
blob4d6049b16e71fbbe7b1bfaf36976e796ceacd19c
1 /*
2  *  linux/arch/arm26/lib/io-writesl.S
3  *
4  *  Copyright (C) 1995-2000 Russell King
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
10 #include <linux/linkage.h>
11 #include <asm/assembler.h>
12 #include <asm/hardware.h>
14 ENTRY(__raw_writesl)
15                 teq     r2, #0          @ do we have to check for the zero len?
16                 moveq   pc, lr
17                 ands    ip, r1, #3
18                 bne     2f
20 1:              ldr     r3, [r1], #4
21                 str     r3, [r0]
22                 subs    r2, r2, #1
23                 bne     1b
24                 mov     pc, lr
26 2:              bic     r1, r1, #3
27                 cmp     ip, #2
28                 ldr     r3, [r1], #4
29                 bgt     4f
30                 blt     5f
32 3:              mov     ip, r3, lsr #16
33                 ldr     r3, [r1], #4
34                 orr     ip, ip, r3, lsl #16
35                 str     ip, [r0]
36                 subs    r2, r2, #1
37                 bne     3b
38                 mov     pc, lr
40 4:              mov     ip, r3, lsr #24
41                 ldr     r3, [r1], #4
42                 orr     ip, ip, r3, lsl #8
43                 str     ip, [r0]
44                 subs    r2, r2, #1
45                 bne     4b
46                 mov     pc, lr
48 5:              mov     ip, r3, lsr #8
49                 ldr     r3, [r1], #4
50                 orr     ip, ip, r3, lsl #24
51                 str     ip, [r0]
52                 subs    r2, r2, #1
53                 bne     5b
54                 mov     pc, lr