arch/ia64/sn/pci/pci_dma.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2000,2002-2005 Silicon Graphics, Inc. All rights reserved.
   7  *
   8  * Routines for PCI DMA mapping.  See Documentation/DMA-API.txt for
   9  * a description of how these routines should be used.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <asm/dma.h>
  14 #include <asm/sn/sn_sal.h>
  15 #include <asm/sn/pcibus_provider_defs.h>
  16 #include <asm/sn/pcidev.h>
  17
  18 #define SG_ENT_VIRT_ADDRESS(sg) (page_address((sg)->page) + (sg)->offset)
  19 #define SG_ENT_PHYS_ADDRESS(SG) virt_to_phys(SG_ENT_VIRT_ADDRESS(SG))
  20
  21 /**
  22  * sn_dma_supported - test a DMA mask
  23  * @dev: device to test
  24  * @mask: DMA mask to test
  25  *
  26  * Return whether the given PCI device DMA address mask can be supported
  27  * properly.  For example, if your device can only drive the low 24-bits
  28  * during PCI bus mastering, then you would pass 0x00ffffff as the mask to
  29  * this function.  Of course, SN only supports devices that have 32 or more
  30  * address bits when using the PMU.
  31  */
  32 int sn_dma_supported(struct device *dev, u64 mask)
  33 {
  34         BUG_ON(dev->bus != &pci_bus_type);
  35
  36         if (mask < 0x7fffffff)
  37                 return 0;
  38         return 1;
  39 }
  40 EXPORT_SYMBOL(sn_dma_supported);
  41
  42 /**
  43  * sn_dma_set_mask - set the DMA mask
  44  * @dev: device to set
  45  * @dma_mask: new mask
  46  *
  47  * Set @dev's DMA mask if the hw supports it.
  48  */
  49 int sn_dma_set_mask(struct device *dev, u64 dma_mask)
  50 {
  51         BUG_ON(dev->bus != &pci_bus_type);
  52
  53         if (!sn_dma_supported(dev, dma_mask))
  54                 return 0;
  55
  56         *dev->dma_mask = dma_mask;
  57         return 1;
  58 }
  59 EXPORT_SYMBOL(sn_dma_set_mask);
  60
  61 /**
  62  * sn_dma_alloc_coherent - allocate memory for coherent DMA
  63  * @dev: device to allocate for
  64  * @size: size of the region
  65  * @dma_handle: DMA (bus) address
  66  * @flags: memory allocation flags
  67  *
  68  * dma_alloc_coherent() returns a pointer to a memory region suitable for
  69  * coherent DMA traffic to/from a PCI device.  On SN platforms, this means
  70  * that @dma_handle will have the %PCIIO_DMA_CMD flag set.
  71  *
  72  * This interface is usually used for "command" streams (e.g. the command
  73  * queue for a SCSI controller).  See Documentation/DMA-API.txt for
  74  * more information.
  75  */
  76 void *sn_dma_alloc_coherent(struct device *dev, size_t size,
  77                             dma_addr_t * dma_handle, int flags)
  78 {
  79         void *cpuaddr;
  80         unsigned long phys_addr;
  81         struct pci_dev *pdev = to_pci_dev(dev);
  82         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
  83
  84         BUG_ON(dev->bus != &pci_bus_type);
  85
  86         /*
  87          * Allocate the memory.
  88          * FIXME: We should be doing alloc_pages_node for the node closest
  89          *        to the PCI device.
  90          */
  91         if (!(cpuaddr = (void *)__get_free_pages(GFP_ATOMIC, get_order(size))))
  92                 return NULL;
  93
  94         memset(cpuaddr, 0x0, size);
  95
  96         /* physical addr. of the memory we just got */
  97         phys_addr = __pa(cpuaddr);
  98
  99         /*
 100          * 64 bit address translations should never fail.
 101          * 32 bit translations can fail if there are insufficient mapping
 102          * resources.
 103          */
 104
 105         *dma_handle = provider->dma_map_consistent(pdev, phys_addr, size);
 106         if (!*dma_handle) {
 107                 printk(KERN_ERR "%s: out of ATEs\n", __FUNCTION__);
 108                 free_pages((unsigned long)cpuaddr, get_order(size));
 109                 return NULL;
 110         }
 111
 112         return cpuaddr;
 113 }
 114 EXPORT_SYMBOL(sn_dma_alloc_coherent);
 115
 116 /**
 117  * sn_pci_free_coherent - free memory associated with coherent DMAable region
 118  * @dev: device to free for
 119  * @size: size to free
 120  * @cpu_addr: kernel virtual address to free
 121  * @dma_handle: DMA address associated with this region
 122  *
 123  * Frees the memory allocated by dma_alloc_coherent(), potentially unmapping
 124  * any associated IOMMU mappings.
 125  */
 126 void sn_dma_free_coherent(struct device *dev, size_t size, void *cpu_addr,
 127                           dma_addr_t dma_handle)
 128 {
 129         struct pci_dev *pdev = to_pci_dev(dev);
 130         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
 131
 132         BUG_ON(dev->bus != &pci_bus_type);
 133
 134         provider->dma_unmap(pdev, dma_handle, 0);
 135         free_pages((unsigned long)cpu_addr, get_order(size));
 136 }
 137 EXPORT_SYMBOL(sn_dma_free_coherent);
 138
 139 /**
 140  * sn_dma_map_single - map a single page for DMA
 141  * @dev: device to map for
 142  * @cpu_addr: kernel virtual address of the region to map
 143  * @size: size of the region
 144  * @direction: DMA direction
 145  *
 146  * Map the region pointed to by @cpu_addr for DMA and return the
 147  * DMA address.
 148  *
 149  * We map this to the one step pcibr_dmamap_trans interface rather than
 150  * the two step pcibr_dmamap_alloc/pcibr_dmamap_addr because we have
 151  * no way of saving the dmamap handle from the alloc to later free
 152  * (which is pretty much unacceptable).
 153  *
 154  * TODO: simplify our interface;
 155  *       figure out how to save dmamap handle so can use two step.
 156  */
 157 dma_addr_t sn_dma_map_single(struct device *dev, void *cpu_addr, size_t size,
 158                              int direction)
 159 {
 160         dma_addr_t dma_addr;
 161         unsigned long phys_addr;
 162         struct pci_dev *pdev = to_pci_dev(dev);
 163         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
 164
 165         BUG_ON(dev->bus != &pci_bus_type);
 166
 167         phys_addr = __pa(cpu_addr);
 168         dma_addr = provider->dma_map(pdev, phys_addr, size);
 169         if (!dma_addr) {
 170                 printk(KERN_ERR "%s: out of ATEs\n", __FUNCTION__);
 171                 return 0;
 172         }
 173         return dma_addr;
 174 }
 175 EXPORT_SYMBOL(sn_dma_map_single);
 176
 177 /**
 178  * sn_dma_unmap_single - unamp a DMA mapped page
 179  * @dev: device to sync
 180  * @dma_addr: DMA address to sync
 181  * @size: size of region
 182  * @direction: DMA direction
 183  *
 184  * This routine is supposed to sync the DMA region specified
 185  * by @dma_handle into the coherence domain.  On SN, we're always cache
 186  * coherent, so we just need to free any ATEs associated with this mapping.
 187  */
 188 void sn_dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
 189                          int direction)
 190 {
 191         struct pci_dev *pdev = to_pci_dev(dev);
 192         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
 193
 194         BUG_ON(dev->bus != &pci_bus_type);
 195
 196         provider->dma_unmap(pdev, dma_addr, direction);
 197 }
 198 EXPORT_SYMBOL(sn_dma_unmap_single);
 199
 200 /**
 201  * sn_dma_unmap_sg - unmap a DMA scatterlist
 202  * @dev: device to unmap
 203  * @sg: scatterlist to unmap
 204  * @nhwentries: number of scatterlist entries
 205  * @direction: DMA direction
 206  *
 207  * Unmap a set of streaming mode DMA translations.
 208  */
 209 void sn_dma_unmap_sg(struct device *dev, struct scatterlist *sg,
 210                      int nhwentries, int direction)
 211 {
 212         int i;
 213         struct pci_dev *pdev = to_pci_dev(dev);
 214         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
 215
 216         BUG_ON(dev->bus != &pci_bus_type);
 217
 218         for (i = 0; i < nhwentries; i++, sg++) {
 219                 provider->dma_unmap(pdev, sg->dma_address, direction);
 220                 sg->dma_address = (dma_addr_t) NULL;
 221                 sg->dma_length = 0;
 222         }
 223 }
 224 EXPORT_SYMBOL(sn_dma_unmap_sg);
 225
 226 /**
 227  * sn_dma_map_sg - map a scatterlist for DMA
 228  * @dev: device to map for
 229  * @sg: scatterlist to map
 230  * @nhwentries: number of entries
 231  * @direction: direction of the DMA transaction
 232  *
 233  * Maps each entry of @sg for DMA.
 234  */
 235 int sn_dma_map_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
 236                   int direction)
 237 {
 238         unsigned long phys_addr;
 239         struct scatterlist *saved_sg = sg;
 240         struct pci_dev *pdev = to_pci_dev(dev);
 241         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
 242         int i;
 243
 244         BUG_ON(dev->bus != &pci_bus_type);
 245
 246         /*
 247          * Setup a DMA address for each entry in the scatterlist.
 248          */
 249         for (i = 0; i < nhwentries; i++, sg++) {
 250                 phys_addr = SG_ENT_PHYS_ADDRESS(sg);
 251                 sg->dma_address = provider->dma_map(pdev,
 252                                                     phys_addr, sg->length);
 253
 254                 if (!sg->dma_address) {
 255                         printk(KERN_ERR "%s: out of ATEs\n", __FUNCTION__);
 256
 257                         /*
 258                          * Free any successfully allocated entries.
 259                          */
 260                         if (i > 0)
 261                                 sn_dma_unmap_sg(dev, saved_sg, i, direction);
 262                         return 0;
 263                 }
 264
 265                 sg->dma_length = sg->length;
 266         }
 267
 268         return nhwentries;
 269 }
 270 EXPORT_SYMBOL(sn_dma_map_sg);
 271
 272 void sn_dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
 273                                 size_t size, int direction)
 274 {
 275         BUG_ON(dev->bus != &pci_bus_type);
 276 }
 277 EXPORT_SYMBOL(sn_dma_sync_single_for_cpu);
 278
 279 void sn_dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
 280                                    size_t size, int direction)
 281 {
 282         BUG_ON(dev->bus != &pci_bus_type);
 283 }
 284 EXPORT_SYMBOL(sn_dma_sync_single_for_device);
 285
 286 void sn_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
 287                             int nelems, int direction)
 288 {
 289         BUG_ON(dev->bus != &pci_bus_type);
 290 }
 291 EXPORT_SYMBOL(sn_dma_sync_sg_for_cpu);
 292
 293 void sn_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
 294                                int nelems, int direction)
 295 {
 296         BUG_ON(dev->bus != &pci_bus_type);
 297 }
 298 EXPORT_SYMBOL(sn_dma_sync_sg_for_device);
 299
 300 int sn_dma_mapping_error(dma_addr_t dma_addr)
 301 {
 302         return 0;
 303 }
 304 EXPORT_SYMBOL(sn_dma_mapping_error);
 305
 306 char *sn_pci_get_legacy_mem(struct pci_bus *bus)
 307 {
 308         if (!SN_PCIBUS_BUSSOFT(bus))
 309                 return ERR_PTR(-ENODEV);
 310
 311         return (char *)(SN_PCIBUS_BUSSOFT(bus)->bs_legacy_mem | __IA64_UNCACHED_OFFSET);
 312 }
 313
 314 int sn_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
 315 {
 316         unsigned long addr;
 317         int ret;
 318
 319         if (!SN_PCIBUS_BUSSOFT(bus))
 320                 return -ENODEV;
 321
 322         addr = SN_PCIBUS_BUSSOFT(bus)->bs_legacy_io | __IA64_UNCACHED_OFFSET;
 323         addr += port;
 324
 325         ret = ia64_sn_probe_mem(addr, (long)size, (void *)val);
 326
 327         if (ret == 2)
 328                 return -EINVAL;
 329
 330         if (ret == 1)
 331                 *val = -1;
 332
 333         return size;
 334 }
 335
 336 int sn_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
 337 {
 338         int ret = size;
 339         unsigned long paddr;
 340         unsigned long *addr;
 341
 342         if (!SN_PCIBUS_BUSSOFT(bus)) {
 343                 ret = -ENODEV;
 344                 goto out;
 345         }
 346
 347         /* Put the phys addr in uncached space */
 348         paddr = SN_PCIBUS_BUSSOFT(bus)->bs_legacy_io | __IA64_UNCACHED_OFFSET;
 349         paddr += port;
 350         addr = (unsigned long *)paddr;
 351
 352         switch (size) {
 353         case 1:
 354                 *(volatile u8 *)(addr) = (u8)(val);
 355                 break;
 356         case 2:
 357                 *(volatile u16 *)(addr) = (u16)(val);
 358                 break;
 359         case 4:
 360                 *(volatile u32 *)(addr) = (u32)(val);
 361                 break;
 362         default:
 363                 ret = -EINVAL;
 364                 break;
 365         }
 366  out:
 367         return ret;
 368 }