[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / arch / mips / au1000 / common / dbg_io.c
blob7bc768e558dbec0bb14dd2c1311d7a67963ed701
2 #include <linux/config.h>
3 #include <asm/io.h>
4 #include <asm/mach-au1x00/au1000.h>
6 #ifdef CONFIG_KGDB
8 /*
9 * FIXME the user should be able to select the
10 * uart to be used for debugging.
12 #define DEBUG_BASE UART_DEBUG_BASE
13 /**/
15 /* we need uint32 uint8 */
16 /* #include "types.h" */
17 typedef unsigned char uint8;
18 typedef unsigned int uint32;
20 #define UART16550_BAUD_2400 2400
21 #define UART16550_BAUD_4800 4800
22 #define UART16550_BAUD_9600 9600
23 #define UART16550_BAUD_19200 19200
24 #define UART16550_BAUD_38400 38400
25 #define UART16550_BAUD_57600 57600
26 #define UART16550_BAUD_115200 115200
28 #define UART16550_PARITY_NONE 0
29 #define UART16550_PARITY_ODD 0x08
30 #define UART16550_PARITY_EVEN 0x18
31 #define UART16550_PARITY_MARK 0x28
32 #define UART16550_PARITY_SPACE 0x38
34 #define UART16550_DATA_5BIT 0x0
35 #define UART16550_DATA_6BIT 0x1
36 #define UART16550_DATA_7BIT 0x2
37 #define UART16550_DATA_8BIT 0x3
39 #define UART16550_STOP_1BIT 0x0
40 #define UART16550_STOP_2BIT 0x4
43 #define UART_RX 0 /* Receive buffer */
44 #define UART_TX 4 /* Transmit buffer */
45 #define UART_IER 8 /* Interrupt Enable Register */
46 #define UART_IIR 0xC /* Interrupt ID Register */
47 #define UART_FCR 0x10 /* FIFO Control Register */
48 #define UART_LCR 0x14 /* Line Control Register */
49 #define UART_MCR 0x18 /* Modem Control Register */
50 #define UART_LSR 0x1C /* Line Status Register */
51 #define UART_MSR 0x20 /* Modem Status Register */
52 #define UART_CLK 0x28 /* Baud Rat4e Clock Divider */
53 #define UART_MOD_CNTRL 0x100 /* Module Control */
55 /* memory-mapped read/write of the port */
56 #define UART16550_READ(y) (au_readl(DEBUG_BASE + y) & 0xff)
57 #define UART16550_WRITE(y,z) (au_writel(z&0xff, DEBUG_BASE + y))
59 extern unsigned long get_au1x00_uart_baud_base(void);
60 extern unsigned long cal_r4koff(void);
62 void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
65 if (UART16550_READ(UART_MOD_CNTRL) != 0x3) {
66 UART16550_WRITE(UART_MOD_CNTRL, 3);
68 cal_r4koff();
70 /* disable interrupts */
71 UART16550_WRITE(UART_IER, 0);
73 /* set up baud rate */
75 uint32 divisor;
77 /* set divisor */
78 divisor = get_au1x00_uart_baud_base() / baud;
79 UART16550_WRITE(UART_CLK, divisor & 0xffff);
82 /* set data format */
83 UART16550_WRITE(UART_LCR, (data | parity | stop));
86 static int remoteDebugInitialized = 0;
88 uint8 getDebugChar(void)
90 if (!remoteDebugInitialized) {
91 remoteDebugInitialized = 1;
92 debugInit(UART16550_BAUD_115200,
93 UART16550_DATA_8BIT,
94 UART16550_PARITY_NONE,
95 UART16550_STOP_1BIT);
98 while((UART16550_READ(UART_LSR) & 0x1) == 0);
99 return UART16550_READ(UART_RX);
103 int putDebugChar(uint8 byte)
105 // int i;
107 if (!remoteDebugInitialized) {
108 remoteDebugInitialized = 1;
109 debugInit(UART16550_BAUD_115200,
110 UART16550_DATA_8BIT,
111 UART16550_PARITY_NONE,
112 UART16550_STOP_1BIT);
115 while ((UART16550_READ(UART_LSR)&0x40) == 0);
116 UART16550_WRITE(UART_TX, byte);
117 //for (i=0;i<0xfff;i++);
119 return 1;
122 #endif