arch/mips/au1000/common/setup.c

   1 /*
   2  * Copyright 2000 MontaVista Software Inc.
   3  * Author: MontaVista Software, Inc.
   4  *              ppopov@mvista.com or source@mvista.com
   5  *
   6  * Updates to 2.6, Pete Popov, Embedded Alley Solutions, Inc.
   7  *
   8  *  This program is free software; you can redistribute  it and/or modify it
   9  *  under  the terms of  the GNU General  Public License as published by the
  10  *  Free Software Foundation;  either version 2 of the  License, or (at your
  11  *  option) any later version.
  12  *
  13  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  14  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  15  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  16  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  17  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  18  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  19  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  20  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  21  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  22  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23  *
  24  *  You should have received a copy of the  GNU General Public License along
  25  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  26  *  675 Mass Ave, Cambridge, MA 02139, USA.
  27  */
  28 #include <linux/config.h>
  29 #include <linux/init.h>
  30 #include <linux/sched.h>
  31 #include <linux/ioport.h>
  32 #include <linux/mm.h>
  33 #include <linux/delay.h>
  34 #include <linux/interrupt.h>
  35
  36 #include <asm/cpu.h>
  37 #include <asm/bootinfo.h>
  38 #include <asm/irq.h>
  39 #include <asm/mipsregs.h>
  40 #include <asm/reboot.h>
  41 #include <asm/pgtable.h>
  42 #include <asm/mach-au1x00/au1000.h>
  43 #include <asm/time.h>
  44
  45 extern char * __init prom_getcmdline(void);
  46 extern void __init board_setup(void);
  47 extern void au1000_restart(char *);
  48 extern void au1000_halt(void);
  49 extern void au1000_power_off(void);
  50 extern struct resource ioport_resource;
  51 extern struct resource iomem_resource;
  52 extern void (*board_time_init)(void);
  53 extern void au1x_time_init(void);
  54 extern void (*board_timer_setup)(struct irqaction *irq);
  55 extern void au1x_timer_setup(struct irqaction *irq);
  56 extern void au1xxx_time_init(void);
  57 extern void au1xxx_timer_setup(struct irqaction *irq);
  58 extern void set_cpuspec(void);
  59
  60 static int __init au1x00_setup(void)
  61 {
  62         struct  cpu_spec *sp;
  63         char *argptr;
  64         unsigned long prid, cpupll, bclk = 1;
  65
  66         set_cpuspec();
  67         sp = cur_cpu_spec[0];
  68
  69         board_setup();  /* board specific setup */
  70
  71         prid = read_c0_prid();
  72         cpupll = (au_readl(0xB1900060) & 0x3F) * 12;
  73         printk("(PRId %08lx) @ %ldMHZ\n", prid, cpupll);
  74
  75         bclk = sp->cpu_bclk;
  76         if (bclk)
  77         {
  78                 /* Enable BCLK switching */
  79                 bclk = au_readl(0xB190003C);
  80                 au_writel(bclk | 0x60, 0xB190003C);
  81                 printk("BCLK switching enabled!\n");
  82         }
  83
  84         if (sp->cpu_od) {
  85                 /* Various early Au1000 Errata corrected by this */
  86                 set_c0_config(1<<19); /* Set Config[OD] */
  87         }
  88         else {
  89                 /* Clear to obtain best system bus performance */
  90                 clear_c0_config(1<<19); /* Clear Config[OD] */
  91         }
  92
  93         argptr = prom_getcmdline();
  94
  95 #ifdef CONFIG_SERIAL_AU1X00_CONSOLE
  96         if ((argptr = strstr(argptr, "console=")) == NULL) {
  97                 argptr = prom_getcmdline();
  98                 strcat(argptr, " console=ttyS0,115200");
  99         }
 100 #endif
 101
 102 #ifdef CONFIG_FB_AU1100
 103     if ((argptr = strstr(argptr, "video=")) == NULL) {
 104         argptr = prom_getcmdline();
 105         /* default panel */
 106         /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
 107 #ifdef CONFIG_MIPS_HYDROGEN3
 108          strcat(argptr, " video=au1100fb:panel:Hydrogen_3_NEC_panel_320x240,nohwcursor");
 109 #else
 110         strcat(argptr, " video=au1100fb:panel:s10,nohwcursor");
 111 #endif
 112     }
 113 #endif
 114
 115 #ifdef CONFIG_FB_E1356
 116         if ((argptr = strstr(argptr, "video=")) == NULL) {
 117                 argptr = prom_getcmdline();
 118 #ifdef CONFIG_MIPS_PB1000
 119                 strcat(argptr, " video=e1356fb:system:pb1000,mmunalign:1");
 120 #else
 121                 strcat(argptr, " video=e1356fb:system:pb1500");
 122 #endif
 123         }
 124 #endif
 125
 126 #ifdef CONFIG_FB_XPERT98
 127         if ((argptr = strstr(argptr, "video=")) == NULL) {
 128                 argptr = prom_getcmdline();
 129                 strcat(argptr, " video=atyfb:1024x768-8@70");
 130         }
 131 #endif
 132
 133 #if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000)
 134         /* au1000 does not support vra, au1500 and au1100 do */
 135         strcat(argptr, " au1000_audio=vra");
 136         argptr = prom_getcmdline();
 137 #endif
 138         _machine_restart = au1000_restart;
 139         _machine_halt = au1000_halt;
 140         _machine_power_off = au1000_power_off;
 141         board_time_init = au1xxx_time_init;
 142         board_timer_setup = au1xxx_timer_setup;
 143
 144         /* IO/MEM resources. */
 145         set_io_port_base(0);
 146         ioport_resource.start = IOPORT_RESOURCE_START;
 147         ioport_resource.end = IOPORT_RESOURCE_END;
 148         iomem_resource.start = IOMEM_RESOURCE_START;
 149         iomem_resource.end = IOMEM_RESOURCE_END;
 150
 151         while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S);
 152         au_writel(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL);
 153         au_sync();
 154         while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S);
 155         au_writel(0, SYS_TOYTRIM);
 156
 157         return 0;
 158 }
 159
 160 early_initcall(au1x00_setup);
 161
 162 #if defined(CONFIG_64BIT_PHYS_ADDR)
 163 /* This routine should be valid for all Au1x based boards */
 164 phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
 165 {
 166         u32 start, end;
 167
 168         /* Don't fixup 36 bit addresses */
 169         if ((phys_addr >> 32) != 0) return phys_addr;
 170
 171 #ifdef CONFIG_PCI
 172         start = (u32)Au1500_PCI_MEM_START;
 173         end = (u32)Au1500_PCI_MEM_END;
 174         /* check for pci memory window */
 175         if ((phys_addr >= start) && ((phys_addr + size) < end)) {
 176                 return (phys_t)((phys_addr - start) + Au1500_PCI_MEM_START);
 177         }
 178 #endif
 179
 180         /* All Au1x SOCs have a pcmcia controller */
 181         /* We setup our 32 bit pseudo addresses to be equal to the
 182          * 36 bit addr >> 4, to make it easier to check the address
 183          * and fix it.
 184          * The Au1x socket 0 phys attribute address is 0xF 4000 0000.
 185          * The pseudo address we use is 0xF400 0000. Any address over
 186          * 0xF400 0000 is a pcmcia pseudo address.
 187          */
 188         if ((phys_addr >= 0xF4000000) && (phys_addr < 0xFFFFFFFF)) {
 189                 return (phys_t)(phys_addr << 4);
 190         }
 191
 192         /* default nop */
 193         return phys_addr;
 194 }
 195 #endif