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[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / arch / mips / dec / setup.c
blob6a69309baf40e24e7f8c7d1d42ad2fa1815f7f2a
1 /*
2 * Setup the interrupt stuff.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1998 Harald Koerfgen
9 * Copyright (C) 2000, 2001, 2002, 2003 Maciej W. Rozycki
10 */
11 #include <linux/sched.h>
12 #include <linux/interrupt.h>
13 #include <linux/param.h>
14 #include <linux/console.h>
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/types.h>
19
20 #include <asm/bootinfo.h>
21 #include <asm/cpu.h>
22 #include <asm/cpu-features.h>
23 #include <asm/irq.h>
24 #include <asm/irq_cpu.h>
25 #include <asm/mipsregs.h>
26 #include <asm/reboot.h>
27 #include <asm/time.h>
28 #include <asm/traps.h>
29 #include <asm/wbflush.h>
30
31 #include <asm/dec/interrupts.h>
32 #include <asm/dec/ioasic.h>
33 #include <asm/dec/ioasic_addrs.h>
34 #include <asm/dec/ioasic_ints.h>
35 #include <asm/dec/kn01.h>
36 #include <asm/dec/kn02.h>
37 #include <asm/dec/kn02ba.h>
38 #include <asm/dec/kn02ca.h>
39 #include <asm/dec/kn03.h>
40 #include <asm/dec/kn230.h>
41
42
43 extern void dec_machine_restart(char *command);
44 extern void dec_machine_halt(void);
45 extern void dec_machine_power_off(void);
46 extern irqreturn_t dec_intr_halt(int irq, void *dev_id, struct pt_regs *regs);
47
48 extern asmlinkage void decstation_handle_int(void);
49
50 spinlock_t ioasic_ssr_lock;
51
52 volatile u32 *ioasic_base;
53 unsigned long dec_kn_slot_size;
54
55 /*
56 * IRQ routing and priority tables. Priorites are set as follows:
57 *
58 * KN01 KN230 KN02 KN02-BA KN02-CA KN03
59 *
60 * MEMORY CPU CPU CPU ASIC CPU CPU
61 * RTC CPU CPU CPU ASIC CPU CPU
62 * DMA - - - ASIC ASIC ASIC
63 * SERIAL0 CPU CPU CSR ASIC ASIC ASIC
64 * SERIAL1 - - - ASIC - ASIC
65 * SCSI CPU CPU CSR ASIC ASIC ASIC
66 * ETHERNET CPU * CSR ASIC ASIC ASIC
67 * other - - - ASIC - -
68 * TC2 - - CSR CPU ASIC ASIC
69 * TC1 - - CSR CPU ASIC ASIC
70 * TC0 - - CSR CPU ASIC ASIC
71 * other - CPU - CPU ASIC ASIC
72 * other - - - - CPU CPU
73 *
74 * * -- shared with SCSI
75 */
76
77 int dec_interrupt[DEC_NR_INTS] = {
78 [0 ... DEC_NR_INTS - 1] = -1
79 };
80 int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = {
81 { { .i = ~0 }, { .p = dec_intr_unimplemented } },
82 };
83 int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2] = {
84 { { .i = ~0 }, { .p = asic_intr_unimplemented } },
85 };
86 int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU);
87
88 static struct irqaction ioirq = {
89 .handler = no_action,
90 .name = "cascade",
91 };
92 static struct irqaction fpuirq = {
93 .handler = no_action,
94 .name = "fpu",
95 };
96
97 static struct irqaction busirq = {
98 .flags = SA_INTERRUPT,
99 .name = "bus error",
100 };
101
102 static struct irqaction haltirq = {
103 .handler = dec_intr_halt,
104 .name = "halt",
105 };
106
107
108 /*
109 * Bus error (DBE/IBE exceptions and bus interrupts) handling setup.
110 */
111 void __init dec_be_init(void)
112 {
113 switch (mips_machtype) {
114 case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */
115 busirq.flags |= SA_SHIRQ;
116 break;
117 case MACH_DS5000_200: /* DS5000/200 3max */
118 case MACH_DS5000_2X0: /* DS5000/240 3max+ */
119 case MACH_DS5900: /* DS5900 bigmax */
120 board_be_handler = dec_ecc_be_handler;
121 busirq.handler = dec_ecc_be_interrupt;
122 dec_ecc_be_init();
123 break;
124 }
125 }
126
127
128 extern void dec_time_init(void);
129 extern void dec_timer_setup(struct irqaction *);
130
131 static void __init decstation_setup(void)
132 {
133 board_be_init = dec_be_init;
134 board_time_init = dec_time_init;
135 board_timer_setup = dec_timer_setup;
136
137 wbflush_setup();
138
139 _machine_restart = dec_machine_restart;
140 _machine_halt = dec_machine_halt;
141 _machine_power_off = dec_machine_power_off;
142 }
143
144 early_initcall(decstation_setup);
145
146 /*
147 * Machine-specific initialisation for KN01, aka DS2100 (aka Pmin)
148 * or DS3100 (aka Pmax).
149 */
150 static int kn01_interrupt[DEC_NR_INTS] __initdata = {
151 [DEC_IRQ_CASCADE] = -1,
152 [DEC_IRQ_AB_RECV] = -1,
153 [DEC_IRQ_AB_XMIT] = -1,
154 [DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11),
155 [DEC_IRQ_ASC] = -1,
156 [DEC_IRQ_FLOPPY] = -1,
157 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
158 [DEC_IRQ_HALT] = -1,
159 [DEC_IRQ_ISDN] = -1,
160 [DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE),
161 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS),
162 [DEC_IRQ_PSU] = -1,
163 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC),
164 [DEC_IRQ_SCC0] = -1,
165 [DEC_IRQ_SCC1] = -1,
166 [DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII),
167 [DEC_IRQ_TC0] = -1,
168 [DEC_IRQ_TC1] = -1,
169 [DEC_IRQ_TC2] = -1,
170 [DEC_IRQ_TIMER] = -1,
171 [DEC_IRQ_VIDEO] = DEC_CPU_IRQ_NR(KN01_CPU_INR_VIDEO),
172 [DEC_IRQ_ASC_MERR] = -1,
173 [DEC_IRQ_ASC_ERR] = -1,
174 [DEC_IRQ_ASC_DMA] = -1,
175 [DEC_IRQ_FLOPPY_ERR] = -1,
176 [DEC_IRQ_ISDN_ERR] = -1,
177 [DEC_IRQ_ISDN_RXDMA] = -1,
178 [DEC_IRQ_ISDN_TXDMA] = -1,
179 [DEC_IRQ_LANCE_MERR] = -1,
180 [DEC_IRQ_SCC0A_RXERR] = -1,
181 [DEC_IRQ_SCC0A_RXDMA] = -1,
182 [DEC_IRQ_SCC0A_TXERR] = -1,
183 [DEC_IRQ_SCC0A_TXDMA] = -1,
184 [DEC_IRQ_AB_RXERR] = -1,
185 [DEC_IRQ_AB_RXDMA] = -1,
186 [DEC_IRQ_AB_TXERR] = -1,
187 [DEC_IRQ_AB_TXDMA] = -1,
188 [DEC_IRQ_SCC1A_RXERR] = -1,
189 [DEC_IRQ_SCC1A_RXDMA] = -1,
190 [DEC_IRQ_SCC1A_TXERR] = -1,
191 [DEC_IRQ_SCC1A_TXDMA] = -1,
192 };
193
194 static int_ptr kn01_cpu_mask_nr_tbl[][2] __initdata = {
195 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_BUS) },
196 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS) } },
197 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_RTC) },
198 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC) } },
199 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_DZ11) },
200 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11) } },
201 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_SII) },
202 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII) } },
203 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_LANCE) },
204 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE) } },
205 { { .i = DEC_CPU_IRQ_ALL },
206 { .p = cpu_all_int } },
207 };
208
209 void __init dec_init_kn01(void)
210 {
211 /* IRQ routing. */
212 memcpy(&dec_interrupt, &kn01_interrupt,
213 sizeof(kn01_interrupt));
214
215 /* CPU IRQ priorities. */
216 memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl,
217 sizeof(kn01_cpu_mask_nr_tbl));
218
219 mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
220
221 } /* dec_init_kn01 */
222
223
224 /*
225 * Machine-specific initialisation for KN230, aka DS5100, aka MIPSmate.
226 */
227 static int kn230_interrupt[DEC_NR_INTS] __initdata = {
228 [DEC_IRQ_CASCADE] = -1,
229 [DEC_IRQ_AB_RECV] = -1,
230 [DEC_IRQ_AB_XMIT] = -1,
231 [DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11),
232 [DEC_IRQ_ASC] = -1,
233 [DEC_IRQ_FLOPPY] = -1,
234 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
235 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN230_CPU_INR_HALT),
236 [DEC_IRQ_ISDN] = -1,
237 [DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN230_CPU_INR_LANCE),
238 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS),
239 [DEC_IRQ_PSU] = -1,
240 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC),
241 [DEC_IRQ_SCC0] = -1,
242 [DEC_IRQ_SCC1] = -1,
243 [DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII),
244 [DEC_IRQ_TC0] = -1,
245 [DEC_IRQ_TC1] = -1,
246 [DEC_IRQ_TC2] = -1,
247 [DEC_IRQ_TIMER] = -1,
248 [DEC_IRQ_VIDEO] = -1,
249 [DEC_IRQ_ASC_MERR] = -1,
250 [DEC_IRQ_ASC_ERR] = -1,
251 [DEC_IRQ_ASC_DMA] = -1,
252 [DEC_IRQ_FLOPPY_ERR] = -1,
253 [DEC_IRQ_ISDN_ERR] = -1,
254 [DEC_IRQ_ISDN_RXDMA] = -1,
255 [DEC_IRQ_ISDN_TXDMA] = -1,
256 [DEC_IRQ_LANCE_MERR] = -1,
257 [DEC_IRQ_SCC0A_RXERR] = -1,
258 [DEC_IRQ_SCC0A_RXDMA] = -1,
259 [DEC_IRQ_SCC0A_TXERR] = -1,
260 [DEC_IRQ_SCC0A_TXDMA] = -1,
261 [DEC_IRQ_AB_RXERR] = -1,
262 [DEC_IRQ_AB_RXDMA] = -1,
263 [DEC_IRQ_AB_TXERR] = -1,
264 [DEC_IRQ_AB_TXDMA] = -1,
265 [DEC_IRQ_SCC1A_RXERR] = -1,
266 [DEC_IRQ_SCC1A_RXDMA] = -1,
267 [DEC_IRQ_SCC1A_TXERR] = -1,
268 [DEC_IRQ_SCC1A_TXDMA] = -1,
269 };
270
271 static int_ptr kn230_cpu_mask_nr_tbl[][2] __initdata = {
272 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_BUS) },
273 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS) } },
274 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_RTC) },
275 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC) } },
276 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_DZ11) },
277 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11) } },
278 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_SII) },
279 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII) } },
280 { { .i = DEC_CPU_IRQ_ALL },
281 { .p = cpu_all_int } },
282 };
283
284 void __init dec_init_kn230(void)
285 {
286 /* IRQ routing. */
287 memcpy(&dec_interrupt, &kn230_interrupt,
288 sizeof(kn230_interrupt));
289
290 /* CPU IRQ priorities. */
291 memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl,
292 sizeof(kn230_cpu_mask_nr_tbl));
293
294 mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
295
296 } /* dec_init_kn230 */
297
298
299 /*
300 * Machine-specific initialisation for KN02, aka DS5000/200, aka 3max.
301 */
302 static int kn02_interrupt[DEC_NR_INTS] __initdata = {
303 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02_CPU_INR_CASCADE),
304 [DEC_IRQ_AB_RECV] = -1,
305 [DEC_IRQ_AB_XMIT] = -1,
306 [DEC_IRQ_DZ11] = KN02_IRQ_NR(KN02_CSR_INR_DZ11),
307 [DEC_IRQ_ASC] = KN02_IRQ_NR(KN02_CSR_INR_ASC),
308 [DEC_IRQ_FLOPPY] = -1,
309 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
310 [DEC_IRQ_HALT] = -1,
311 [DEC_IRQ_ISDN] = -1,
312 [DEC_IRQ_LANCE] = KN02_IRQ_NR(KN02_CSR_INR_LANCE),
313 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS),
314 [DEC_IRQ_PSU] = -1,
315 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC),
316 [DEC_IRQ_SCC0] = -1,
317 [DEC_IRQ_SCC1] = -1,
318 [DEC_IRQ_SII] = -1,
319 [DEC_IRQ_TC0] = KN02_IRQ_NR(KN02_CSR_INR_TC0),
320 [DEC_IRQ_TC1] = KN02_IRQ_NR(KN02_CSR_INR_TC1),
321 [DEC_IRQ_TC2] = KN02_IRQ_NR(KN02_CSR_INR_TC2),
322 [DEC_IRQ_TIMER] = -1,
323 [DEC_IRQ_VIDEO] = -1,
324 [DEC_IRQ_ASC_MERR] = -1,
325 [DEC_IRQ_ASC_ERR] = -1,
326 [DEC_IRQ_ASC_DMA] = -1,
327 [DEC_IRQ_FLOPPY_ERR] = -1,
328 [DEC_IRQ_ISDN_ERR] = -1,
329 [DEC_IRQ_ISDN_RXDMA] = -1,
330 [DEC_IRQ_ISDN_TXDMA] = -1,
331 [DEC_IRQ_LANCE_MERR] = -1,
332 [DEC_IRQ_SCC0A_RXERR] = -1,
333 [DEC_IRQ_SCC0A_RXDMA] = -1,
334 [DEC_IRQ_SCC0A_TXERR] = -1,
335 [DEC_IRQ_SCC0A_TXDMA] = -1,
336 [DEC_IRQ_AB_RXERR] = -1,
337 [DEC_IRQ_AB_RXDMA] = -1,
338 [DEC_IRQ_AB_TXERR] = -1,
339 [DEC_IRQ_AB_TXDMA] = -1,
340 [DEC_IRQ_SCC1A_RXERR] = -1,
341 [DEC_IRQ_SCC1A_RXDMA] = -1,
342 [DEC_IRQ_SCC1A_TXERR] = -1,
343 [DEC_IRQ_SCC1A_TXDMA] = -1,
344 };
345
346 static int_ptr kn02_cpu_mask_nr_tbl[][2] __initdata = {
347 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_BUS) },
348 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS) } },
349 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_RTC) },
350 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC) } },
351 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_CASCADE) },
352 { .p = kn02_io_int } },
353 { { .i = DEC_CPU_IRQ_ALL },
354 { .p = cpu_all_int } },
355 };
356
357 static int_ptr kn02_asic_mask_nr_tbl[][2] __initdata = {
358 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_DZ11) },
359 { .i = KN02_IRQ_NR(KN02_CSR_INR_DZ11) } },
360 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_ASC) },
361 { .i = KN02_IRQ_NR(KN02_CSR_INR_ASC) } },
362 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_LANCE) },
363 { .i = KN02_IRQ_NR(KN02_CSR_INR_LANCE) } },
364 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC2) },
365 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC2) } },
366 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC1) },
367 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC1) } },
368 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC0) },
369 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC0) } },
370 { { .i = KN02_IRQ_ALL },
371 { .p = kn02_all_int } },
372 };
373
374 void __init dec_init_kn02(void)
375 {
376 /* IRQ routing. */
377 memcpy(&dec_interrupt, &kn02_interrupt,
378 sizeof(kn02_interrupt));
379
380 /* CPU IRQ priorities. */
381 memcpy(&cpu_mask_nr_tbl, &kn02_cpu_mask_nr_tbl,
382 sizeof(kn02_cpu_mask_nr_tbl));
383
384 /* KN02 CSR IRQ priorities. */
385 memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl,
386 sizeof(kn02_asic_mask_nr_tbl));
387
388 mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
389 init_kn02_irqs(KN02_IRQ_BASE);
390
391 } /* dec_init_kn02 */
392
393
394 /*
395 * Machine-specific initialisation for KN02-BA, aka DS5000/1xx
396 * (xx = 20, 25, 33), aka 3min. Also applies to KN04(-BA), aka
397 * DS5000/150, aka 4min.
398 */
399 static int kn02ba_interrupt[DEC_NR_INTS] __initdata = {
400 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_CASCADE),
401 [DEC_IRQ_AB_RECV] = -1,
402 [DEC_IRQ_AB_XMIT] = -1,
403 [DEC_IRQ_DZ11] = -1,
404 [DEC_IRQ_ASC] = IO_IRQ_NR(KN02BA_IO_INR_ASC),
405 [DEC_IRQ_FLOPPY] = -1,
406 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
407 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_HALT),
408 [DEC_IRQ_ISDN] = -1,
409 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN02BA_IO_INR_LANCE),
410 [DEC_IRQ_BUS] = IO_IRQ_NR(KN02BA_IO_INR_BUS),
411 [DEC_IRQ_PSU] = IO_IRQ_NR(KN02BA_IO_INR_PSU),
412 [DEC_IRQ_RTC] = IO_IRQ_NR(KN02BA_IO_INR_RTC),
413 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN02BA_IO_INR_SCC0),
414 [DEC_IRQ_SCC1] = IO_IRQ_NR(KN02BA_IO_INR_SCC1),
415 [DEC_IRQ_SII] = -1,
416 [DEC_IRQ_TC0] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0),
417 [DEC_IRQ_TC1] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1),
418 [DEC_IRQ_TC2] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2),
419 [DEC_IRQ_TIMER] = -1,
420 [DEC_IRQ_VIDEO] = -1,
421 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR),
422 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR),
423 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA),
424 [DEC_IRQ_FLOPPY_ERR] = -1,
425 [DEC_IRQ_ISDN_ERR] = -1,
426 [DEC_IRQ_ISDN_RXDMA] = -1,
427 [DEC_IRQ_ISDN_TXDMA] = -1,
428 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR),
429 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
430 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
431 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
432 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
433 [DEC_IRQ_AB_RXERR] = -1,
434 [DEC_IRQ_AB_RXDMA] = -1,
435 [DEC_IRQ_AB_TXERR] = -1,
436 [DEC_IRQ_AB_TXDMA] = -1,
437 [DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
438 [DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
439 [DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
440 [DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
441 };
442
443 static int_ptr kn02ba_cpu_mask_nr_tbl[][2] __initdata = {
444 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_CASCADE) },
445 { .p = kn02xa_io_int } },
446 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC2) },
447 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2) } },
448 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC1) },
449 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1) } },
450 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC0) },
451 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0) } },
452 { { .i = DEC_CPU_IRQ_ALL },
453 { .p = cpu_all_int } },
454 };
455
456 static int_ptr kn02ba_asic_mask_nr_tbl[][2] __initdata = {
457 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_BUS) },
458 { .i = IO_IRQ_NR(KN02BA_IO_INR_BUS) } },
459 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_RTC) },
460 { .i = IO_IRQ_NR(KN02BA_IO_INR_RTC) } },
461 { { .i = IO_IRQ_DMA },
462 { .p = asic_dma_int } },
463 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC0) },
464 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC0) } },
465 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC1) },
466 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC1) } },
467 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_ASC) },
468 { .i = IO_IRQ_NR(KN02BA_IO_INR_ASC) } },
469 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_LANCE) },
470 { .i = IO_IRQ_NR(KN02BA_IO_INR_LANCE) } },
471 { { .i = IO_IRQ_ALL },
472 { .p = asic_all_int } },
473 };
474
475 void __init dec_init_kn02ba(void)
476 {
477 /* IRQ routing. */
478 memcpy(&dec_interrupt, &kn02ba_interrupt,
479 sizeof(kn02ba_interrupt));
480
481 /* CPU IRQ priorities. */
482 memcpy(&cpu_mask_nr_tbl, &kn02ba_cpu_mask_nr_tbl,
483 sizeof(kn02ba_cpu_mask_nr_tbl));
484
485 /* I/O ASIC IRQ priorities. */
486 memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl,
487 sizeof(kn02ba_asic_mask_nr_tbl));
488
489 mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
490 init_ioasic_irqs(IO_IRQ_BASE);
491
492 } /* dec_init_kn02ba */
493
494
495 /*
496 * Machine-specific initialisation for KN02-CA, aka DS5000/xx,
497 * (xx = 20, 25, 33), aka MAXine. Also applies to KN04(-CA), aka
498 * DS5000/50, aka 4MAXine.
499 */
500 static int kn02ca_interrupt[DEC_NR_INTS] __initdata = {
501 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_CASCADE),
502 [DEC_IRQ_AB_RECV] = IO_IRQ_NR(KN02CA_IO_INR_AB_RECV),
503 [DEC_IRQ_AB_XMIT] = IO_IRQ_NR(KN02CA_IO_INR_AB_XMIT),
504 [DEC_IRQ_DZ11] = -1,
505 [DEC_IRQ_ASC] = IO_IRQ_NR(KN02CA_IO_INR_ASC),
506 [DEC_IRQ_FLOPPY] = IO_IRQ_NR(KN02CA_IO_INR_FLOPPY),
507 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
508 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_HALT),
509 [DEC_IRQ_ISDN] = IO_IRQ_NR(KN02CA_IO_INR_ISDN),
510 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN02CA_IO_INR_LANCE),
511 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS),
512 [DEC_IRQ_PSU] = -1,
513 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC),
514 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN02CA_IO_INR_SCC0),
515 [DEC_IRQ_SCC1] = -1,
516 [DEC_IRQ_SII] = -1,
517 [DEC_IRQ_TC0] = IO_IRQ_NR(KN02CA_IO_INR_TC0),
518 [DEC_IRQ_TC1] = IO_IRQ_NR(KN02CA_IO_INR_TC1),
519 [DEC_IRQ_TC2] = -1,
520 [DEC_IRQ_TIMER] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_TIMER),
521 [DEC_IRQ_VIDEO] = IO_IRQ_NR(KN02CA_IO_INR_VIDEO),
522 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR),
523 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR),
524 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA),
525 [DEC_IRQ_FLOPPY_ERR] = IO_IRQ_NR(IO_INR_FLOPPY_ERR),
526 [DEC_IRQ_ISDN_ERR] = IO_IRQ_NR(IO_INR_ISDN_ERR),
527 [DEC_IRQ_ISDN_RXDMA] = IO_IRQ_NR(IO_INR_ISDN_RXDMA),
528 [DEC_IRQ_ISDN_TXDMA] = IO_IRQ_NR(IO_INR_ISDN_TXDMA),
529 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR),
530 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
531 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
532 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
533 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
534 [DEC_IRQ_AB_RXERR] = IO_IRQ_NR(IO_INR_AB_RXERR),
535 [DEC_IRQ_AB_RXDMA] = IO_IRQ_NR(IO_INR_AB_RXDMA),
536 [DEC_IRQ_AB_TXERR] = IO_IRQ_NR(IO_INR_AB_TXERR),
537 [DEC_IRQ_AB_TXDMA] = IO_IRQ_NR(IO_INR_AB_TXDMA),
538 [DEC_IRQ_SCC1A_RXERR] = -1,
539 [DEC_IRQ_SCC1A_RXDMA] = -1,
540 [DEC_IRQ_SCC1A_TXERR] = -1,
541 [DEC_IRQ_SCC1A_TXDMA] = -1,
542 };
543
544 static int_ptr kn02ca_cpu_mask_nr_tbl[][2] __initdata = {
545 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_BUS) },
546 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS) } },
547 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_RTC) },
548 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC) } },
549 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_CASCADE) },
550 { .p = kn02xa_io_int } },
551 { { .i = DEC_CPU_IRQ_ALL },
552 { .p = cpu_all_int } },
553 };
554
555 static int_ptr kn02ca_asic_mask_nr_tbl[][2] __initdata = {
556 { { .i = IO_IRQ_DMA },
557 { .p = asic_dma_int } },
558 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_SCC0) },
559 { .i = IO_IRQ_NR(KN02CA_IO_INR_SCC0) } },
560 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_ASC) },
561 { .i = IO_IRQ_NR(KN02CA_IO_INR_ASC) } },
562 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_LANCE) },
563 { .i = IO_IRQ_NR(KN02CA_IO_INR_LANCE) } },
564 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC1) },
565 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC1) } },
566 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC0) },
567 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC0) } },
568 { { .i = IO_IRQ_ALL },
569 { .p = asic_all_int } },
570 };
571
572 void __init dec_init_kn02ca(void)
573 {
574 /* IRQ routing. */
575 memcpy(&dec_interrupt, &kn02ca_interrupt,
576 sizeof(kn02ca_interrupt));
577
578 /* CPU IRQ priorities. */
579 memcpy(&cpu_mask_nr_tbl, &kn02ca_cpu_mask_nr_tbl,
580 sizeof(kn02ca_cpu_mask_nr_tbl));
581
582 /* I/O ASIC IRQ priorities. */
583 memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl,
584 sizeof(kn02ca_asic_mask_nr_tbl));
585
586 mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
587 init_ioasic_irqs(IO_IRQ_BASE);
588
589 } /* dec_init_kn02ca */
590
591
592 /*
593 * Machine-specific initialisation for KN03, aka DS5000/240,
594 * aka 3max+ and DS5900, aka BIGmax. Also applies to KN05, aka
595 * DS5000/260, aka 4max+ and DS5900/260.
596 */
597 static int kn03_interrupt[DEC_NR_INTS] __initdata = {
598 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN03_CPU_INR_CASCADE),
599 [DEC_IRQ_AB_RECV] = -1,
600 [DEC_IRQ_AB_XMIT] = -1,
601 [DEC_IRQ_DZ11] = -1,
602 [DEC_IRQ_ASC] = IO_IRQ_NR(KN03_IO_INR_ASC),
603 [DEC_IRQ_FLOPPY] = -1,
604 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
605 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN03_CPU_INR_HALT),
606 [DEC_IRQ_ISDN] = -1,
607 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN03_IO_INR_LANCE),
608 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS),
609 [DEC_IRQ_PSU] = IO_IRQ_NR(KN03_IO_INR_PSU),
610 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC),
611 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN03_IO_INR_SCC0),
612 [DEC_IRQ_SCC1] = IO_IRQ_NR(KN03_IO_INR_SCC1),
613 [DEC_IRQ_SII] = -1,
614 [DEC_IRQ_TC0] = IO_IRQ_NR(KN03_IO_INR_TC0),
615 [DEC_IRQ_TC1] = IO_IRQ_NR(KN03_IO_INR_TC1),
616 [DEC_IRQ_TC2] = IO_IRQ_NR(KN03_IO_INR_TC2),
617 [DEC_IRQ_TIMER] = -1,
618 [DEC_IRQ_VIDEO] = -1,
619 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR),
620 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR),
621 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA),
622 [DEC_IRQ_FLOPPY_ERR] = -1,
623 [DEC_IRQ_ISDN_ERR] = -1,
624 [DEC_IRQ_ISDN_RXDMA] = -1,
625 [DEC_IRQ_ISDN_TXDMA] = -1,
626 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR),
627 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
628 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
629 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
630 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
631 [DEC_IRQ_AB_RXERR] = -1,
632 [DEC_IRQ_AB_RXDMA] = -1,
633 [DEC_IRQ_AB_TXERR] = -1,
634 [DEC_IRQ_AB_TXDMA] = -1,
635 [DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
636 [DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
637 [DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
638 [DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
639 };
640
641 static int_ptr kn03_cpu_mask_nr_tbl[][2] __initdata = {
642 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_BUS) },
643 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS) } },
644 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_RTC) },
645 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC) } },
646 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_CASCADE) },
647 { .p = kn03_io_int } },
648 { { .i = DEC_CPU_IRQ_ALL },
649 { .p = cpu_all_int } },
650 };
651
652 static int_ptr kn03_asic_mask_nr_tbl[][2] __initdata = {
653 { { .i = IO_IRQ_DMA },
654 { .p = asic_dma_int } },
655 { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC0) },
656 { .i = IO_IRQ_NR(KN03_IO_INR_SCC0) } },
657 { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC1) },
658 { .i = IO_IRQ_NR(KN03_IO_INR_SCC1) } },
659 { { .i = IO_IRQ_MASK(KN03_IO_INR_ASC) },
660 { .i = IO_IRQ_NR(KN03_IO_INR_ASC) } },
661 { { .i = IO_IRQ_MASK(KN03_IO_INR_LANCE) },
662 { .i = IO_IRQ_NR(KN03_IO_INR_LANCE) } },
663 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC2) },
664 { .i = IO_IRQ_NR(KN03_IO_INR_TC2) } },
665 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC1) },
666 { .i = IO_IRQ_NR(KN03_IO_INR_TC1) } },
667 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC0) },
668 { .i = IO_IRQ_NR(KN03_IO_INR_TC0) } },
669 { { .i = IO_IRQ_ALL },
670 { .p = asic_all_int } },
671 };
672
673 void __init dec_init_kn03(void)
674 {
675 /* IRQ routing. */
676 memcpy(&dec_interrupt, &kn03_interrupt,
677 sizeof(kn03_interrupt));
678
679 /* CPU IRQ priorities. */
680 memcpy(&cpu_mask_nr_tbl, &kn03_cpu_mask_nr_tbl,
681 sizeof(kn03_cpu_mask_nr_tbl));
682
683 /* I/O ASIC IRQ priorities. */
684 memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl,
685 sizeof(kn03_asic_mask_nr_tbl));
686
687 mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
688 init_ioasic_irqs(IO_IRQ_BASE);
689
690 } /* dec_init_kn03 */
691
692
693 void __init arch_init_irq(void)
694 {
695 switch (mips_machtype) {
696 case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */
697 dec_init_kn01();
698 break;
699 case MACH_DS5100: /* DS5100 MIPSmate */
700 dec_init_kn230();
701 break;
702 case MACH_DS5000_200: /* DS5000/200 3max */
703 dec_init_kn02();
704 break;
705 case MACH_DS5000_1XX: /* DS5000/1xx 3min */
706 dec_init_kn02ba();
707 break;
708 case MACH_DS5000_2X0: /* DS5000/240 3max+ */
709 case MACH_DS5900: /* DS5900 bigmax */
710 dec_init_kn03();
711 break;
712 case MACH_DS5000_XX: /* Personal DS5000/xx */
713 dec_init_kn02ca();
714 break;
715 case MACH_DS5800: /* DS5800 Isis */
716 panic("Don't know how to set this up!");
717 break;
718 case MACH_DS5400: /* DS5400 MIPSfair */
719 panic("Don't know how to set this up!");
720 break;
721 case MACH_DS5500: /* DS5500 MIPSfair-2 */
722 panic("Don't know how to set this up!");
723 break;
724 }
725 set_except_vector(0, decstation_handle_int);
726
727 /* Free the FPU interrupt if the exception is present. */
728 if (!cpu_has_nofpuex) {
729 cpu_fpu_mask = 0;
730 dec_interrupt[DEC_IRQ_FPU] = -1;
731 }
732
733 /* Register board interrupts: FPU and cascade. */
734 if (dec_interrupt[DEC_IRQ_FPU] >= 0)
735 setup_irq(dec_interrupt[DEC_IRQ_FPU], &fpuirq);
736 if (dec_interrupt[DEC_IRQ_CASCADE] >= 0)
737 setup_irq(dec_interrupt[DEC_IRQ_CASCADE], &ioirq);
738
739 /* Register the bus error interrupt. */
740 if (dec_interrupt[DEC_IRQ_BUS] >= 0 && busirq.handler)
741 setup_irq(dec_interrupt[DEC_IRQ_BUS], &busirq);
742
743 /* Register the HALT interrupt. */
744 if (dec_interrupt[DEC_IRQ_HALT] >= 0)
745 setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq);
746 }
747
748 EXPORT_SYMBOL(ioasic_base);
749 EXPORT_SYMBOL(dec_kn_slot_size);
750 EXPORT_SYMBOL(dec_interrupt);
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