arch/mips/gt64120/momenco_ocelot/setup.c

   1 /*
   2  * setup.c
   3  *
   4  * BRIEF MODULE DESCRIPTION
   5  * Momentum Computer Ocelot (CP7000) - board dependent boot routines
   6  *
   7  * Copyright (C) 1996, 1997, 2001  Ralf Baechle
   8  * Copyright (C) 2000 RidgeRun, Inc.
   9  * Copyright (C) 2001 Red Hat, Inc.
  10  * Copyright (C) 2002 Momentum Computer
  11  *
  12  * Author: RidgeRun, Inc.
  13  *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
  14  *
  15  * Copyright 2001 MontaVista Software Inc.
  16  * Author: jsun@mvista.com or jsun@junsun.net
  17  *
  18  *  This program is free software; you can redistribute  it and/or modify it
  19  *  under  the terms of  the GNU General  Public License as published by the
  20  *  Free Software Foundation;  either version 2 of the  License, or (at your
  21  *  option) any later version.
  22  *
  23  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  24  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  25  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  26  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  27  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  28  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  29  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  30  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  31  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  32  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  *
  34  *  You should have received a copy of the  GNU General Public License along
  35  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  36  *  675 Mass Ave, Cambridge, MA 02139, USA.
  37  *
  38  */
  39 #include <linux/init.h>
  40 #include <linux/kernel.h>
  41 #include <linux/types.h>
  42 #include <linux/mm.h>
  43 #include <linux/swap.h>
  44 #include <linux/ioport.h>
  45 #include <linux/sched.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/pci.h>
  48 #include <linux/timex.h>
  49 #include <linux/vmalloc.h>
  50 #include <asm/time.h>
  51 #include <asm/bootinfo.h>
  52 #include <asm/page.h>
  53 #include <asm/io.h>
  54 #include <asm/irq.h>
  55 #include <asm/pci.h>
  56 #include <asm/processor.h>
  57 #include <asm/ptrace.h>
  58 #include <asm/reboot.h>
  59 #include <asm/traps.h>
  60 #include <linux/bootmem.h>
  61 #include <linux/initrd.h>
  62 #include <asm/gt64120.h>
  63 #include "ocelot_pld.h"
  64
  65 unsigned long gt64120_base = KSEG1ADDR(GT_DEF_BASE);
  66
  67 /* These functions are used for rebooting or halting the machine*/
  68 extern void momenco_ocelot_restart(char *command);
  69 extern void momenco_ocelot_halt(void);
  70 extern void momenco_ocelot_power_off(void);
  71
  72 extern void gt64120_time_init(void);
  73 extern void momenco_ocelot_irq_setup(void);
  74
  75 static char reset_reason;
  76
  77 #define ENTRYLO(x) ((pte_val(pfn_pte((x) >> PAGE_SHIFT, PAGE_KERNEL_UNCACHED)) >> 6)|1)
  78
  79 static void __init setup_l3cache(unsigned long size);
  80
  81 /* setup code for a handoff from a version 1 PMON 2000 PROM */
  82 void PMON_v1_setup()
  83 {
  84         /* A wired TLB entry for the GT64120A and the serial port. The
  85            GT64120A is going to be hit on every IRQ anyway - there's
  86            absolutely no point in letting it be a random TLB entry, as
  87            it'll just cause needless churning of the TLB. And we use
  88            the other half for the serial port, which is just a PITA
  89            otherwise :)
  90
  91                 Device                  Physical        Virtual
  92                 GT64120 Internal Regs   0x24000000      0xe0000000
  93                 UARTs (CS2)             0x2d000000      0xe0001000
  94         */
  95         add_wired_entry(ENTRYLO(0x24000000), ENTRYLO(0x2D000000), 0xe0000000, PM_4K);
  96
  97         /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
  98            in the CS[012] region. We can't use ioremap() yet. The NVRAM
  99            is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
 100
 101                 Ocelot PLD (CS0)        0x2c000000      0xe0020000
 102                 NVRAM                   0x2c800000      0xe0030000
 103         */
 104
 105         add_temporary_entry(ENTRYLO(0x2C000000), ENTRYLO(0x2d000000), 0xe0020000, PM_64K);
 106
 107         /* Relocate the CS3/BootCS region */
 108         GT_WRITE(GT_CS3BOOTLD_OFS, 0x2f000000 >> 21);
 109
 110         /* Relocate CS[012] */
 111         GT_WRITE(GT_CS20LD_OFS, 0x2c000000 >> 21);
 112
 113         /* Relocate the GT64120A itself... */
 114         GT_WRITE(GT_ISD_OFS, 0x24000000 >> 21);
 115         mb();
 116         gt64120_base = 0xe0000000;
 117
 118         /* ...and the PCI0 view of it. */
 119         GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000020);
 120         GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000000);
 121         GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000024);
 122         GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000001);
 123 }
 124
 125 /* setup code for a handoff from a version 2 PMON 2000 PROM */
 126 void PMON_v2_setup()
 127 {
 128         /* A wired TLB entry for the GT64120A and the serial port. The
 129            GT64120A is going to be hit on every IRQ anyway - there's
 130            absolutely no point in letting it be a random TLB entry, as
 131            it'll just cause needless churning of the TLB. And we use
 132            the other half for the serial port, which is just a PITA
 133            otherwise :)
 134
 135                 Device                  Physical        Virtual
 136                 GT64120 Internal Regs   0xf4000000      0xe0000000
 137                 UARTs (CS2)             0xfd000000      0xe0001000
 138         */
 139         add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xfD000000), 0xe0000000, PM_4K);
 140
 141         /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
 142            in the CS[012] region. We can't use ioremap() yet. The NVRAM
 143            is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
 144
 145                 Ocelot PLD (CS0)        0xfc000000      0xe0020000
 146                 NVRAM                   0xfc800000      0xe0030000
 147         */
 148         add_temporary_entry(ENTRYLO(0xfC000000), ENTRYLO(0xfd000000), 0xe0020000, PM_64K);
 149
 150         gt64120_base = 0xe0000000;
 151 }
 152
 153 static void __init momenco_ocelot_setup(void)
 154 {
 155         void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache);
 156         unsigned int tmpword;
 157
 158         board_time_init = gt64120_time_init;
 159
 160         _machine_restart = momenco_ocelot_restart;
 161         _machine_halt = momenco_ocelot_halt;
 162         _machine_power_off = momenco_ocelot_power_off;
 163
 164         /*
 165          * initrd_start = (ulong)ocelot_initrd_start;
 166          * initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size;
 167          * initrd_below_start_ok = 1;
 168          */
 169
 170         /* do handoff reconfiguration */
 171         if (gt64120_base == KSEG1ADDR(GT_DEF_BASE))
 172                 PMON_v1_setup();
 173         else
 174                 PMON_v2_setup();
 175
 176         /* Turn off the Bit-Error LED */
 177         OCELOT_PLD_WRITE(0x80, INTCLR);
 178
 179         /* Relocate all the PCI1 stuff, not that we use it */
 180         GT_WRITE(GT_PCI1IOLD_OFS, 0x30000000 >> 21);
 181         GT_WRITE(GT_PCI1M0LD_OFS, 0x32000000 >> 21);
 182         GT_WRITE(GT_PCI1M1LD_OFS, 0x34000000 >> 21);
 183
 184         /* Relocate PCI0 I/O and Mem0 */
 185         GT_WRITE(GT_PCI0IOLD_OFS, 0x20000000 >> 21);
 186         GT_WRITE(GT_PCI0M0LD_OFS, 0x22000000 >> 21);
 187
 188         /* Relocate PCI0 Mem1 */
 189         GT_WRITE(GT_PCI0M1LD_OFS, 0x36000000 >> 21);
 190
 191         /* For the initial programming, we assume 512MB configuration */
 192         /* Relocate the CPU's view of the RAM... */
 193         GT_WRITE(GT_SCS10LD_OFS, 0);
 194         GT_WRITE(GT_SCS10HD_OFS, 0x0fe00000 >> 21);
 195         GT_WRITE(GT_SCS32LD_OFS, 0x10000000 >> 21);
 196         GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21);
 197
 198         GT_WRITE(GT_SCS1LD_OFS, 0xff);
 199         GT_WRITE(GT_SCS1HD_OFS, 0x00);
 200         GT_WRITE(GT_SCS0LD_OFS, 0);
 201         GT_WRITE(GT_SCS0HD_OFS, 0xff);
 202         GT_WRITE(GT_SCS3LD_OFS, 0xff);
 203         GT_WRITE(GT_SCS3HD_OFS, 0x00);
 204         GT_WRITE(GT_SCS2LD_OFS, 0);
 205         GT_WRITE(GT_SCS2HD_OFS, 0xff);
 206
 207         /* ...and the PCI0 view of it. */
 208         GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000010);
 209         GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x00000000);
 210         GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
 211         GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x10000000);
 212         GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000);
 213         GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000);
 214
 215         tmpword = OCELOT_PLD_READ(BOARDREV);
 216         if (tmpword < 26)
 217                 printk("Momenco Ocelot: Board Assembly Rev. %c\n", 'A'+tmpword);
 218         else
 219                 printk("Momenco Ocelot: Board Assembly Revision #0x%x\n", tmpword);
 220
 221         tmpword = OCELOT_PLD_READ(PLD1_ID);
 222         printk("PLD 1 ID: %d.%d\n", tmpword>>4, tmpword&15);
 223         tmpword = OCELOT_PLD_READ(PLD2_ID);
 224         printk("PLD 2 ID: %d.%d\n", tmpword>>4, tmpword&15);
 225         tmpword = OCELOT_PLD_READ(RESET_STATUS);
 226         printk("Reset reason: 0x%x\n", tmpword);
 227         reset_reason = tmpword;
 228         OCELOT_PLD_WRITE(0xff, RESET_STATUS);
 229
 230         tmpword = OCELOT_PLD_READ(BOARD_STATUS);
 231         printk("Board Status register: 0x%02x\n", tmpword);
 232         printk("  - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
 233         printk("  - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
 234         printk("  - Tulip PHY %s connected\n", (tmpword&0x10)?"is":"not");
 235         printk("  - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
 236         printk("  - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
 237
 238         if (tmpword&12)
 239                 l3func((1<<(((tmpword&12) >> 2)+20)));
 240
 241         switch(tmpword &3) {
 242         case 3:
 243                 /* 512MiB */
 244                 /* Decoders are allready set -- just add the
 245                  * appropriate region */
 246                 add_memory_region( 0x40<<20,  0xC0<<20, BOOT_MEM_RAM);
 247                 add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM);
 248                 break;
 249         case 2:
 250                 /* 256MiB -- two banks of 128MiB */
 251                 GT_WRITE(GT_SCS10HD_OFS, 0x07e00000 >> 21);
 252                 GT_WRITE(GT_SCS32LD_OFS, 0x08000000 >> 21);
 253                 GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21);
 254
 255                 GT_WRITE(GT_SCS0HD_OFS, 0x7f);
 256                 GT_WRITE(GT_SCS2LD_OFS, 0x80);
 257                 GT_WRITE(GT_SCS2HD_OFS, 0xff);
 258
 259                 /* reconfigure the PCI0 interface view of memory */
 260                 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
 261                 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x08000000);
 262                 GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000);
 263                 GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000);
 264
 265                 add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
 266                 add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM);
 267                 break;
 268         case 1:
 269                 /* 128MiB -- 64MiB per bank */
 270                 GT_WRITE(GT_SCS10HD_OFS, 0x03e00000 >> 21);
 271                 GT_WRITE(GT_SCS32LD_OFS, 0x04000000 >> 21);
 272                 GT_WRITE(GT_SCS32HD_OFS, 0x07e00000 >> 21);
 273
 274                 GT_WRITE(GT_SCS0HD_OFS, 0x3f);
 275                 GT_WRITE(GT_SCS2LD_OFS, 0x40);
 276                 GT_WRITE(GT_SCS2HD_OFS, 0x7f);
 277
 278                 /* reconfigure the PCI0 interface view of memory */
 279                 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
 280                 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000);
 281                 GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x03fff000);
 282                 GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x03fff000);
 283
 284                 /* add the appropriate region */
 285                 add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
 286                 break;
 287         case 0:
 288                 /* 64MiB */
 289                 GT_WRITE(GT_SCS10HD_OFS, 0x01e00000 >> 21);
 290                 GT_WRITE(GT_SCS32LD_OFS, 0x02000000 >> 21);
 291                 GT_WRITE(GT_SCS32HD_OFS, 0x03e00000 >> 21);
 292
 293                 GT_WRITE(GT_SCS0HD_OFS, 0x1f);
 294                 GT_WRITE(GT_SCS2LD_OFS, 0x20);
 295                 GT_WRITE(GT_SCS2HD_OFS, 0x3f);
 296
 297                 /* reconfigure the PCI0 interface view of memory */
 298                 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
 299                 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000);
 300                 GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x01fff000);
 301                 GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x01fff000);
 302
 303                 break;
 304         }
 305
 306         /* Fix up the DiskOnChip mapping */
 307         GT_WRITE(GT_DEV_B3_OFS, 0xfef73);
 308 }
 309
 310 early_initcall(momenco_ocelot_setup);
 311
 312 extern int rm7k_tcache_enabled;
 313 /*
 314  * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache()
 315  */
 316 #define Page_Invalidate_T 0x16
 317 static void __init setup_l3cache(unsigned long size)
 318 {
 319         int register i;
 320         unsigned long tmp;
 321
 322         printk("Enabling L3 cache...");
 323
 324         /* Enable the L3 cache in the GT64120A's CPU Configuration register */
 325         tmp = GT_READ(GT_CPU_OFS);
 326         GT_WRITE(GT_CPU_OFS, tmp | (1<<14));
 327
 328         /* Enable the L3 cache in the CPU */
 329         set_c0_config(1<<12 /* CONF_TE */);
 330
 331         /* Clear the cache */
 332         write_c0_taglo(0);
 333         write_c0_taghi(0);
 334
 335         for (i=0; i < size; i+= 4096) {
 336                 __asm__ __volatile__ (
 337                         ".set noreorder\n\t"
 338                         ".set mips3\n\t"
 339                         "cache %1, (%0)\n\t"
 340                         ".set mips0\n\t"
 341                         ".set reorder"
 342                         :
 343                         : "r" (KSEG0ADDR(i)),
 344                           "i" (Page_Invalidate_T));
 345         }
 346
 347         /* Let the RM7000 MM code know that the tertiary cache is enabled */
 348         rm7k_tcache_enabled = 1;
 349
 350         printk("Done\n");
 351 }
 352
 353
 354 /* This needs to be one of the first initcalls, because no I/O port access
 355    can work before this */
 356
 357 static int io_base_ioremap(void)
 358 {
 359         void *io_remap_range = ioremap(GT_PCI_IO_BASE, GT_PCI_IO_SIZE);
 360
 361         if (!io_remap_range) {
 362                 panic("Could not ioremap I/O port range");
 363         }
 364         set_io_port_base(io_remap_range - GT_PCI_IO_BASE);
 365
 366         return 0;
 367 }
 368
 369 module_init(io_base_ioremap);