arch/mips/pci/pci-ddb5476.c

   1 #include <linux/kernel.h>
   2 #include <linux/init.h>
   3 #include <linux/types.h>
   4 #include <linux/pci.h>
   5
   6 #include <asm/debug.h>
   7
   8 #include <asm/ddb5xxx/ddb5xxx.h>
   9
  10 static struct resource extpci_io_resource = {
  11         "pci IO space",
  12         0x1000,                 /* leave some room for ISA bus */
  13         DDB_PCI_IO_SIZE - 1,
  14         IORESOURCE_IO
  15 };
  16
  17 static struct resource extpci_mem_resource = {
  18         "pci memory space",
  19         DDB_PCI_MEM_BASE + 0x00100000,  /* leave 1 MB for RTC */
  20         DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE - 1,
  21         IORESOURCE_MEM
  22 };
  23
  24 extern struct pci_ops ddb5476_ext_pci_ops;
  25
  26 struct pci_controller ddb5476_controller = {
  27         .pci_ops        = &ddb5476_ext_pci_ops,
  28         .io_resource    = &extpci_io_resource,
  29         .mem_resource   = &extpci_mem_resource
  30 };
  31
  32
  33 /*
  34  * we fix up irqs based on the slot number.
  35  * The first entry is at AD:11.
  36  *
  37  * This does not work for devices on sub-buses yet.
  38  */
  39
  40 /*
  41  * temporary
  42  */
  43
  44 #define         PCI_EXT_INTA            8
  45 #define         PCI_EXT_INTB            9
  46 #define         PCI_EXT_INTC            10
  47 #define         PCI_EXT_INTD            11
  48 #define         PCI_EXT_INTE            12
  49
  50 /*
  51  * based on ddb5477 manual page 11
  52  */
  53 #define         MAX_SLOT_NUM            21
  54 static unsigned char irq_map[MAX_SLOT_NUM] = {
  55  [ 2] = 9,                              /* AD:13        USB             */
  56  [ 3] = 10,                             /* AD:14        PMU             */
  57  [ 5] = 0,                              /* AD:16        P2P bridge      */
  58  [ 6] = nile4_to_irq(PCI_EXT_INTB),     /* AD:17                        */
  59  [ 7] = nile4_to_irq(PCI_EXT_INTC),     /* AD:18                        */
  60  [ 8] = nile4_to_irq(PCI_EXT_INTD),     /* AD:19                        */
  61  [ 9] = nile4_to_irq(PCI_EXT_INTA),     /* AD:20                        */
  62  [13] = 14,                             /* AD:24 HD controller, M5229   */
  63 };
  64
  65 int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
  66 {
  67         return irq_map[slot];
  68 }
  69
  70 /* Do platform specific device initialization at pci_enable_device() time */
  71 int pcibios_plat_dev_init(struct pci_dev *dev)
  72 {
  73         return 0;
  74 }
  75
  76 void __init ddb_pci_reset_bus(void)
  77 {
  78         u32 temp;
  79
  80         /*
  81          * I am not sure about the "official" procedure, the following
  82          * steps work as far as I know:
  83          * We first set PCI cold reset bit (bit 31) in PCICTRL-H.
  84          * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H.
  85          * The same is true for both PCI channels.
  86          */
  87         temp = ddb_in32(DDB_PCICTRL + 4);
  88         temp |= 0x80000000;
  89         ddb_out32(DDB_PCICTRL + 4, temp);
  90         temp &= ~0xc0000000;
  91         ddb_out32(DDB_PCICTRL + 4, temp);
  92
  93 }