[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / arch / mips / sgi-ip32 / crime.c
blobeb3a16a04fee2c75beec145a62d725f478cd3412
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
6 * Copyright (C) 2001, 2003 Keith M Wesolowski
7 * Copyright (C) 2005 Ilya A. Volynets <ilya@total-knowledge.com>
8 */
9 #include <linux/types.h>
10 #include <linux/init.h>
11 #include <linux/kernel.h>
12 #include <linux/interrupt.h>
13 #include <asm/bootinfo.h>
14 #include <asm/io.h>
15 #include <asm/mipsregs.h>
16 #include <asm/ptrace.h>
17 #include <asm/page.h>
18 #include <asm/ip32/crime.h>
19 #include <asm/ip32/mace.h>
21 struct sgi_crime *crime;
22 struct sgi_mace *mace;
24 void __init crime_init(void)
26 unsigned int id, rev;
27 const int field = 2 * sizeof(unsigned long);
29 set_io_port_base((unsigned long) ioremap(MACEPCI_LOW_IO, 0x2000000));
30 crime = ioremap(CRIME_BASE, sizeof(struct sgi_crime));
31 mace = ioremap(MACE_BASE, sizeof(struct sgi_mace));
33 id = crime->id;
34 rev = id & CRIME_ID_REV;
35 id = (id & CRIME_ID_IDBITS) >> 4;
36 printk (KERN_INFO "CRIME id %1x rev %d at 0x%0*lx\n",
37 id, rev, field, (unsigned long) CRIME_BASE);
40 irqreturn_t
41 crime_memerr_intr (unsigned int irq, void *dev_id, struct pt_regs *regs)
43 unsigned long stat, addr;
44 int fatal = 0;
46 stat = crime->mem_error_stat & CRIME_MEM_ERROR_STAT_MASK;
47 addr = crime->mem_error_addr & CRIME_MEM_ERROR_ADDR_MASK;
49 printk("CRIME memory error at 0x%08lx ST 0x%08lx<", addr, stat);
51 if (stat & CRIME_MEM_ERROR_INV)
52 printk("INV,");
53 if (stat & CRIME_MEM_ERROR_ECC) {
54 unsigned long ecc_syn =
55 crime->mem_ecc_syn & CRIME_MEM_ERROR_ECC_SYN_MASK;
56 unsigned long ecc_gen =
57 crime->mem_ecc_chk & CRIME_MEM_ERROR_ECC_CHK_MASK;
58 printk("ECC,SYN=0x%08lx,GEN=0x%08lx,", ecc_syn, ecc_gen);
60 if (stat & CRIME_MEM_ERROR_MULTIPLE) {
61 fatal = 1;
62 printk("MULTIPLE,");
64 if (stat & CRIME_MEM_ERROR_HARD_ERR) {
65 fatal = 1;
66 printk("HARD,");
68 if (stat & CRIME_MEM_ERROR_SOFT_ERR)
69 printk("SOFT,");
70 if (stat & CRIME_MEM_ERROR_CPU_ACCESS)
71 printk("CPU,");
72 if (stat & CRIME_MEM_ERROR_VICE_ACCESS)
73 printk("VICE,");
74 if (stat & CRIME_MEM_ERROR_GBE_ACCESS)
75 printk("GBE,");
76 if (stat & CRIME_MEM_ERROR_RE_ACCESS)
77 printk("RE,REID=0x%02lx,", (stat & CRIME_MEM_ERROR_RE_ID)>>8);
78 if (stat & CRIME_MEM_ERROR_MACE_ACCESS)
79 printk("MACE,MACEID=0x%02lx,", stat & CRIME_MEM_ERROR_MACE_ID);
81 crime->mem_error_stat = 0;
83 if (fatal) {
84 printk("FATAL>\n");
85 panic("Fatal memory error.");
86 } else
87 printk("NONFATAL>\n");
89 return IRQ_HANDLED;
92 irqreturn_t
93 crime_cpuerr_intr (unsigned int irq, void *dev_id, struct pt_regs *regs)
95 unsigned long stat = crime->cpu_error_stat & CRIME_CPU_ERROR_MASK;
96 unsigned long addr = crime->cpu_error_addr & CRIME_CPU_ERROR_ADDR_MASK;
98 addr <<= 2;
99 printk ("CRIME CPU error at 0x%09lx status 0x%08lx\n", addr, stat);
100 crime->cpu_error_stat = 0;
102 return IRQ_HANDLED;