arch/mips/sgi-ip32/ip32-setup.c

   1 /*
   2  * IP32 basic setup
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 2000 Harald Koerfgen
   9  * Copyright (C) 2002, 2003, 2005 Ilya A. Volynets
  10  */
  11 #include <linux/config.h>
  12 #include <linux/console.h>
  13 #include <linux/init.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/mc146818rtc.h>
  16 #include <linux/param.h>
  17 #include <linux/sched.h>
  18
  19 #include <asm/bootinfo.h>
  20 #include <asm/mc146818-time.h>
  21 #include <asm/mipsregs.h>
  22 #include <asm/mmu_context.h>
  23 #include <asm/sgialib.h>
  24 #include <asm/time.h>
  25 #include <asm/traps.h>
  26 #include <asm/io.h>
  27 #include <asm/ip32/crime.h>
  28 #include <asm/ip32/mace.h>
  29 #include <asm/ip32/ip32_ints.h>
  30
  31 extern void ip32_be_init(void);
  32 extern void crime_init(void);
  33
  34 #ifdef CONFIG_SGI_O2MACE_ETH
  35 /*
  36  * This is taken care of in here 'cause they say using Arc later on is
  37  * problematic
  38  */
  39 extern char o2meth_eaddr[8];
  40 static inline unsigned char str2hexnum(unsigned char c)
  41 {
  42         if (c >= '0' && c <= '9')
  43                 return c - '0';
  44         if (c >= 'a' && c <= 'f')
  45                 return c - 'a' + 10;
  46         return 0; /* foo */
  47 }
  48
  49 static inline void str2eaddr(unsigned char *ea, unsigned char *str)
  50 {
  51         int i;
  52
  53         for (i = 0; i < 6; i++) {
  54                 unsigned char num;
  55
  56                 if(*str == ':')
  57                         str++;
  58                 num = str2hexnum(*str++) << 4;
  59                 num |= (str2hexnum(*str++));
  60                 ea[i] = num;
  61         }
  62 }
  63 #endif
  64
  65 #ifdef CONFIG_SERIAL_8250
  66 #include <linux/tty.h>
  67 #include <linux/serial.h>
  68 #include <linux/serial_core.h>
  69 extern int early_serial_setup(struct uart_port *port);
  70
  71 #define STD_COM_FLAGS (ASYNC_SKIP_TEST)
  72 #define BASE_BAUD (1843200 / 16)
  73
  74 #endif /* CONFIG_SERIAL_8250 */
  75
  76 /* An arbitrary time; this can be decreased if reliability looks good */
  77 #define WAIT_MS 10
  78
  79 void __init ip32_time_init(void)
  80 {
  81         printk(KERN_INFO "Calibrating system timer... ");
  82         write_c0_count(0);
  83         crime->timer = 0;
  84         while (crime->timer < CRIME_MASTER_FREQ * WAIT_MS / 1000) ;
  85         mips_hpt_frequency = read_c0_count() * 1000 / WAIT_MS;
  86         printk("%d MHz CPU detected\n", mips_hpt_frequency * 2 / 1000000);
  87 }
  88
  89 void __init ip32_timer_setup(struct irqaction *irq)
  90 {
  91         irq->handler = no_action;
  92         setup_irq(IP32_R4K_TIMER_IRQ, irq);
  93 }
  94
  95 static int __init ip32_setup(void)
  96 {
  97         board_be_init = ip32_be_init;
  98
  99         rtc_get_time = mc146818_get_cmos_time;
 100         rtc_set_mmss = mc146818_set_rtc_mmss;
 101
 102         board_time_init = ip32_time_init;
 103         board_timer_setup = ip32_timer_setup;
 104
 105 #ifdef CONFIG_SERIAL_8250
 106         {
 107                 static struct uart_port o2_serial[2];
 108
 109                 memset(o2_serial, 0, sizeof(o2_serial));
 110                 o2_serial[0].type       = PORT_16550A;
 111                 o2_serial[0].line       = 0;
 112                 o2_serial[0].irq        = MACEISA_SERIAL1_IRQ;
 113                 o2_serial[0].flags      = STD_COM_FLAGS;
 114                 o2_serial[0].uartclk    = BASE_BAUD * 16;
 115                 o2_serial[0].iotype     = UPIO_MEM;
 116                 o2_serial[0].membase    = (char *)&mace->isa.serial1;
 117                 o2_serial[0].fifosize   = 14;
 118                 /* How much to shift register offset by. Each UART register
 119                  * is replicated over 256 byte space */
 120                 o2_serial[0].regshift   = 8;
 121                 o2_serial[1].type       = PORT_16550A;
 122                 o2_serial[1].line       = 1;
 123                 o2_serial[1].irq        = MACEISA_SERIAL2_IRQ;
 124                 o2_serial[1].flags      = STD_COM_FLAGS;
 125                 o2_serial[1].uartclk    = BASE_BAUD * 16;
 126                 o2_serial[1].iotype     = UPIO_MEM;
 127                 o2_serial[1].membase    = (char *)&mace->isa.serial2;
 128                 o2_serial[1].fifosize   = 14;
 129                 o2_serial[1].regshift   = 8;
 130
 131                 early_serial_setup(&o2_serial[0]);
 132                 early_serial_setup(&o2_serial[1]);
 133         }
 134 #endif
 135 #ifdef CONFIG_SGI_O2MACE_ETH
 136         {
 137                 char *mac = ArcGetEnvironmentVariable("eaddr");
 138                 str2eaddr(o2meth_eaddr, mac);
 139         }
 140 #endif
 141
 142 #if defined(CONFIG_SERIAL_CORE_CONSOLE)
 143         {
 144                 char* con = ArcGetEnvironmentVariable("console");
 145                 if (con && *con == 'd') {
 146                         static char options[8];
 147                         char *baud = ArcGetEnvironmentVariable("dbaud");
 148                         if (baud)
 149                                 strcpy(options, baud);
 150                         add_preferred_console("ttyS", *(con + 1) == '2' ? 1 : 0,
 151                                               baud ? options : NULL);
 152                 }
 153         }
 154 #endif
 155
 156         return 0;
 157 }
 158
 159 early_initcall(ip32_setup);