| blob | 9b6a8e5136570537adca7dc8ddf244a8fac19cfd |
1 /*
2 * arch/ppc/kernel/head_44x.S
3 *
4 * Kernel execution entry point code.
5 *
6 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
7 * Initial PowerPC version.
8 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
9 * Rewritten for PReP
10 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
11 * Low-level exception handers, MMU support, and rewrite.
12 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
13 * PowerPC 8xx modifications.
14 * Copyright (c) 1998-1999 TiVo, Inc.
15 * PowerPC 403GCX modifications.
16 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
17 * PowerPC 403GCX/405GP modifications.
18 * Copyright 2000 MontaVista Software Inc.
19 * PPC405 modifications
20 * PowerPC 403GCX/405GP modifications.
21 * Author: MontaVista Software, Inc.
22 * frank_rowand@mvista.com or source@mvista.com
23 * debbie_chu@mvista.com
24 * Copyright 2002-2005 MontaVista Software, Inc.
25 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
26 *
27 * This program is free software; you can redistribute it and/or modify it
28 * under the terms of the GNU General Public License as published by the
29 * Free Software Foundation; either version 2 of the License, or (at your
30 * option) any later version.
31 */
33 #include <linux/config.h>
34 #include <asm/processor.h>
35 #include <asm/page.h>
36 #include <asm/mmu.h>
37 #include <asm/pgtable.h>
38 #include <asm/ibm4xx.h>
39 #include <asm/ibm44x.h>
40 #include <asm/cputable.h>
41 #include <asm/thread_info.h>
42 #include <asm/ppc_asm.h>
43 #include <asm/offsets.h>
44 #include "head_booke.h"
47 /* As with the other PowerPC ports, it is expected that when code
48 * execution begins here, the following registers contain valid, yet
49 * optional, information:
50 *
51 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
52 * r4 - Starting address of the init RAM disk
53 * r5 - Ending address of the init RAM disk
54 * r6 - Start of kernel command line string (e.g. "mem=128")
55 * r7 - End of kernel command line string
56 *
57 */
58 .text
59 _GLOBAL(_stext)
60 _GLOBAL(_start)
61 /*
62 * Reserve a word at a fixed location to store the address
63 * of abatron_pteptrs
64 */
65 nop
66 /*
67 * Save parameters we are passed
68 */
69 mr r31,r3
70 mr r30,r4
71 mr r29,r5
72 mr r28,r6
73 mr r27,r7
74 li r24,0 /* CPU number */
76 /*
77 * Set up the initial MMU state
78 *
79 * We are still executing code at the virtual address
80 * mappings set by the firmware for the base of RAM.
81 *
82 * We first invalidate all TLB entries but the one
83 * we are running from. We then load the KERNELBASE
84 * mappings so we can begin to use kernel addresses
85 * natively and so the interrupt vector locations are
86 * permanently pinned (necessary since Book E
87 * implementations always have translation enabled).
88 *
89 * TODO: Use the known TLB entry we are running from to
90 * determine which physical region we are located
91 * in. This can be used to determine where in RAM
92 * (on a shared CPU system) or PCI memory space
93 * (on a DRAMless system) we are located.
94 * For now, we assume a perfect world which means
95 * we are located at the base of DRAM (physical 0).
96 */
98 /*
99 * Search TLB for entry that we are currently using.
100 * Invalidate all entries but the one we are using.
101 */
102 /* Load our current PID->MMUCR TID and MSR IS->MMUCR STS */
103 mfspr r3,SPRN_PID /* Get PID */
104 mfmsr r4 /* Get MSR */
105 andi. r4,r4,MSR_IS@l /* TS=1? */
106 beq wmmucr /* If not, leave STS=0 */
107 oris r3,r3,PPC44x_MMUCR_STS@h /* Set STS=1 */
108 wmmucr: mtspr SPRN_MMUCR,r3 /* Put MMUCR */
109 sync
111 bl invstr /* Find our address */
112 invstr: mflr r5 /* Make it accessible */
113 tlbsx r23,0,r5 /* Find entry we are in */
114 li r4,0 /* Start at TLB entry 0 */
115 li r3,0 /* Set PAGEID inval value */
116 1: cmpw r23,r4 /* Is this our entry? */
117 beq skpinv /* If so, skip the inval */
118 tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */
119 skpinv: addi r4,r4,1 /* Increment */
120 cmpwi r4,64 /* Are we done? */
121 bne 1b /* If not, repeat */
122 isync /* If so, context change */
124 /*
125 * Configure and load pinned entry into TLB slot 63.
126 */
128 lis r3,KERNELBASE@h /* Load the kernel virtual address */
129 ori r3,r3,KERNELBASE@l
131 /* Kernel is at the base of RAM */
132 li r4, 0 /* Load the kernel physical address */
134 /* Load the kernel PID = 0 */
135 li r0,0
136 mtspr SPRN_PID,r0
137 sync
139 /* Initialize MMUCR */
140 li r5,0
141 mtspr SPRN_MMUCR,r5
142 sync
144 /* pageid fields */
145 clrrwi r3,r3,10 /* Mask off the effective page number */
146 ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_256M
148 /* xlat fields */
149 clrrwi r4,r4,10 /* Mask off the real page number */
150 /* ERPN is 0 for first 4GB page */
152 /* attrib fields */
153 /* Added guarded bit to protect against speculative loads/stores */
154 li r5,0
155 ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G)
157 li r0,63 /* TLB slot 63 */
159 tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */
160 tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */
161 tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */
163 /* Force context change */
164 mfmsr r0
165 mtspr SPRN_SRR1, r0
166 lis r0,3f@h
167 ori r0,r0,3f@l
168 mtspr SPRN_SRR0,r0
169 sync
170 rfi
172 /* If necessary, invalidate original entry we used */
173 3: cmpwi r23,63
174 beq 4f
175 li r6,0
176 tlbwe r6,r23,PPC44x_TLB_PAGEID
177 isync
179 4:
180 #ifdef CONFIG_SERIAL_TEXT_DEBUG
181 /*
182 * Add temporary UART mapping for early debug. This
183 * mapping must be identical to that used by the early
184 * bootloader code since the same asm/serial.h parameters
185 * are used for polled operation.
186 */
187 /* pageid fields */
188 lis r3,UART0_IO_BASE@h
189 ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_256M
191 /* xlat fields */
192 lis r4,UART0_PHYS_IO_BASE@h /* RPN depends on SoC */
193 ori r4,r4,0x0001 /* ERPN is 1 for second 4GB page */
195 /* attrib fields */
196 li r5,0
197 ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_I | PPC44x_TLB_G)
199 li r0,1 /* TLB slot 1 */
201 tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */
202 tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */
203 tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */
205 /* Force context change */
206 isync
207 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
209 /* Establish the interrupt vector offsets */
210 SET_IVOR(0, CriticalInput);
211 SET_IVOR(1, MachineCheck);
212 SET_IVOR(2, DataStorage);
213 SET_IVOR(3, InstructionStorage);
214 SET_IVOR(4, ExternalInput);
215 SET_IVOR(5, Alignment);
216 SET_IVOR(6, Program);
217 SET_IVOR(7, FloatingPointUnavailable);
218 SET_IVOR(8, SystemCall);
219 SET_IVOR(9, AuxillaryProcessorUnavailable);
220 SET_IVOR(10, Decrementer);
221 SET_IVOR(11, FixedIntervalTimer);
222 SET_IVOR(12, WatchdogTimer);
223 SET_IVOR(13, DataTLBError);
224 SET_IVOR(14, InstructionTLBError);
225 SET_IVOR(15, Debug);
227 /* Establish the interrupt vector base */
228 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
229 mtspr SPRN_IVPR,r4
231 /*
232 * This is where the main kernel code starts.
233 */
235 /* ptr to current */
236 lis r2,init_task@h
237 ori r2,r2,init_task@l
239 /* ptr to current thread */
240 addi r4,r2,THREAD /* init task's THREAD */
241 mtspr SPRN_SPRG3,r4
243 /* stack */
244 lis r1,init_thread_union@h
245 ori r1,r1,init_thread_union@l
246 li r0,0
247 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
249 bl early_init
251 /*
252 * Decide what sort of machine this is and initialize the MMU.
253 */
254 mr r3,r31
255 mr r4,r30
256 mr r5,r29
257 mr r6,r28
258 mr r7,r27
259 bl machine_init
260 bl MMU_init
262 /* Setup PTE pointers for the Abatron bdiGDB */
263 lis r6, swapper_pg_dir@h
264 ori r6, r6, swapper_pg_dir@l
265 lis r5, abatron_pteptrs@h
266 ori r5, r5, abatron_pteptrs@l
267 lis r4, KERNELBASE@h
268 ori r4, r4, KERNELBASE@l
269 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
270 stw r6, 0(r5)
272 /* Let's move on */
273 lis r4,start_kernel@h
274 ori r4,r4,start_kernel@l
275 lis r3,MSR_KERNEL@h
276 ori r3,r3,MSR_KERNEL@l
277 mtspr SPRN_SRR0,r4
278 mtspr SPRN_SRR1,r3
279 rfi /* change context and jump to start_kernel */
281 /*
282 * Interrupt vector entry code
283 *
284 * The Book E MMUs are always on so we don't need to handle
285 * interrupts in real mode as with previous PPC processors. In
286 * this case we handle interrupts in the kernel virtual address
287 * space.
288 *
289 * Interrupt vectors are dynamically placed relative to the
290 * interrupt prefix as determined by the address of interrupt_base.
291 * The interrupt vectors offsets are programmed using the labels
292 * for each interrupt vector entry.
293 *
294 * Interrupt vectors must be aligned on a 16 byte boundary.
295 * We align on a 32 byte cache line boundary for good measure.
296 */
298 interrupt_base:
299 /* Critical Input Interrupt */
300 CRITICAL_EXCEPTION(0x0100, CriticalInput, UnknownException)
302 /* Machine Check Interrupt */
303 #ifdef CONFIG_440A
304 MCHECK_EXCEPTION(0x0200, MachineCheck, MachineCheckException)
305 #else
306 CRITICAL_EXCEPTION(0x0200, MachineCheck, MachineCheckException)
307 #endif
309 /* Data Storage Interrupt */
310 START_EXCEPTION(DataStorage)
311 mtspr SPRN_SPRG0, r10 /* Save some working registers */
312 mtspr SPRN_SPRG1, r11
313 mtspr SPRN_SPRG4W, r12
314 mtspr SPRN_SPRG5W, r13
315 mfcr r11
316 mtspr SPRN_SPRG7W, r11
318 /*
319 * Check if it was a store fault, if not then bail
320 * because a user tried to access a kernel or
321 * read-protected page. Otherwise, get the
322 * offending address and handle it.
323 */
324 mfspr r10, SPRN_ESR
325 andis. r10, r10, ESR_ST@h
326 beq 2f
328 mfspr r10, SPRN_DEAR /* Get faulting address */
330 /* If we are faulting a kernel address, we have to use the
331 * kernel page tables.
332 */
333 andis. r11, r10, 0x8000
334 beq 3f
335 lis r11, swapper_pg_dir@h
336 ori r11, r11, swapper_pg_dir@l
338 mfspr r12,SPRN_MMUCR
339 rlwinm r12,r12,0,0,23 /* Clear TID */
341 b 4f
343 /* Get the PGD for the current thread */
344 3:
345 mfspr r11,SPRN_SPRG3
346 lwz r11,PGDIR(r11)
348 /* Load PID into MMUCR TID */
349 mfspr r12,SPRN_MMUCR /* Get MMUCR */
350 mfspr r13,SPRN_PID /* Get PID */
351 rlwimi r12,r13,0,24,31 /* Set TID */
353 4:
354 mtspr SPRN_MMUCR,r12
356 rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */
357 lwzx r11, r12, r11 /* Get pgd/pmd entry */
358 rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */
359 beq 2f /* Bail if no table */
361 rlwimi r12, r10, 23, 20, 28 /* Compute pte address */
362 lwz r11, 4(r12) /* Get pte entry */
364 andi. r13, r11, _PAGE_RW /* Is it writeable? */
365 beq 2f /* Bail if not */
367 /* Update 'changed'.
368 */
369 ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
370 stw r11, 4(r12) /* Update Linux page table */
372 li r13, PPC44x_TLB_SR@l /* Set SR */
373 rlwimi r13, r11, 29, 29, 29 /* SX = _PAGE_HWEXEC */
374 rlwimi r13, r11, 0, 30, 30 /* SW = _PAGE_RW */
375 rlwimi r13, r11, 29, 28, 28 /* UR = _PAGE_USER */
376 rlwimi r12, r11, 31, 26, 26 /* (_PAGE_USER>>1)->r12 */
377 rlwimi r12, r11, 29, 30, 30 /* (_PAGE_USER>>3)->r12 */
378 and r12, r12, r11 /* HWEXEC/RW & USER */
379 rlwimi r13, r12, 0, 26, 26 /* UX = HWEXEC & USER */
380 rlwimi r13, r12, 3, 27, 27 /* UW = RW & USER */
382 rlwimi r11,r13,0,26,31 /* Insert static perms */
384 rlwinm r11,r11,0,20,15 /* Clear U0-U3 */
386 /* find the TLB index that caused the fault. It has to be here. */
387 tlbsx r10, 0, r10
389 tlbwe r11, r10, PPC44x_TLB_ATTRIB /* Write ATTRIB */
391 /* Done...restore registers and get out of here.
392 */
393 mfspr r11, SPRN_SPRG7R
394 mtcr r11
395 mfspr r13, SPRN_SPRG5R
396 mfspr r12, SPRN_SPRG4R
398 mfspr r11, SPRN_SPRG1
399 mfspr r10, SPRN_SPRG0
400 rfi /* Force context change */
402 2:
403 /*
404 * The bailout. Restore registers to pre-exception conditions
405 * and call the heavyweights to help us out.
406 */
407 mfspr r11, SPRN_SPRG7R
408 mtcr r11
409 mfspr r13, SPRN_SPRG5R
410 mfspr r12, SPRN_SPRG4R
412 mfspr r11, SPRN_SPRG1
413 mfspr r10, SPRN_SPRG0
414 b data_access
416 /* Instruction Storage Interrupt */
417 INSTRUCTION_STORAGE_EXCEPTION
419 /* External Input Interrupt */
420 EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
422 /* Alignment Interrupt */
423 ALIGNMENT_EXCEPTION
425 /* Program Interrupt */
426 PROGRAM_EXCEPTION
428 /* Floating Point Unavailable Interrupt */
429 #ifdef CONFIG_PPC_FPU
430 FP_UNAVAILABLE_EXCEPTION
431 #else
432 EXCEPTION(0x2010, FloatingPointUnavailable, UnknownException, EXC_XFER_EE)
433 #endif
435 /* System Call Interrupt */
436 START_EXCEPTION(SystemCall)
437 NORMAL_EXCEPTION_PROLOG
438 EXC_XFER_EE_LITE(0x0c00, DoSyscall)
440 /* Auxillary Processor Unavailable Interrupt */
441 EXCEPTION(0x2020, AuxillaryProcessorUnavailable, UnknownException, EXC_XFER_EE)
443 /* Decrementer Interrupt */
444 DECREMENTER_EXCEPTION
446 /* Fixed Internal Timer Interrupt */
447 /* TODO: Add FIT support */
448 EXCEPTION(0x1010, FixedIntervalTimer, UnknownException, EXC_XFER_EE)
450 /* Watchdog Timer Interrupt */
451 /* TODO: Add watchdog support */
452 CRITICAL_EXCEPTION(0x1020, WatchdogTimer, UnknownException)
454 /* Data TLB Error Interrupt */
455 START_EXCEPTION(DataTLBError)
456 mtspr SPRN_SPRG0, r10 /* Save some working registers */
457 mtspr SPRN_SPRG1, r11
458 mtspr SPRN_SPRG4W, r12
459 mtspr SPRN_SPRG5W, r13
460 mfcr r11
461 mtspr SPRN_SPRG7W, r11
462 mfspr r10, SPRN_DEAR /* Get faulting address */
464 /* If we are faulting a kernel address, we have to use the
465 * kernel page tables.
466 */
467 andis. r11, r10, 0x8000
468 beq 3f
469 lis r11, swapper_pg_dir@h
470 ori r11, r11, swapper_pg_dir@l
472 mfspr r12,SPRN_MMUCR
473 rlwinm r12,r12,0,0,23 /* Clear TID */
475 b 4f
477 /* Get the PGD for the current thread */
478 3:
479 mfspr r11,SPRN_SPRG3
480 lwz r11,PGDIR(r11)
482 /* Load PID into MMUCR TID */
483 mfspr r12,SPRN_MMUCR
484 mfspr r13,SPRN_PID /* Get PID */
485 rlwimi r12,r13,0,24,31 /* Set TID */
487 4:
488 mtspr SPRN_MMUCR,r12
490 rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */
491 lwzx r11, r12, r11 /* Get pgd/pmd entry */
492 rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */
493 beq 2f /* Bail if no table */
495 rlwimi r12, r10, 23, 20, 28 /* Compute pte address */
496 lwz r11, 4(r12) /* Get pte entry */
497 andi. r13, r11, _PAGE_PRESENT /* Is the page present? */
498 beq 2f /* Bail if not present */
500 ori r11, r11, _PAGE_ACCESSED
501 stw r11, 4(r12)
503 /* Jump to common tlb load */
504 b finish_tlb_load
506 2:
507 /* The bailout. Restore registers to pre-exception conditions
508 * and call the heavyweights to help us out.
509 */
510 mfspr r11, SPRN_SPRG7R
511 mtcr r11
512 mfspr r13, SPRN_SPRG5R
513 mfspr r12, SPRN_SPRG4R
514 mfspr r11, SPRN_SPRG1
515 mfspr r10, SPRN_SPRG0
516 b data_access
518 /* Instruction TLB Error Interrupt */
519 /*
520 * Nearly the same as above, except we get our
521 * information from different registers and bailout
522 * to a different point.
523 */
524 START_EXCEPTION(InstructionTLBError)
525 mtspr SPRN_SPRG0, r10 /* Save some working registers */
526 mtspr SPRN_SPRG1, r11
527 mtspr SPRN_SPRG4W, r12
528 mtspr SPRN_SPRG5W, r13
529 mfcr r11
530 mtspr SPRN_SPRG7W, r11
531 mfspr r10, SPRN_SRR0 /* Get faulting address */
533 /* If we are faulting a kernel address, we have to use the
534 * kernel page tables.
535 */
536 andis. r11, r10, 0x8000
537 beq 3f
538 lis r11, swapper_pg_dir@h
539 ori r11, r11, swapper_pg_dir@l
541 mfspr r12,SPRN_MMUCR
542 rlwinm r12,r12,0,0,23 /* Clear TID */
544 b 4f
546 /* Get the PGD for the current thread */
547 3:
548 mfspr r11,SPRN_SPRG3
549 lwz r11,PGDIR(r11)
551 /* Load PID into MMUCR TID */
552 mfspr r12,SPRN_MMUCR
553 mfspr r13,SPRN_PID /* Get PID */
554 rlwimi r12,r13,0,24,31 /* Set TID */
556 4:
557 mtspr SPRN_MMUCR,r12
559 rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */
560 lwzx r11, r12, r11 /* Get pgd/pmd entry */
561 rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */
562 beq 2f /* Bail if no table */
564 rlwimi r12, r10, 23, 20, 28 /* Compute pte address */
565 lwz r11, 4(r12) /* Get pte entry */
566 andi. r13, r11, _PAGE_PRESENT /* Is the page present? */
567 beq 2f /* Bail if not present */
569 ori r11, r11, _PAGE_ACCESSED
570 stw r11, 4(r12)
572 /* Jump to common TLB load point */
573 b finish_tlb_load
575 2:
576 /* The bailout. Restore registers to pre-exception conditions
577 * and call the heavyweights to help us out.
578 */
579 mfspr r11, SPRN_SPRG7R
580 mtcr r11
581 mfspr r13, SPRN_SPRG5R
582 mfspr r12, SPRN_SPRG4R
583 mfspr r11, SPRN_SPRG1
584 mfspr r10, SPRN_SPRG0
585 b InstructionStorage
587 /* Debug Interrupt */
588 DEBUG_EXCEPTION
590 /*
591 * Local functions
592 */
593 /*
594 * Data TLB exceptions will bail out to this point
595 * if they can't resolve the lightweight TLB fault.
596 */
597 data_access:
598 NORMAL_EXCEPTION_PROLOG
599 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
600 stw r5,_ESR(r11)
601 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
602 EXC_XFER_EE_LITE(0x0300, handle_page_fault)
604 /*
606 * Both the instruction and data TLB miss get to this
607 * point to load the TLB.
608 * r10 - EA of fault
609 * r11 - available to use
610 * r12 - Pointer to the 64-bit PTE
611 * r13 - available to use
612 * MMUCR - loaded with proper value when we get here
613 * Upon exit, we reload everything and RFI.
614 */
615 finish_tlb_load:
616 /*
617 * We set execute, because we don't have the granularity to
618 * properly set this at the page level (Linux problem).
619 * If shared is set, we cause a zero PID->TID load.
620 * Many of these bits are software only. Bits we don't set
621 * here we (properly should) assume have the appropriate value.
622 */
624 /* Load the next available TLB index */
625 lis r13, tlb_44x_index@ha
626 lwz r13, tlb_44x_index@l(r13)
627 /* Load the TLB high watermark */
628 lis r11, tlb_44x_hwater@ha
629 lwz r11, tlb_44x_hwater@l(r11)
631 /* Increment, rollover, and store TLB index */
632 addi r13, r13, 1
633 cmpw 0, r13, r11 /* reserve entries */
634 ble 7f
635 li r13, 0
636 7:
637 /* Store the next available TLB index */
638 lis r11, tlb_44x_index@ha
639 stw r13, tlb_44x_index@l(r11)
641 lwz r11, 0(r12) /* Get MS word of PTE */
642 lwz r12, 4(r12) /* Get LS word of PTE */
643 rlwimi r11, r12, 0, 0 , 19 /* Insert RPN */
644 tlbwe r11, r13, PPC44x_TLB_XLAT /* Write XLAT */
646 /*
647 * Create PAGEID. This is the faulting address,
648 * page size, and valid flag.
649 */
650 li r11, PPC44x_TLB_VALID | PPC44x_TLB_4K
651 rlwimi r10, r11, 0, 20, 31 /* Insert valid and page size */
652 tlbwe r10, r13, PPC44x_TLB_PAGEID /* Write PAGEID */
654 li r10, PPC44x_TLB_SR@l /* Set SR */
655 rlwimi r10, r12, 0, 30, 30 /* Set SW = _PAGE_RW */
656 rlwimi r10, r12, 29, 29, 29 /* SX = _PAGE_HWEXEC */
657 rlwimi r10, r12, 29, 28, 28 /* UR = _PAGE_USER */
658 rlwimi r11, r12, 31, 26, 26 /* (_PAGE_USER>>1)->r12 */
659 and r11, r12, r11 /* HWEXEC & USER */
660 rlwimi r10, r11, 0, 26, 26 /* UX = HWEXEC & USER */
662 rlwimi r12, r10, 0, 26, 31 /* Insert static perms */
663 rlwinm r12, r12, 0, 20, 15 /* Clear U0-U3 */
664 tlbwe r12, r13, PPC44x_TLB_ATTRIB /* Write ATTRIB */
666 /* Done...restore registers and get out of here.
667 */
668 mfspr r11, SPRN_SPRG7R
669 mtcr r11
670 mfspr r13, SPRN_SPRG5R
671 mfspr r12, SPRN_SPRG4R
672 mfspr r11, SPRN_SPRG1
673 mfspr r10, SPRN_SPRG0
674 rfi /* Force context change */
676 /*
677 * Global functions
678 */
680 /*
681 * extern void giveup_altivec(struct task_struct *prev)
682 *
683 * The 44x core does not have an AltiVec unit.
684 */
685 _GLOBAL(giveup_altivec)
686 blr
688 /*
689 * extern void giveup_fpu(struct task_struct *prev)
690 *
691 * The 44x core does not have an FPU.
692 */
693 #ifndef CONFIG_PPC_FPU
694 _GLOBAL(giveup_fpu)
695 blr
696 #endif
698 /*
699 * extern void abort(void)
700 *
701 * At present, this routine just applies a system reset.
702 */
703 _GLOBAL(abort)
704 mfspr r13,SPRN_DBCR0
705 oris r13,r13,DBCR0_RST_SYSTEM@h
706 mtspr SPRN_DBCR0,r13
708 _GLOBAL(set_context)
710 #ifdef CONFIG_BDI_SWITCH
711 /* Context switch the PTE pointer for the Abatron BDI2000.
712 * The PGDIR is the second parameter.
713 */
714 lis r5, abatron_pteptrs@h
715 ori r5, r5, abatron_pteptrs@l
716 stw r4, 0x4(r5)
717 #endif
718 mtspr SPRN_PID,r3
719 isync /* Force context change */
720 blr
722 /*
723 * We put a few things here that have to be page-aligned. This stuff
724 * goes at the beginning of the data segment, which is page-aligned.
725 */
726 .data
727 _GLOBAL(sdata)
728 _GLOBAL(empty_zero_page)
729 .space 4096
731 /*
732 * To support >32-bit physical addresses, we use an 8KB pgdir.
733 */
734 _GLOBAL(swapper_pg_dir)
735 .space 8192
737 /* Reserved 4k for the critical exception stack & 4k for the machine
738 * check stack per CPU for kernel mode exceptions */
739 .section .bss
740 .align 12
741 exception_stack_bottom:
742 .space BOOKE_EXCEPTION_STACK_SIZE
743 _GLOBAL(exception_stack_top)
745 /*
746 * This space gets a copy of optional info passed to us by the bootstrap
747 * which is used to pass parameters into the kernel like root=/dev/sda1, etc.
748 */
749 _GLOBAL(cmd_line)
750 .space 512
752 /*
753 * Room for two PTE pointers, usually the kernel and current user pointers
754 * to their respective root page table.
755 */
756 abatron_pteptrs:
757 .space 8