arch/ppc/mm/ppc_mmu.c

   1 /*
   2  * This file contains the routines for handling the MMU on those
   3  * PowerPC implementations where the MMU substantially follows the
   4  * architecture specification.  This includes the 6xx, 7xx, 7xxx,
   5  * 8260, and POWER3 implementations but excludes the 8xx and 4xx.
   6  *  -- paulus
   7  *
   8  *  Derived from arch/ppc/mm/init.c:
   9  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  10  *
  11  *  Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
  12  *  and Cort Dougan (PReP) (cort@cs.nmt.edu)
  13  *    Copyright (C) 1996 Paul Mackerras
  14  *  Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
  15  *
  16  *  Derived from "arch/i386/mm/init.c"
  17  *    Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
  18  *
  19  *  This program is free software; you can redistribute it and/or
  20  *  modify it under the terms of the GNU General Public License
  21  *  as published by the Free Software Foundation; either version
  22  *  2 of the License, or (at your option) any later version.
  23  *
  24  */
  25
  26 #include <linux/config.h>
  27 #include <linux/kernel.h>
  28 #include <linux/mm.h>
  29 #include <linux/init.h>
  30 #include <linux/highmem.h>
  31
  32 #include <asm/prom.h>
  33 #include <asm/mmu.h>
  34 #include <asm/machdep.h>
  35
  36 #include "mmu_decl.h"
  37 #include "mem_pieces.h"
  38
  39 PTE *Hash, *Hash_end;
  40 unsigned long Hash_size, Hash_mask;
  41 unsigned long _SDR1;
  42
  43 union ubat {                    /* BAT register values to be loaded */
  44         BAT     bat;
  45 #ifdef CONFIG_PPC64BRIDGE
  46         u64     word[2];
  47 #else
  48         u32     word[2];
  49 #endif
  50 } BATS[4][2];                   /* 4 pairs of IBAT, DBAT */
  51
  52 struct batrange {               /* stores address ranges mapped by BATs */
  53         unsigned long start;
  54         unsigned long limit;
  55         unsigned long phys;
  56 } bat_addrs[4];
  57
  58 /*
  59  * Return PA for this VA if it is mapped by a BAT, or 0
  60  */
  61 unsigned long v_mapped_by_bats(unsigned long va)
  62 {
  63         int b;
  64         for (b = 0; b < 4; ++b)
  65                 if (va >= bat_addrs[b].start && va < bat_addrs[b].limit)
  66                         return bat_addrs[b].phys + (va - bat_addrs[b].start);
  67         return 0;
  68 }
  69
  70 /*
  71  * Return VA for a given PA or 0 if not mapped
  72  */
  73 unsigned long p_mapped_by_bats(unsigned long pa)
  74 {
  75         int b;
  76         for (b = 0; b < 4; ++b)
  77                 if (pa >= bat_addrs[b].phys
  78                     && pa < (bat_addrs[b].limit-bat_addrs[b].start)
  79                               +bat_addrs[b].phys)
  80                         return bat_addrs[b].start+(pa-bat_addrs[b].phys);
  81         return 0;
  82 }
  83
  84 unsigned long __init mmu_mapin_ram(void)
  85 {
  86 #ifdef CONFIG_POWER4
  87         return 0;
  88 #else
  89         unsigned long tot, bl, done;
  90         unsigned long max_size = (256<<20);
  91         unsigned long align;
  92
  93         if (__map_without_bats)
  94                 return 0;
  95
  96         /* Set up BAT2 and if necessary BAT3 to cover RAM. */
  97
  98         /* Make sure we don't map a block larger than the
  99            smallest alignment of the physical address. */
 100         /* alignment of PPC_MEMSTART */
 101         align = ~(PPC_MEMSTART-1) & PPC_MEMSTART;
 102         /* set BAT block size to MIN(max_size, align) */
 103         if (align && align < max_size)
 104                 max_size = align;
 105
 106         tot = total_lowmem;
 107         for (bl = 128<<10; bl < max_size; bl <<= 1) {
 108                 if (bl * 2 > tot)
 109                         break;
 110         }
 111
 112         setbat(2, KERNELBASE, PPC_MEMSTART, bl, _PAGE_RAM);
 113         done = (unsigned long)bat_addrs[2].limit - KERNELBASE + 1;
 114         if ((done < tot) && !bat_addrs[3].limit) {
 115                 /* use BAT3 to cover a bit more */
 116                 tot -= done;
 117                 for (bl = 128<<10; bl < max_size; bl <<= 1)
 118                         if (bl * 2 > tot)
 119                                 break;
 120                 setbat(3, KERNELBASE+done, PPC_MEMSTART+done, bl, _PAGE_RAM);
 121                 done = (unsigned long)bat_addrs[3].limit - KERNELBASE + 1;
 122         }
 123
 124         return done;
 125 #endif
 126 }
 127
 128 /*
 129  * Set up one of the I/D BAT (block address translation) register pairs.
 130  * The parameters are not checked; in particular size must be a power
 131  * of 2 between 128k and 256M.
 132  */
 133 void __init setbat(int index, unsigned long virt, unsigned long phys,
 134                    unsigned int size, int flags)
 135 {
 136         unsigned int bl;
 137         int wimgxpp;
 138         union ubat *bat = BATS[index];
 139
 140         if (((flags & _PAGE_NO_CACHE) == 0) &&
 141             cpu_has_feature(CPU_FTR_NEED_COHERENT))
 142                 flags |= _PAGE_COHERENT;
 143
 144         bl = (size >> 17) - 1;
 145         if (PVR_VER(mfspr(SPRN_PVR)) != 1) {
 146                 /* 603, 604, etc. */
 147                 /* Do DBAT first */
 148                 wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE
 149                                    | _PAGE_COHERENT | _PAGE_GUARDED);
 150                 wimgxpp |= (flags & _PAGE_RW)? BPP_RW: BPP_RX;
 151                 bat[1].word[0] = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */
 152                 bat[1].word[1] = phys | wimgxpp;
 153 #ifndef CONFIG_KGDB /* want user access for breakpoints */
 154                 if (flags & _PAGE_USER)
 155 #endif
 156                         bat[1].bat.batu.vp = 1;
 157                 if (flags & _PAGE_GUARDED) {
 158                         /* G bit must be zero in IBATs */
 159                         bat[0].word[0] = bat[0].word[1] = 0;
 160                 } else {
 161                         /* make IBAT same as DBAT */
 162                         bat[0] = bat[1];
 163                 }
 164         } else {
 165                 /* 601 cpu */
 166                 if (bl > BL_8M)
 167                         bl = BL_8M;
 168                 wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE
 169                                    | _PAGE_COHERENT);
 170                 wimgxpp |= (flags & _PAGE_RW)?
 171                         ((flags & _PAGE_USER)? PP_RWRW: PP_RWXX): PP_RXRX;
 172                 bat->word[0] = virt | wimgxpp | 4;      /* Ks=0, Ku=1 */
 173                 bat->word[1] = phys | bl | 0x40;        /* V=1 */
 174         }
 175
 176         bat_addrs[index].start = virt;
 177         bat_addrs[index].limit = virt + ((bl + 1) << 17) - 1;
 178         bat_addrs[index].phys = phys;
 179 }
 180
 181 /*
 182  * Initialize the hash table and patch the instructions in hashtable.S.
 183  */
 184 void __init MMU_init_hw(void)
 185 {
 186         unsigned int hmask, mb, mb2;
 187         unsigned int n_hpteg, lg_n_hpteg;
 188
 189         extern unsigned int hash_page_patch_A[];
 190         extern unsigned int hash_page_patch_B[], hash_page_patch_C[];
 191         extern unsigned int hash_page[];
 192         extern unsigned int flush_hash_patch_A[], flush_hash_patch_B[];
 193
 194         if (!cpu_has_feature(CPU_FTR_HPTE_TABLE)) {
 195                 /*
 196                  * Put a blr (procedure return) instruction at the
 197                  * start of hash_page, since we can still get DSI
 198                  * exceptions on a 603.
 199                  */
 200                 hash_page[0] = 0x4e800020;
 201                 flush_icache_range((unsigned long) &hash_page[0],
 202                                    (unsigned long) &hash_page[1]);
 203                 return;
 204         }
 205
 206         if ( ppc_md.progress ) ppc_md.progress("hash:enter", 0x105);
 207
 208 #ifdef CONFIG_PPC64BRIDGE
 209 #define LG_HPTEG_SIZE   7               /* 128 bytes per HPTEG */
 210 #define SDR1_LOW_BITS   (lg_n_hpteg - 11)
 211 #define MIN_N_HPTEG     2048            /* min 256kB hash table */
 212 #else
 213 #define LG_HPTEG_SIZE   6               /* 64 bytes per HPTEG */
 214 #define SDR1_LOW_BITS   ((n_hpteg - 1) >> 10)
 215 #define MIN_N_HPTEG     1024            /* min 64kB hash table */
 216 #endif
 217
 218 #ifdef CONFIG_POWER4
 219         /* The hash table has already been allocated and initialized
 220            in prom.c */
 221         n_hpteg = Hash_size >> LG_HPTEG_SIZE;
 222         lg_n_hpteg = __ilog2(n_hpteg);
 223
 224         /* Remove the hash table from the available memory */
 225         if (Hash)
 226                 reserve_phys_mem(__pa(Hash), Hash_size);
 227
 228 #else /* CONFIG_POWER4 */
 229         /*
 230          * Allow 1 HPTE (1/8 HPTEG) for each page of memory.
 231          * This is less than the recommended amount, but then
 232          * Linux ain't AIX.
 233          */
 234         n_hpteg = total_memory / (PAGE_SIZE * 8);
 235         if (n_hpteg < MIN_N_HPTEG)
 236                 n_hpteg = MIN_N_HPTEG;
 237         lg_n_hpteg = __ilog2(n_hpteg);
 238         if (n_hpteg & (n_hpteg - 1)) {
 239                 ++lg_n_hpteg;           /* round up if not power of 2 */
 240                 n_hpteg = 1 << lg_n_hpteg;
 241         }
 242         Hash_size = n_hpteg << LG_HPTEG_SIZE;
 243
 244         /*
 245          * Find some memory for the hash table.
 246          */
 247         if ( ppc_md.progress ) ppc_md.progress("hash:find piece", 0x322);
 248         Hash = mem_pieces_find(Hash_size, Hash_size);
 249         cacheable_memzero(Hash, Hash_size);
 250         _SDR1 = __pa(Hash) | SDR1_LOW_BITS;
 251 #endif /* CONFIG_POWER4 */
 252
 253         Hash_end = (PTE *) ((unsigned long)Hash + Hash_size);
 254
 255         printk("Total memory = %ldMB; using %ldkB for hash table (at %p)\n",
 256                total_memory >> 20, Hash_size >> 10, Hash);
 257
 258
 259         /*
 260          * Patch up the instructions in hashtable.S:create_hpte
 261          */
 262         if ( ppc_md.progress ) ppc_md.progress("hash:patch", 0x345);
 263         Hash_mask = n_hpteg - 1;
 264         hmask = Hash_mask >> (16 - LG_HPTEG_SIZE);
 265         mb2 = mb = 32 - LG_HPTEG_SIZE - lg_n_hpteg;
 266         if (lg_n_hpteg > 16)
 267                 mb2 = 16 - LG_HPTEG_SIZE;
 268
 269         hash_page_patch_A[0] = (hash_page_patch_A[0] & ~0xffff)
 270                 | ((unsigned int)(Hash) >> 16);
 271         hash_page_patch_A[1] = (hash_page_patch_A[1] & ~0x7c0) | (mb << 6);
 272         hash_page_patch_A[2] = (hash_page_patch_A[2] & ~0x7c0) | (mb2 << 6);
 273         hash_page_patch_B[0] = (hash_page_patch_B[0] & ~0xffff) | hmask;
 274         hash_page_patch_C[0] = (hash_page_patch_C[0] & ~0xffff) | hmask;
 275
 276         /*
 277          * Ensure that the locations we've patched have been written
 278          * out from the data cache and invalidated in the instruction
 279          * cache, on those machines with split caches.
 280          */
 281         flush_icache_range((unsigned long) &hash_page_patch_A[0],
 282                            (unsigned long) &hash_page_patch_C[1]);
 283
 284         /*
 285          * Patch up the instructions in hashtable.S:flush_hash_page
 286          */
 287         flush_hash_patch_A[0] = (flush_hash_patch_A[0] & ~0xffff)
 288                 | ((unsigned int)(Hash) >> 16);
 289         flush_hash_patch_A[1] = (flush_hash_patch_A[1] & ~0x7c0) | (mb << 6);
 290         flush_hash_patch_A[2] = (flush_hash_patch_A[2] & ~0x7c0) | (mb2 << 6);
 291         flush_hash_patch_B[0] = (flush_hash_patch_B[0] & ~0xffff) | hmask;
 292         flush_icache_range((unsigned long) &flush_hash_patch_A[0],
 293                            (unsigned long) &flush_hash_patch_B[1]);
 294
 295         if ( ppc_md.progress ) ppc_md.progress("hash:done", 0x205);
 296 }