arch/ppc/syslib/ibm440gx_common.c

   1 /*
   2  * arch/ppc/kernel/ibm440gx_common.c
   3  *
   4  * PPC440GX system library
   5  *
   6  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
   7  * Copyright (c) 2003, 2004 Zultys Technologies
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  *
  14  */
  15 #include <linux/config.h>
  16 #include <linux/kernel.h>
  17 #include <linux/interrupt.h>
  18 #include <asm/ibm44x.h>
  19 #include <asm/mmu.h>
  20 #include <asm/processor.h>
  21 #include <syslib/ibm440gx_common.h>
  22
  23 /*
  24  * Calculate 440GX clocks
  25  */
  26 static inline u32 __fix_zero(u32 v, u32 def){
  27         return v ? v : def;
  28 }
  29
  30 void __init ibm440gx_get_clocks(struct ibm44x_clocks* p, unsigned int sys_clk,
  31         unsigned int ser_clk)
  32 {
  33         u32 pllc  = CPR_READ(DCRN_CPR_PLLC);
  34         u32 plld  = CPR_READ(DCRN_CPR_PLLD);
  35         u32 uart0 = SDR_READ(DCRN_SDR_UART0);
  36         u32 uart1 = SDR_READ(DCRN_SDR_UART1);
  37
  38         /* Dividers */
  39         u32 fbdv   = __fix_zero((plld >> 24) & 0x1f, 32);
  40         u32 fwdva  = __fix_zero((plld >> 16) & 0xf, 16);
  41         u32 fwdvb  = __fix_zero((plld >> 8) & 7, 8);
  42         u32 lfbdv  = __fix_zero(plld & 0x3f, 64);
  43         u32 pradv0 = __fix_zero((CPR_READ(DCRN_CPR_PRIMAD) >> 24) & 7, 8);
  44         u32 prbdv0 = __fix_zero((CPR_READ(DCRN_CPR_PRIMBD) >> 24) & 7, 8);
  45         u32 opbdv0 = __fix_zero((CPR_READ(DCRN_CPR_OPBD) >> 24) & 3, 4);
  46         u32 perdv0 = __fix_zero((CPR_READ(DCRN_CPR_PERD) >> 24) & 3, 4);
  47
  48         /* Input clocks for primary dividers */
  49         u32 clk_a, clk_b;
  50
  51         if (pllc & 0x40000000){
  52                 u32 m;
  53
  54                 /* Feedback path */
  55                 switch ((pllc >> 24) & 7){
  56                 case 0:
  57                         /* PLLOUTx */
  58                         m = ((pllc & 0x20000000) ? fwdvb : fwdva) * lfbdv;
  59                         break;
  60                 case 1:
  61                         /* CPU */
  62                         m = fwdva * pradv0;
  63                         break;
  64                 case 5:
  65                         /* PERClk */
  66                         m = fwdvb * prbdv0 * opbdv0 * perdv0;
  67                         break;
  68                 default:
  69                         printk(KERN_EMERG "invalid PLL feedback source\n");
  70                         goto bypass;
  71                 }
  72                 m *= fbdv;
  73                 p->vco = sys_clk * m;
  74                 clk_a = p->vco / fwdva;
  75                 clk_b = p->vco / fwdvb;
  76         }
  77         else {
  78 bypass:
  79                 /* Bypass system PLL */
  80                 p->vco = 0;
  81                 clk_a = clk_b = sys_clk;
  82         }
  83
  84         p->cpu = clk_a / pradv0;
  85         p->plb = clk_b / prbdv0;
  86         p->opb = p->plb / opbdv0;
  87         p->ebc = p->opb / perdv0;
  88
  89         /* UARTs clock */
  90         if (uart0 & 0x00800000)
  91                 p->uart0 = ser_clk;
  92         else
  93                 p->uart0 = p->plb / __fix_zero(uart0 & 0xff, 256);
  94
  95         if (uart1 & 0x00800000)
  96                 p->uart1 = ser_clk;
  97         else
  98                 p->uart1 = p->plb / __fix_zero(uart1 & 0xff, 256);
  99 }
 100
 101 /* Issue L2C diagnostic command */
 102 static inline u32 l2c_diag(u32 addr)
 103 {
 104         mtdcr(DCRN_L2C0_ADDR, addr);
 105         mtdcr(DCRN_L2C0_CMD, L2C_CMD_DIAG);
 106         while (!(mfdcr(DCRN_L2C0_SR) & L2C_SR_CC)) ;
 107         return mfdcr(DCRN_L2C0_DATA);
 108 }
 109
 110 static irqreturn_t l2c_error_handler(int irq, void* dev, struct pt_regs* regs)
 111 {
 112         u32 sr = mfdcr(DCRN_L2C0_SR);
 113         if (sr & L2C_SR_CPE){
 114                 /* Read cache trapped address */
 115                 u32 addr = l2c_diag(0x42000000);
 116                 printk(KERN_EMERG "L2C: Cache Parity Error, addr[16:26] = 0x%08x\n", addr);
 117         }
 118         if (sr & L2C_SR_TPE){
 119                 /* Read tag trapped address */
 120                 u32 addr = l2c_diag(0x82000000) >> 16;
 121                 printk(KERN_EMERG "L2C: Tag Parity Error, addr[16:26] = 0x%08x\n", addr);
 122         }
 123
 124         /* Clear parity errors */
 125         if (sr & (L2C_SR_CPE | L2C_SR_TPE)){
 126                 mtdcr(DCRN_L2C0_ADDR, 0);
 127                 mtdcr(DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
 128         } else
 129                 printk(KERN_EMERG "L2C: LRU error\n");
 130
 131         return IRQ_HANDLED;
 132 }
 133
 134 /* Enable L2 cache */
 135 void __init ibm440gx_l2c_enable(void){
 136         u32 r;
 137         unsigned long flags;
 138
 139         /* Install error handler */
 140         if (request_irq(87, l2c_error_handler, SA_INTERRUPT, "L2C", 0) < 0){
 141                 printk(KERN_ERR "Cannot install L2C error handler, cache is not enabled\n");
 142                 return;
 143         }
 144
 145         local_irq_save(flags);
 146         asm volatile ("sync" ::: "memory");
 147
 148         /* Disable SRAM */
 149         mtdcr(DCRN_SRAM0_DPC,   mfdcr(DCRN_SRAM0_DPC)   & ~SRAM_DPC_ENABLE);
 150         mtdcr(DCRN_SRAM0_SB0CR, mfdcr(DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK);
 151         mtdcr(DCRN_SRAM0_SB1CR, mfdcr(DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK);
 152         mtdcr(DCRN_SRAM0_SB2CR, mfdcr(DCRN_SRAM0_SB2CR) & ~SRAM_SBCR_BU_MASK);
 153         mtdcr(DCRN_SRAM0_SB3CR, mfdcr(DCRN_SRAM0_SB3CR) & ~SRAM_SBCR_BU_MASK);
 154
 155         /* Enable L2_MODE without ICU/DCU */
 156         r = mfdcr(DCRN_L2C0_CFG) & ~(L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_SS_MASK);
 157         r |= L2C_CFG_L2M | L2C_CFG_SS_256;
 158         mtdcr(DCRN_L2C0_CFG, r);
 159
 160         mtdcr(DCRN_L2C0_ADDR, 0);
 161
 162         /* Hardware Clear Command */
 163         mtdcr(DCRN_L2C0_CMD, L2C_CMD_HCC);
 164         while (!(mfdcr(DCRN_L2C0_SR) & L2C_SR_CC)) ;
 165
 166         /* Clear Cache Parity and Tag Errors */
 167         mtdcr(DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
 168
 169         /* Enable 64G snoop region starting at 0 */
 170         r = mfdcr(DCRN_L2C0_SNP0) & ~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK);
 171         r |= L2C_SNP_SSR_32G | L2C_SNP_ESR;
 172         mtdcr(DCRN_L2C0_SNP0, r);
 173
 174         r = mfdcr(DCRN_L2C0_SNP1) & ~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK);
 175         r |= 0x80000000 | L2C_SNP_SSR_32G | L2C_SNP_ESR;
 176         mtdcr(DCRN_L2C0_SNP1, r);
 177
 178         asm volatile ("sync" ::: "memory");
 179
 180         /* Enable ICU/DCU ports */
 181         r = mfdcr(DCRN_L2C0_CFG);
 182         r &= ~(L2C_CFG_DCW_MASK | L2C_CFG_PMUX_MASK | L2C_CFG_PMIM | L2C_CFG_TPEI
 183                 | L2C_CFG_CPEI | L2C_CFG_NAM | L2C_CFG_NBRM);
 184         r |= L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_TPC | L2C_CFG_CPC | L2C_CFG_FRAN
 185                 | L2C_CFG_CPIM | L2C_CFG_TPIM | L2C_CFG_LIM | L2C_CFG_SMCM;
 186         mtdcr(DCRN_L2C0_CFG, r);
 187
 188         asm volatile ("sync; isync" ::: "memory");
 189         local_irq_restore(flags);
 190 }
 191
 192 /* Disable L2 cache */
 193 void __init ibm440gx_l2c_disable(void){
 194         u32 r;
 195         unsigned long flags;
 196
 197         local_irq_save(flags);
 198         asm volatile ("sync" ::: "memory");
 199
 200         /* Disable L2C mode */
 201         r = mfdcr(DCRN_L2C0_CFG) & ~(L2C_CFG_L2M | L2C_CFG_ICU | L2C_CFG_DCU);
 202         mtdcr(DCRN_L2C0_CFG, r);
 203
 204         /* Enable SRAM */
 205         mtdcr(DCRN_SRAM0_DPC, mfdcr(DCRN_SRAM0_DPC) | SRAM_DPC_ENABLE);
 206         mtdcr(DCRN_SRAM0_SB0CR,
 207               SRAM_SBCR_BAS0 | SRAM_SBCR_BS_64KB | SRAM_SBCR_BU_RW);
 208         mtdcr(DCRN_SRAM0_SB1CR,
 209               SRAM_SBCR_BAS1 | SRAM_SBCR_BS_64KB | SRAM_SBCR_BU_RW);
 210         mtdcr(DCRN_SRAM0_SB2CR,
 211               SRAM_SBCR_BAS2 | SRAM_SBCR_BS_64KB | SRAM_SBCR_BU_RW);
 212         mtdcr(DCRN_SRAM0_SB3CR,
 213               SRAM_SBCR_BAS3 | SRAM_SBCR_BS_64KB | SRAM_SBCR_BU_RW);
 214
 215         asm volatile ("sync; isync" ::: "memory");
 216         local_irq_restore(flags);
 217 }
 218
 219 void __init ibm440gx_l2c_setup(struct ibm44x_clocks* p)
 220 {
 221         /* Disable L2C on rev.A, rev.B and 800MHz version of rev.C,
 222            enable it on all other revisions
 223          */
 224         u32 pvr = mfspr(SPRN_PVR);
 225         if (pvr == PVR_440GX_RA || pvr == PVR_440GX_RB ||
 226             (pvr == PVR_440GX_RC && p->cpu > 667000000))
 227                 ibm440gx_l2c_disable();
 228         else
 229                 ibm440gx_l2c_enable();
 230 }
 231
 232 int __init ibm440gx_get_eth_grp(void)
 233 {
 234         return (SDR_READ(DCRN_SDR_PFC1) & DCRN_SDR_PFC1_EPS) >> DCRN_SDR_PFC1_EPS_SHIFT;
 235 }
 236
 237 void __init ibm440gx_set_eth_grp(int group)
 238 {
 239         SDR_WRITE(DCRN_SDR_PFC1, (SDR_READ(DCRN_SDR_PFC1) & ~DCRN_SDR_PFC1_EPS) | (group << DCRN_SDR_PFC1_EPS_SHIFT));
 240 }
 241
 242 void __init ibm440gx_tah_enable(void)
 243 {
 244         /* Enable TAH0 and TAH1 */
 245         SDR_WRITE(DCRN_SDR_MFR,SDR_READ(DCRN_SDR_MFR) &
 246                         ~DCRN_SDR_MFR_TAH0);
 247         SDR_WRITE(DCRN_SDR_MFR,SDR_READ(DCRN_SDR_MFR) &
 248                         ~DCRN_SDR_MFR_TAH1);
 249 }
 250
 251 int ibm440gx_show_cpuinfo(struct seq_file *m){
 252
 253         u32 l2c_cfg = mfdcr(DCRN_L2C0_CFG);
 254         const char* s;
 255         if (l2c_cfg & L2C_CFG_L2M){
 256             switch (l2c_cfg & (L2C_CFG_ICU | L2C_CFG_DCU)){
 257                 case L2C_CFG_ICU: s = "I-Cache only";    break;
 258                 case L2C_CFG_DCU: s = "D-Cache only";    break;
 259                 default:          s = "I-Cache/D-Cache"; break;
 260             }
 261         }
 262         else
 263             s = "disabled";
 264
 265         seq_printf(m, "L2-Cache\t: %s (0x%08x 0x%08x)\n", s,
 266             l2c_cfg, mfdcr(DCRN_L2C0_SR));
 267
 268         return 0;
 269 }
 270