arch/ppc/syslib/m8xx_setup.c

   1 /*
   2  *  arch/ppc/kernel/setup.c
   3  *
   4  *  Copyright (C) 1995  Linus Torvalds
   5  *  Adapted from 'alpha' version by Gary Thomas
   6  *  Modified by Cort Dougan (cort@cs.nmt.edu)
   7  *  Modified for MBX using prep/chrp/pmac functions by Dan (dmalek@jlc.net)
   8  *  Further modified for generic 8xx by Dan.
   9  */
  10
  11 /*
  12  * bootup setup stuff..
  13  */
  14
  15 #include <linux/config.h>
  16 #include <linux/errno.h>
  17 #include <linux/sched.h>
  18 #include <linux/kernel.h>
  19 #include <linux/mm.h>
  20 #include <linux/stddef.h>
  21 #include <linux/unistd.h>
  22 #include <linux/ptrace.h>
  23 #include <linux/slab.h>
  24 #include <linux/user.h>
  25 #include <linux/a.out.h>
  26 #include <linux/tty.h>
  27 #include <linux/major.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/reboot.h>
  30 #include <linux/init.h>
  31 #include <linux/initrd.h>
  32 #include <linux/ioport.h>
  33 #include <linux/bootmem.h>
  34 #include <linux/seq_file.h>
  35 #include <linux/root_dev.h>
  36
  37 #include <asm/mmu.h>
  38 #include <asm/reg.h>
  39 #include <asm/residual.h>
  40 #include <asm/io.h>
  41 #include <asm/pgtable.h>
  42 #include <asm/mpc8xx.h>
  43 #include <asm/8xx_immap.h>
  44 #include <asm/machdep.h>
  45 #include <asm/bootinfo.h>
  46 #include <asm/time.h>
  47 #include <asm/xmon.h>
  48
  49 #include "ppc8xx_pic.h"
  50
  51 static int m8xx_set_rtc_time(unsigned long time);
  52 static unsigned long m8xx_get_rtc_time(void);
  53 void m8xx_calibrate_decr(void);
  54
  55 unsigned char __res[sizeof(bd_t)];
  56
  57 extern void m8xx_ide_init(void);
  58
  59 extern unsigned long find_available_memory(void);
  60 extern void m8xx_cpm_reset(uint cpm_page);
  61 extern void m8xx_wdt_handler_install(bd_t *bp);
  62 extern void rpxfb_alloc_pages(void);
  63 extern void cpm_interrupt_init(void);
  64
  65 void __attribute__ ((weak))
  66 board_init(void)
  67 {
  68 }
  69
  70 void __init
  71 m8xx_setup_arch(void)
  72 {
  73         int     cpm_page;
  74
  75         cpm_page = (int) alloc_bootmem_pages(PAGE_SIZE);
  76
  77         /* Reset the Communication Processor Module.
  78         */
  79         m8xx_cpm_reset(cpm_page);
  80
  81 #ifdef CONFIG_FB_RPX
  82         rpxfb_alloc_pages();
  83 #endif
  84
  85 #ifdef notdef
  86         ROOT_DEV = Root_HDA1; /* hda1 */
  87 #endif
  88
  89 #ifdef CONFIG_BLK_DEV_INITRD
  90 #if 0
  91         ROOT_DEV = Root_FD0; /* floppy */
  92         rd_prompt = 1;
  93         rd_doload = 1;
  94         rd_image_start = 0;
  95 #endif
  96 #if 0   /* XXX this may need to be updated for the new bootmem stuff,
  97            or possibly just deleted (see set_phys_avail() in init.c).
  98            - paulus. */
  99         /* initrd_start and size are setup by boot/head.S and kernel/head.S */
 100         if ( initrd_start )
 101         {
 102                 if (initrd_end > *memory_end_p)
 103                 {
 104                         printk("initrd extends beyond end of memory "
 105                                "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
 106                                initrd_end,*memory_end_p);
 107                         initrd_start = 0;
 108                 }
 109         }
 110 #endif
 111 #endif
 112         board_init();
 113 }
 114
 115 void
 116 abort(void)
 117 {
 118 #ifdef CONFIG_XMON
 119         xmon(0);
 120 #endif
 121         machine_restart(NULL);
 122
 123         /* not reached */
 124         for (;;);
 125 }
 126
 127 /* A place holder for time base interrupts, if they are ever enabled. */
 128 irqreturn_t timebase_interrupt(int irq, void * dev, struct pt_regs * regs)
 129 {
 130         printk ("timebase_interrupt()\n");
 131
 132         return IRQ_HANDLED;
 133 }
 134
 135 static struct irqaction tbint_irqaction = {
 136         .handler = timebase_interrupt,
 137         .mask = CPU_MASK_NONE,
 138         .name = "tbint",
 139 };
 140
 141 /* The decrementer counts at the system (internal) clock frequency divided by
 142  * sixteen, or external oscillator divided by four.  We force the processor
 143  * to use system clock divided by sixteen.
 144  */
 145 void __init m8xx_calibrate_decr(void)
 146 {
 147         bd_t    *binfo = (bd_t *)__res;
 148         int freq, fp, divisor;
 149
 150         /* Unlock the SCCR. */
 151         ((volatile immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk = ~KAPWR_KEY;
 152         ((volatile immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk = KAPWR_KEY;
 153
 154         /* Force all 8xx processors to use divide by 16 processor clock. */
 155         ((volatile immap_t *)IMAP_ADDR)->im_clkrst.car_sccr |= 0x02000000;
 156
 157         /* Processor frequency is MHz.
 158          * The value 'fp' is the number of decrementer ticks per second.
 159          */
 160         fp = binfo->bi_intfreq / 16;
 161         freq = fp*60;   /* try to make freq/1e6 an integer */
 162         divisor = 60;
 163         printk("Decrementer Frequency = %d/%d\n", freq, divisor);
 164         tb_ticks_per_jiffy = freq / HZ / divisor;
 165         tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
 166
 167         /* Perform some more timer/timebase initialization.  This used
 168          * to be done elsewhere, but other changes caused it to get
 169          * called more than once....that is a bad thing.
 170          *
 171          * First, unlock all of the registers we are going to modify.
 172          * To protect them from corruption during power down, registers
 173          * that are maintained by keep alive power are "locked".  To
 174          * modify these registers we have to write the key value to
 175          * the key location associated with the register.
 176          * Some boards power up with these unlocked, while others
 177          * are locked.  Writing anything (including the unlock code?)
 178          * to the unlocked registers will lock them again.  So, here
 179          * we guarantee the registers are locked, then we unlock them
 180          * for our use.
 181          */
 182         ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_tbscrk = ~KAPWR_KEY;
 183         ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_rtcsck = ~KAPWR_KEY;
 184         ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk    = ~KAPWR_KEY;
 185         ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_tbscrk =  KAPWR_KEY;
 186         ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_rtcsck =  KAPWR_KEY;
 187         ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk    =  KAPWR_KEY;
 188
 189         /* Disable the RTC one second and alarm interrupts. */
 190         ((volatile immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc &=
 191                                                 ~(RTCSC_SIE | RTCSC_ALE);
 192         /* Enable the RTC */
 193         ((volatile immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc |=
 194                                                 (RTCSC_RTF | RTCSC_RTE);
 195
 196         /* Enabling the decrementer also enables the timebase interrupts
 197          * (or from the other point of view, to get decrementer interrupts
 198          * we have to enable the timebase).  The decrementer interrupt
 199          * is wired into the vector table, nothing to do here for that.
 200          */
 201         ((volatile immap_t *)IMAP_ADDR)->im_sit.sit_tbscr =
 202                                 ((mk_int_int_mask(DEC_INTERRUPT) << 8) |
 203                                          (TBSCR_TBF | TBSCR_TBE));
 204
 205         if (setup_irq(DEC_INTERRUPT, &tbint_irqaction))
 206                 panic("Could not allocate timer IRQ!");
 207
 208 #ifdef CONFIG_8xx_WDT
 209         /* Install watchdog timer handler early because it might be
 210          * already enabled by the bootloader
 211          */
 212         m8xx_wdt_handler_install(binfo);
 213 #endif
 214 }
 215
 216 /* The RTC on the MPC8xx is an internal register.
 217  * We want to protect this during power down, so we need to unlock,
 218  * modify, and re-lock.
 219  */
 220 static int
 221 m8xx_set_rtc_time(unsigned long time)
 222 {
 223         ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_rtck = KAPWR_KEY;
 224         ((volatile immap_t *)IMAP_ADDR)->im_sit.sit_rtc = time;
 225         ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_rtck = ~KAPWR_KEY;
 226         return(0);
 227 }
 228
 229 static unsigned long
 230 m8xx_get_rtc_time(void)
 231 {
 232         /* Get time from the RTC. */
 233         return((unsigned long)(((immap_t *)IMAP_ADDR)->im_sit.sit_rtc));
 234 }
 235
 236 static void
 237 m8xx_restart(char *cmd)
 238 {
 239         __volatile__ unsigned char dummy;
 240
 241         local_irq_disable();
 242         ((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr |= 0x00000080;
 243
 244         /* Clear the ME bit in MSR to cause checkstop on machine check
 245         */
 246         mtmsr(mfmsr() & ~0x1000);
 247
 248         dummy = ((immap_t *)IMAP_ADDR)->im_clkrst.res[0];
 249         printk("Restart failed\n");
 250         while(1);
 251 }
 252
 253 static void
 254 m8xx_power_off(void)
 255 {
 256    m8xx_restart(NULL);
 257 }
 258
 259 static void
 260 m8xx_halt(void)
 261 {
 262    m8xx_restart(NULL);
 263 }
 264
 265
 266 static int
 267 m8xx_show_percpuinfo(struct seq_file *m, int i)
 268 {
 269         bd_t    *bp;
 270
 271         bp = (bd_t *)__res;
 272
 273         seq_printf(m, "clock\t\t: %ldMHz\n"
 274                    "bus clock\t: %ldMHz\n",
 275                    bp->bi_intfreq / 1000000,
 276                    bp->bi_busfreq / 1000000);
 277
 278         return 0;
 279 }
 280
 281 #ifdef CONFIG_PCI
 282 static struct irqaction mbx_i8259_irqaction = {
 283         .handler = mbx_i8259_action,
 284         .mask = CPU_MASK_NONE,
 285         .name = "i8259 cascade",
 286 };
 287 #endif
 288
 289 /* Initialize the internal interrupt controller.  The number of
 290  * interrupts supported can vary with the processor type, and the
 291  * 82xx family can have up to 64.
 292  * External interrupts can be either edge or level triggered, and
 293  * need to be initialized by the appropriate driver.
 294  */
 295 static void __init
 296 m8xx_init_IRQ(void)
 297 {
 298         int i;
 299
 300         for (i = SIU_IRQ_OFFSET ; i < SIU_IRQ_OFFSET + NR_SIU_INTS ; i++)
 301                 irq_desc[i].handler = &ppc8xx_pic;
 302
 303         cpm_interrupt_init();
 304
 305 #if defined(CONFIG_PCI)
 306         for (i = I8259_IRQ_OFFSET ; i < I8259_IRQ_OFFSET + NR_8259_INTS ; i++)
 307                 irq_desc[i].handler = &i8259_pic;
 308
 309         i8259_pic_irq_offset = I8259_IRQ_OFFSET;
 310         i8259_init(0);
 311
 312         /* The i8259 cascade interrupt must be level sensitive. */
 313         ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel &=
 314                 ~(0x80000000 >> ISA_BRIDGE_INT);
 315
 316         if (setup_irq(ISA_BRIDGE_INT, &mbx_i8259_irqaction))
 317                 enable_irq(ISA_BRIDGE_INT);
 318 #endif  /* CONFIG_PCI */
 319 }
 320
 321 /* -------------------------------------------------------------------- */
 322
 323 /*
 324  * This is a big hack right now, but it may turn into something real
 325  * someday.
 326  *
 327  * For the 8xx boards (at this time anyway), there is nothing to initialize
 328  * associated the PROM.  Rather than include all of the prom.c
 329  * functions in the image just to get prom_init, all we really need right
 330  * now is the initialization of the physical memory region.
 331  */
 332 static unsigned long __init
 333 m8xx_find_end_of_memory(void)
 334 {
 335         bd_t    *binfo;
 336         extern unsigned char __res[];
 337
 338         binfo = (bd_t *)__res;
 339
 340         return binfo->bi_memsize;
 341 }
 342
 343 /*
 344  * Now map in some of the I/O space that is generically needed
 345  * or shared with multiple devices.
 346  * All of this fits into the same 4Mbyte region, so it only
 347  * requires one page table page.  (or at least it used to  -- paulus)
 348  */
 349 static void __init
 350 m8xx_map_io(void)
 351 {
 352         io_block_mapping(IMAP_ADDR, IMAP_ADDR, IMAP_SIZE, _PAGE_IO);
 353 #ifdef CONFIG_MBX
 354         io_block_mapping(NVRAM_ADDR, NVRAM_ADDR, NVRAM_SIZE, _PAGE_IO);
 355         io_block_mapping(MBX_CSR_ADDR, MBX_CSR_ADDR, MBX_CSR_SIZE, _PAGE_IO);
 356         io_block_mapping(PCI_CSR_ADDR, PCI_CSR_ADDR, PCI_CSR_SIZE, _PAGE_IO);
 357
 358         /* Map some of the PCI/ISA I/O space to get the IDE interface.
 359         */
 360         io_block_mapping(PCI_ISA_IO_ADDR, PCI_ISA_IO_ADDR, 0x4000, _PAGE_IO);
 361         io_block_mapping(PCI_IDE_ADDR, PCI_IDE_ADDR, 0x4000, _PAGE_IO);
 362 #endif
 363 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
 364         io_block_mapping(RPX_CSR_ADDR, RPX_CSR_ADDR, RPX_CSR_SIZE, _PAGE_IO);
 365 #if !defined(CONFIG_PCI)
 366         io_block_mapping(_IO_BASE,_IO_BASE,_IO_BASE_SIZE, _PAGE_IO);
 367 #endif
 368 #endif
 369 #if defined(CONFIG_HTDMSOUND) || defined(CONFIG_RPXTOUCH) || defined(CONFIG_FB_RPX)
 370         io_block_mapping(HIOX_CSR_ADDR, HIOX_CSR_ADDR, HIOX_CSR_SIZE, _PAGE_IO);
 371 #endif
 372 #ifdef CONFIG_FADS
 373         io_block_mapping(BCSR_ADDR, BCSR_ADDR, BCSR_SIZE, _PAGE_IO);
 374 #endif
 375 #ifdef CONFIG_PCI
 376         io_block_mapping(PCI_CSR_ADDR, PCI_CSR_ADDR, PCI_CSR_SIZE, _PAGE_IO);
 377 #endif
 378 #if defined(CONFIG_NETTA)
 379         io_block_mapping(_IO_BASE,_IO_BASE,_IO_BASE_SIZE, _PAGE_IO);
 380 #endif
 381 }
 382
 383 void __init
 384 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 385                 unsigned long r6, unsigned long r7)
 386 {
 387         parse_bootinfo(find_bootinfo());
 388
 389         if ( r3 )
 390                 memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
 391
 392 #ifdef CONFIG_PCI
 393         m8xx_setup_pci_ptrs();
 394 #endif
 395
 396 #ifdef CONFIG_BLK_DEV_INITRD
 397         /* take care of initrd if we have one */
 398         if ( r4 )
 399         {
 400                 initrd_start = r4 + KERNELBASE;
 401                 initrd_end = r5 + KERNELBASE;
 402         }
 403 #endif /* CONFIG_BLK_DEV_INITRD */
 404         /* take care of cmd line */
 405         if ( r6 )
 406         {
 407                 *(char *)(r7+KERNELBASE) = 0;
 408                 strcpy(cmd_line, (char *)(r6+KERNELBASE));
 409         }
 410
 411         ppc_md.setup_arch               = m8xx_setup_arch;
 412         ppc_md.show_percpuinfo          = m8xx_show_percpuinfo;
 413         ppc_md.irq_canonicalize = NULL;
 414         ppc_md.init_IRQ                 = m8xx_init_IRQ;
 415         ppc_md.get_irq                  = m8xx_get_irq;
 416         ppc_md.init                     = NULL;
 417
 418         ppc_md.restart                  = m8xx_restart;
 419         ppc_md.power_off                = m8xx_power_off;
 420         ppc_md.halt                     = m8xx_halt;
 421
 422         ppc_md.time_init                = NULL;
 423         ppc_md.set_rtc_time             = m8xx_set_rtc_time;
 424         ppc_md.get_rtc_time             = m8xx_get_rtc_time;
 425         ppc_md.calibrate_decr           = m8xx_calibrate_decr;
 426
 427         ppc_md.find_end_of_memory       = m8xx_find_end_of_memory;
 428         ppc_md.setup_io_mappings        = m8xx_map_io;
 429
 430 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
 431         m8xx_ide_init();
 432 #endif
 433 }