arch/ppc/syslib/mpc52xx_pci.h

   1 /*
   2  * arch/ppc/syslib/mpc52xx_pci.h
   3  *
   4  * PCI Include file the Freescale MPC52xx embedded cpu chips
   5  *
   6  *
   7  * Maintainer : Sylvain Munaut <tnt@246tNt.com>
   8  *
   9  * Inspired from code written by Dale Farnsworth <dfarnsworth@mvista.com>
  10  * for the 2.4 kernel.
  11  *
  12  * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
  13  * Copyright (C) 2003 MontaVista, Software, Inc.
  14  *
  15  * This file is licensed under the terms of the GNU General Public License
  16  * version 2. This program is licensed "as is" without any warranty of any
  17  * kind, whether express or implied.
  18  */
  19
  20 #ifndef __SYSLIB_MPC52xx_PCI_H__
  21 #define __SYSLIB_MPC52xx_PCI_H__
  22
  23 /* ======================================================================== */
  24 /* PCI windows config                                                       */
  25 /* ======================================================================== */
  26
  27 /*
  28  * Master windows : MPC52xx -> PCI
  29  *
  30  *  0x80000000 -> 0x9FFFFFFF       PCI Mem prefetchable          IW0BTAR
  31  *  0xA0000000 -> 0xAFFFFFFF       PCI Mem                       IW1BTAR
  32  *  0xB0000000 -> 0xB0FFFFFF       PCI IO                        IW2BTAR
  33  *
  34  * Slave windows  : PCI -> MPC52xx
  35  *
  36  *  0xF0000000 -> 0xF003FFFF       MPC52xx MBAR                  TBATR0
  37  *  0x00000000 -> 0x3FFFFFFF       MPC52xx local memory          TBATR1
  38  */
  39
  40 #define MPC52xx_PCI_MEM_OFFSET  0x00000000      /* Offset for MEM MMIO */
  41
  42 #define MPC52xx_PCI_MEM_START   0x80000000
  43 #define MPC52xx_PCI_MEM_SIZE    0x20000000
  44 #define MPC52xx_PCI_MEM_STOP    (MPC52xx_PCI_MEM_START+MPC52xx_PCI_MEM_SIZE-1)
  45
  46 #define MPC52xx_PCI_MMIO_START  0xa0000000
  47 #define MPC52xx_PCI_MMIO_SIZE   0x10000000
  48 #define MPC52xx_PCI_MMIO_STOP   (MPC52xx_PCI_MMIO_START+MPC52xx_PCI_MMIO_SIZE-1)
  49
  50 #define MPC52xx_PCI_IO_BASE     0xb0000000
  51
  52 #define MPC52xx_PCI_IO_START    0x00000000
  53 #define MPC52xx_PCI_IO_SIZE     0x01000000
  54 #define MPC52xx_PCI_IO_STOP     (MPC52xx_PCI_IO_START+MPC52xx_PCI_IO_SIZE-1)
  55
  56
  57 #define MPC52xx_PCI_TARGET_IO   MPC52xx_MBAR
  58 #define MPC52xx_PCI_TARGET_MEM  0x00000000
  59
  60
  61 /* ======================================================================== */
  62 /* Structures mapping & Defines for PCI Unit                                */
  63 /* ======================================================================== */
  64
  65 #define MPC52xx_PCI_GSCR_BM             0x40000000
  66 #define MPC52xx_PCI_GSCR_PE             0x20000000
  67 #define MPC52xx_PCI_GSCR_SE             0x10000000
  68 #define MPC52xx_PCI_GSCR_XLB2PCI_MASK   0x07000000
  69 #define MPC52xx_PCI_GSCR_XLB2PCI_SHIFT  24
  70 #define MPC52xx_PCI_GSCR_IPG2PCI_MASK   0x00070000
  71 #define MPC52xx_PCI_GSCR_IPG2PCI_SHIFT  16
  72 #define MPC52xx_PCI_GSCR_BME            0x00004000
  73 #define MPC52xx_PCI_GSCR_PEE            0x00002000
  74 #define MPC52xx_PCI_GSCR_SEE            0x00001000
  75 #define MPC52xx_PCI_GSCR_PR             0x00000001
  76
  77
  78 #define MPC52xx_PCI_IWBTAR_TRANSLATION(proc_ad,pci_ad,size)       \
  79                 ( ( (proc_ad) & 0xff000000 )                    | \
  80                   ( (((size) - 1) >> 8) & 0x00ff0000 )          | \
  81                   ( ((pci_ad) >> 16) & 0x0000ff00 ) )
  82
  83 #define MPC52xx_PCI_IWCR_PACK(win0,win1,win2)   (((win0) << 24) | \
  84                                                  ((win1) << 16) | \
  85                                                  ((win2) <<  8))
  86
  87 #define MPC52xx_PCI_IWCR_DISABLE        0x0
  88 #define MPC52xx_PCI_IWCR_ENABLE         0x1
  89 #define MPC52xx_PCI_IWCR_READ           0x0
  90 #define MPC52xx_PCI_IWCR_READ_LINE      0x2
  91 #define MPC52xx_PCI_IWCR_READ_MULTI     0x4
  92 #define MPC52xx_PCI_IWCR_MEM            0x0
  93 #define MPC52xx_PCI_IWCR_IO             0x8
  94
  95 #define MPC52xx_PCI_TCR_P               0x01000000
  96 #define MPC52xx_PCI_TCR_LD              0x00010000
  97
  98 #define MPC52xx_PCI_TBATR_DISABLE       0x0
  99 #define MPC52xx_PCI_TBATR_ENABLE        0x1
 100
 101
 102 #ifndef __ASSEMBLY__
 103
 104 struct mpc52xx_pci {
 105         u32     idr;            /* PCI + 0x00 */
 106         u32     scr;            /* PCI + 0x04 */
 107         u32     ccrir;          /* PCI + 0x08 */
 108         u32     cr1;            /* PCI + 0x0C */
 109         u32     bar0;           /* PCI + 0x10 */
 110         u32     bar1;           /* PCI + 0x14 */
 111         u8      reserved1[16];  /* PCI + 0x18 */
 112         u32     ccpr;           /* PCI + 0x28 */
 113         u32     sid;            /* PCI + 0x2C */
 114         u32     erbar;          /* PCI + 0x30 */
 115         u32     cpr;            /* PCI + 0x34 */
 116         u8      reserved2[4];   /* PCI + 0x38 */
 117         u32     cr2;            /* PCI + 0x3C */
 118         u8      reserved3[32];  /* PCI + 0x40 */
 119         u32     gscr;           /* PCI + 0x60 */
 120         u32     tbatr0;         /* PCI + 0x64 */
 121         u32     tbatr1;         /* PCI + 0x68 */
 122         u32     tcr;            /* PCI + 0x6C */
 123         u32     iw0btar;        /* PCI + 0x70 */
 124         u32     iw1btar;        /* PCI + 0x74 */
 125         u32     iw2btar;        /* PCI + 0x78 */
 126         u8      reserved4[4];   /* PCI + 0x7C */
 127         u32     iwcr;           /* PCI + 0x80 */
 128         u32     icr;            /* PCI + 0x84 */
 129         u32     isr;            /* PCI + 0x88 */
 130         u32     arb;            /* PCI + 0x8C */
 131         u8      reserved5[104]; /* PCI + 0x90 */
 132         u32     car;            /* PCI + 0xF8 */
 133         u8      reserved6[4];   /* PCI + 0xFC */
 134 };
 135
 136 #endif  /* __ASSEMBLY__ */
 137
 138
 139 #endif  /* __SYSLIB_MPC52xx_PCI_H__ */