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[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / arch / ppc / syslib / mpc85xx_devices.c
bloba231795ee26f0a37cc228d51a76a27c314240481
1 /*
2 * arch/ppc/platforms/85xx/mpc85xx_devices.c
3 *
4 * MPC85xx Device descriptions
5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com>
7 *
8 * Copyright 2005 Freescale Semiconductor Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/device.h>
19 #include <linux/serial_8250.h>
20 #include <linux/fsl_devices.h>
21 #include <asm/mpc85xx.h>
22 #include <asm/irq.h>
23 #include <asm/ppc_sys.h>
24
25 /* We use offsets for IORESOURCE_MEM since we do not know at compile time
26 * what CCSRBAR is, will get fixed up by mach_mpc85xx_fixup
27 */
28
29 static struct gianfar_platform_data mpc85xx_tsec1_pdata = {
30 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
31 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
32 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
33 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
34 };
35
36 static struct gianfar_platform_data mpc85xx_tsec2_pdata = {
37 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
38 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
39 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
40 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
41 };
42
43 static struct gianfar_platform_data mpc85xx_fec_pdata = {
44 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
45 };
46
47 static struct fsl_i2c_platform_data mpc85xx_fsl_i2c_pdata = {
48 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
49 };
50
51 static struct plat_serial8250_port serial_platform_data[] = {
52 [0] = {
53 .mapbase = 0x4500,
54 .irq = MPC85xx_IRQ_DUART,
55 .iotype = UPIO_MEM,
56 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
57 },
58 [1] = {
59 .mapbase = 0x4600,
60 .irq = MPC85xx_IRQ_DUART,
61 .iotype = UPIO_MEM,
62 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
63 },
64 };
65
66 struct platform_device ppc_sys_platform_devices[] = {
67 [MPC85xx_TSEC1] = {
68 .name = "fsl-gianfar",
69 .id = 1,
70 .dev.platform_data = &mpc85xx_tsec1_pdata,
71 .num_resources = 4,
72 .resource = (struct resource[]) {
73 {
74 .start = MPC85xx_ENET1_OFFSET,
75 .end = MPC85xx_ENET1_OFFSET +
76 MPC85xx_ENET1_SIZE - 1,
77 .flags = IORESOURCE_MEM,
78 },
79 {
80 .name = "tx",
81 .start = MPC85xx_IRQ_TSEC1_TX,
82 .end = MPC85xx_IRQ_TSEC1_TX,
83 .flags = IORESOURCE_IRQ,
84 },
85 {
86 .name = "rx",
87 .start = MPC85xx_IRQ_TSEC1_RX,
88 .end = MPC85xx_IRQ_TSEC1_RX,
89 .flags = IORESOURCE_IRQ,
90 },
91 {
92 .name = "error",
93 .start = MPC85xx_IRQ_TSEC1_ERROR,
94 .end = MPC85xx_IRQ_TSEC1_ERROR,
95 .flags = IORESOURCE_IRQ,
96 },
97 },
98 },
99 [MPC85xx_TSEC2] = {
100 .name = "fsl-gianfar",
101 .id = 2,
102 .dev.platform_data = &mpc85xx_tsec2_pdata,
103 .num_resources = 4,
104 .resource = (struct resource[]) {
105 {
106 .start = MPC85xx_ENET2_OFFSET,
107 .end = MPC85xx_ENET2_OFFSET +
108 MPC85xx_ENET2_SIZE - 1,
109 .flags = IORESOURCE_MEM,
110 },
111 {
112 .name = "tx",
113 .start = MPC85xx_IRQ_TSEC2_TX,
114 .end = MPC85xx_IRQ_TSEC2_TX,
115 .flags = IORESOURCE_IRQ,
116 },
117 {
118 .name = "rx",
119 .start = MPC85xx_IRQ_TSEC2_RX,
120 .end = MPC85xx_IRQ_TSEC2_RX,
121 .flags = IORESOURCE_IRQ,
122 },
123 {
124 .name = "error",
125 .start = MPC85xx_IRQ_TSEC2_ERROR,
126 .end = MPC85xx_IRQ_TSEC2_ERROR,
127 .flags = IORESOURCE_IRQ,
128 },
129 },
130 },
131 [MPC85xx_FEC] = {
132 .name = "fsl-gianfar",
133 .id = 3,
134 .dev.platform_data = &mpc85xx_fec_pdata,
135 .num_resources = 2,
136 .resource = (struct resource[]) {
137 {
138 .start = MPC85xx_ENET3_OFFSET,
139 .end = MPC85xx_ENET3_OFFSET +
140 MPC85xx_ENET3_SIZE - 1,
141 .flags = IORESOURCE_MEM,
142
143 },
144 {
145 .start = MPC85xx_IRQ_FEC,
146 .end = MPC85xx_IRQ_FEC,
147 .flags = IORESOURCE_IRQ,
148 },
149 },
150 },
151 [MPC85xx_IIC1] = {
152 .name = "fsl-i2c",
153 .id = 1,
154 .dev.platform_data = &mpc85xx_fsl_i2c_pdata,
155 .num_resources = 2,
156 .resource = (struct resource[]) {
157 {
158 .start = MPC85xx_IIC1_OFFSET,
159 .end = MPC85xx_IIC1_OFFSET +
160 MPC85xx_IIC1_SIZE - 1,
161 .flags = IORESOURCE_MEM,
162 },
163 {
164 .start = MPC85xx_IRQ_IIC1,
165 .end = MPC85xx_IRQ_IIC1,
166 .flags = IORESOURCE_IRQ,
167 },
168 },
169 },
170 [MPC85xx_DMA0] = {
171 .name = "fsl-dma",
172 .id = 0,
173 .num_resources = 2,
174 .resource = (struct resource[]) {
175 {
176 .start = MPC85xx_DMA0_OFFSET,
177 .end = MPC85xx_DMA0_OFFSET +
178 MPC85xx_DMA0_SIZE - 1,
179 .flags = IORESOURCE_MEM,
180 },
181 {
182 .start = MPC85xx_IRQ_DMA0,
183 .end = MPC85xx_IRQ_DMA0,
184 .flags = IORESOURCE_IRQ,
185 },
186 },
187 },
188 [MPC85xx_DMA1] = {
189 .name = "fsl-dma",
190 .id = 1,
191 .num_resources = 2,
192 .resource = (struct resource[]) {
193 {
194 .start = MPC85xx_DMA1_OFFSET,
195 .end = MPC85xx_DMA1_OFFSET +
196 MPC85xx_DMA1_SIZE - 1,
197 .flags = IORESOURCE_MEM,
198 },
199 {
200 .start = MPC85xx_IRQ_DMA1,
201 .end = MPC85xx_IRQ_DMA1,
202 .flags = IORESOURCE_IRQ,
203 },
204 },
205 },
206 [MPC85xx_DMA2] = {
207 .name = "fsl-dma",
208 .id = 2,
209 .num_resources = 2,
210 .resource = (struct resource[]) {
211 {
212 .start = MPC85xx_DMA2_OFFSET,
213 .end = MPC85xx_DMA2_OFFSET +
214 MPC85xx_DMA2_SIZE - 1,
215 .flags = IORESOURCE_MEM,
216 },
217 {
218 .start = MPC85xx_IRQ_DMA2,
219 .end = MPC85xx_IRQ_DMA2,
220 .flags = IORESOURCE_IRQ,
221 },
222 },
223 },
224 [MPC85xx_DMA3] = {
225 .name = "fsl-dma",
226 .id = 3,
227 .num_resources = 2,
228 .resource = (struct resource[]) {
229 {
230 .start = MPC85xx_DMA3_OFFSET,
231 .end = MPC85xx_DMA3_OFFSET +
232 MPC85xx_DMA3_SIZE - 1,
233 .flags = IORESOURCE_MEM,
234 },
235 {
236 .start = MPC85xx_IRQ_DMA3,
237 .end = MPC85xx_IRQ_DMA3,
238 .flags = IORESOURCE_IRQ,
239 },
240 },
241 },
242 [MPC85xx_DUART] = {
243 .name = "serial8250",
244 .id = 0,
245 .dev.platform_data = serial_platform_data,
246 },
247 [MPC85xx_PERFMON] = {
248 .name = "fsl-perfmon",
249 .id = 1,
250 .num_resources = 2,
251 .resource = (struct resource[]) {
252 {
253 .start = MPC85xx_PERFMON_OFFSET,
254 .end = MPC85xx_PERFMON_OFFSET +
255 MPC85xx_PERFMON_SIZE - 1,
256 .flags = IORESOURCE_MEM,
257 },
258 {
259 .start = MPC85xx_IRQ_PERFMON,
260 .end = MPC85xx_IRQ_PERFMON,
261 .flags = IORESOURCE_IRQ,
262 },
263 },
264 },
265 [MPC85xx_SEC2] = {
266 .name = "fsl-sec2",
267 .id = 1,
268 .num_resources = 2,
269 .resource = (struct resource[]) {
270 {
271 .start = MPC85xx_SEC2_OFFSET,
272 .end = MPC85xx_SEC2_OFFSET +
273 MPC85xx_SEC2_SIZE - 1,
274 .flags = IORESOURCE_MEM,
275 },
276 {
277 .start = MPC85xx_IRQ_SEC2,
278 .end = MPC85xx_IRQ_SEC2,
279 .flags = IORESOURCE_IRQ,
280 },
281 },
282 },
283 #ifdef CONFIG_CPM2
284 [MPC85xx_CPM_FCC1] = {
285 .name = "fsl-cpm-fcc",
286 .id = 1,
287 .num_resources = 3,
288 .resource = (struct resource[]) {
289 {
290 .start = 0x91300,
291 .end = 0x9131F,
292 .flags = IORESOURCE_MEM,
293 },
294 {
295 .start = 0x91380,
296 .end = 0x9139F,
297 .flags = IORESOURCE_MEM,
298 },
299 {
300 .start = SIU_INT_FCC1,
301 .end = SIU_INT_FCC1,
302 .flags = IORESOURCE_IRQ,
303 },
304 },
305 },
306 [MPC85xx_CPM_FCC2] = {
307 .name = "fsl-cpm-fcc",
308 .id = 2,
309 .num_resources = 3,
310 .resource = (struct resource[]) {
311 {
312 .start = 0x91320,
313 .end = 0x9133F,
314 .flags = IORESOURCE_MEM,
315 },
316 {
317 .start = 0x913A0,
318 .end = 0x913CF,
319 .flags = IORESOURCE_MEM,
320 },
321 {
322 .start = SIU_INT_FCC2,
323 .end = SIU_INT_FCC2,
324 .flags = IORESOURCE_IRQ,
325 },
326 },
327 },
328 [MPC85xx_CPM_FCC3] = {
329 .name = "fsl-cpm-fcc",
330 .id = 3,
331 .num_resources = 3,
332 .resource = (struct resource[]) {
333 {
334 .start = 0x91340,
335 .end = 0x9135F,
336 .flags = IORESOURCE_MEM,
337 },
338 {
339 .start = 0x913D0,
340 .end = 0x913FF,
341 .flags = IORESOURCE_MEM,
342 },
343 {
344 .start = SIU_INT_FCC3,
345 .end = SIU_INT_FCC3,
346 .flags = IORESOURCE_IRQ,
347 },
348 },
349 },
350 [MPC85xx_CPM_I2C] = {
351 .name = "fsl-cpm-i2c",
352 .id = 1,
353 .num_resources = 2,
354 .resource = (struct resource[]) {
355 {
356 .start = 0x91860,
357 .end = 0x918BF,
358 .flags = IORESOURCE_MEM,
359 },
360 {
361 .start = SIU_INT_I2C,
362 .end = SIU_INT_I2C,
363 .flags = IORESOURCE_IRQ,
364 },
365 },
366 },
367 [MPC85xx_CPM_SCC1] = {
368 .name = "fsl-cpm-scc",
369 .id = 1,
370 .num_resources = 2,
371 .resource = (struct resource[]) {
372 {
373 .start = 0x91A00,
374 .end = 0x91A1F,
375 .flags = IORESOURCE_MEM,
376 },
377 {
378 .start = SIU_INT_SCC1,
379 .end = SIU_INT_SCC1,
380 .flags = IORESOURCE_IRQ,
381 },
382 },
383 },
384 [MPC85xx_CPM_SCC2] = {
385 .name = "fsl-cpm-scc",
386 .id = 2,
387 .num_resources = 2,
388 .resource = (struct resource[]) {
389 {
390 .start = 0x91A20,
391 .end = 0x91A3F,
392 .flags = IORESOURCE_MEM,
393 },
394 {
395 .start = SIU_INT_SCC2,
396 .end = SIU_INT_SCC2,
397 .flags = IORESOURCE_IRQ,
398 },
399 },
400 },
401 [MPC85xx_CPM_SCC3] = {
402 .name = "fsl-cpm-scc",
403 .id = 3,
404 .num_resources = 2,
405 .resource = (struct resource[]) {
406 {
407 .start = 0x91A40,
408 .end = 0x91A5F,
409 .flags = IORESOURCE_MEM,
410 },
411 {
412 .start = SIU_INT_SCC3,
413 .end = SIU_INT_SCC3,
414 .flags = IORESOURCE_IRQ,
415 },
416 },
417 },
418 [MPC85xx_CPM_SCC4] = {
419 .name = "fsl-cpm-scc",
420 .id = 4,
421 .num_resources = 2,
422 .resource = (struct resource[]) {
423 {
424 .start = 0x91A60,
425 .end = 0x91A7F,
426 .flags = IORESOURCE_MEM,
427 },
428 {
429 .start = SIU_INT_SCC4,
430 .end = SIU_INT_SCC4,
431 .flags = IORESOURCE_IRQ,
432 },
433 },
434 },
435 [MPC85xx_CPM_SPI] = {
436 .name = "fsl-cpm-spi",
437 .id = 1,
438 .num_resources = 2,
439 .resource = (struct resource[]) {
440 {
441 .start = 0x91AA0,
442 .end = 0x91AFF,
443 .flags = IORESOURCE_MEM,
444 },
445 {
446 .start = SIU_INT_SPI,
447 .end = SIU_INT_SPI,
448 .flags = IORESOURCE_IRQ,
449 },
450 },
451 },
452 [MPC85xx_CPM_MCC1] = {
453 .name = "fsl-cpm-mcc",
454 .id = 1,
455 .num_resources = 2,
456 .resource = (struct resource[]) {
457 {
458 .start = 0x91B30,
459 .end = 0x91B3F,
460 .flags = IORESOURCE_MEM,
461 },
462 {
463 .start = SIU_INT_MCC1,
464 .end = SIU_INT_MCC1,
465 .flags = IORESOURCE_IRQ,
466 },
467 },
468 },
469 [MPC85xx_CPM_MCC2] = {
470 .name = "fsl-cpm-mcc",
471 .id = 2,
472 .num_resources = 2,
473 .resource = (struct resource[]) {
474 {
475 .start = 0x91B50,
476 .end = 0x91B5F,
477 .flags = IORESOURCE_MEM,
478 },
479 {
480 .start = SIU_INT_MCC2,
481 .end = SIU_INT_MCC2,
482 .flags = IORESOURCE_IRQ,
483 },
484 },
485 },
486 [MPC85xx_CPM_SMC1] = {
487 .name = "fsl-cpm-smc",
488 .id = 1,
489 .num_resources = 2,
490 .resource = (struct resource[]) {
491 {
492 .start = 0x91A80,
493 .end = 0x91A8F,
494 .flags = IORESOURCE_MEM,
495 },
496 {
497 .start = SIU_INT_SMC1,
498 .end = SIU_INT_SMC1,
499 .flags = IORESOURCE_IRQ,
500 },
501 },
502 },
503 [MPC85xx_CPM_SMC2] = {
504 .name = "fsl-cpm-smc",
505 .id = 2,
506 .num_resources = 2,
507 .resource = (struct resource[]) {
508 {
509 .start = 0x91A90,
510 .end = 0x91A9F,
511 .flags = IORESOURCE_MEM,
512 },
513 {
514 .start = SIU_INT_SMC2,
515 .end = SIU_INT_SMC2,
516 .flags = IORESOURCE_IRQ,
517 },
518 },
519 },
520 [MPC85xx_CPM_USB] = {
521 .name = "fsl-cpm-usb",
522 .id = 2,
523 .num_resources = 2,
524 .resource = (struct resource[]) {
525 {
526 .start = 0x91B60,
527 .end = 0x91B7F,
528 .flags = IORESOURCE_MEM,
529 },
530 {
531 .start = SIU_INT_USB,
532 .end = SIU_INT_USB,
533 .flags = IORESOURCE_IRQ,
534 },
535 },
536 },
537 #endif /* CONFIG_CPM2 */
538 };
539
540 static int __init mach_mpc85xx_fixup(struct platform_device *pdev)
541 {
542 ppc_sys_fixup_mem_resource(pdev, CCSRBAR);
543 return 0;
544 }
545
546 static int __init mach_mpc85xx_init(void)
547 {
548 ppc_sys_device_fixup = mach_mpc85xx_fixup;
549 return 0;
550 }
551
552 postcore_initcall(mach_mpc85xx_init);
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