arch/ppc/syslib/ppc4xx_setup.c

   1 /*
   2  *
   3  *    Copyright (c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
   4  *
   5  *    Copyright 2000-2001 MontaVista Software Inc.
   6  *      Completed implementation.
   7  *      Author: MontaVista Software, Inc.  <source@mvista.com>
   8  *              Frank Rowand <frank_rowand@mvista.com>
   9  *              Debbie Chu   <debbie_chu@mvista.com>
  10  *      Further modifications by Armin Kuster
  11  *
  12  *    Module name: ppc4xx_setup.c
  13  *
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/init.h>
  18 #include <linux/smp.h>
  19 #include <linux/threads.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/irq.h>
  22 #include <linux/reboot.h>
  23 #include <linux/param.h>
  24 #include <linux/string.h>
  25 #include <linux/initrd.h>
  26 #include <linux/pci.h>
  27 #include <linux/rtc.h>
  28 #include <linux/console.h>
  29 #include <linux/ide.h>
  30 #include <linux/serial_reg.h>
  31 #include <linux/seq_file.h>
  32
  33 #include <asm/system.h>
  34 #include <asm/processor.h>
  35 #include <asm/machdep.h>
  36 #include <asm/page.h>
  37 #include <asm/kgdb.h>
  38 #include <asm/ibm4xx.h>
  39 #include <asm/time.h>
  40 #include <asm/todc.h>
  41 #include <asm/ppc4xx_pic.h>
  42 #include <asm/pci-bridge.h>
  43 #include <asm/bootinfo.h>
  44
  45 #include <syslib/gen550.h>
  46
  47 /* Function Prototypes */
  48 extern void abort(void);
  49 extern void ppc4xx_find_bridges(void);
  50
  51 extern void ppc4xx_wdt_heartbeat(void);
  52 extern int wdt_enable;
  53 extern unsigned long wdt_period;
  54
  55 /* Global Variables */
  56 bd_t __res;
  57
  58 void __init
  59 ppc4xx_setup_arch(void)
  60 {
  61 #if !defined(CONFIG_BDI_SWITCH)
  62         /*
  63          * The Abatron BDI JTAG debugger does not tolerate others
  64          * mucking with the debug registers.
  65          */
  66         mtspr(SPRN_DBCR0, (DBCR0_IDM));
  67         mtspr(SPRN_DBSR, 0xffffffff);
  68 #endif
  69
  70         /* Setup PCI host bridges */
  71 #ifdef CONFIG_PCI
  72         ppc4xx_find_bridges();
  73 #endif
  74 }
  75
  76 /*
  77  *   This routine pretty-prints the platform's internal CPU clock
  78  *   frequencies into the buffer for usage in /proc/cpuinfo.
  79  */
  80
  81 static int
  82 ppc4xx_show_percpuinfo(struct seq_file *m, int i)
  83 {
  84         seq_printf(m, "clock\t\t: %ldMHz\n", (long)__res.bi_intfreq / 1000000);
  85
  86         return 0;
  87 }
  88
  89 /*
  90  *   This routine pretty-prints the platform's internal bus clock
  91  *   frequencies into the buffer for usage in /proc/cpuinfo.
  92  */
  93 static int
  94 ppc4xx_show_cpuinfo(struct seq_file *m)
  95 {
  96         bd_t *bip = &__res;
  97
  98         seq_printf(m, "machine\t\t: %s\n", PPC4xx_MACHINE_NAME);
  99         seq_printf(m, "plb bus clock\t: %ldMHz\n",
 100                    (long) bip->bi_busfreq / 1000000);
 101 #ifdef CONFIG_PCI
 102         seq_printf(m, "pci bus clock\t: %dMHz\n",
 103                    bip->bi_pci_busfreq / 1000000);
 104 #endif
 105
 106         return 0;
 107 }
 108
 109 /*
 110  * Return the virtual address representing the top of physical RAM.
 111  */
 112 static unsigned long __init
 113 ppc4xx_find_end_of_memory(void)
 114 {
 115         return ((unsigned long) __res.bi_memsize);
 116 }
 117
 118 void __init
 119 ppc4xx_map_io(void)
 120 {
 121         io_block_mapping(PPC4xx_ONB_IO_VADDR,
 122                          PPC4xx_ONB_IO_PADDR, PPC4xx_ONB_IO_SIZE, _PAGE_IO);
 123 #ifdef CONFIG_PCI
 124         io_block_mapping(PPC4xx_PCI_IO_VADDR,
 125                          PPC4xx_PCI_IO_PADDR, PPC4xx_PCI_IO_SIZE, _PAGE_IO);
 126         io_block_mapping(PPC4xx_PCI_CFG_VADDR,
 127                          PPC4xx_PCI_CFG_PADDR, PPC4xx_PCI_CFG_SIZE, _PAGE_IO);
 128         io_block_mapping(PPC4xx_PCI_LCFG_VADDR,
 129                          PPC4xx_PCI_LCFG_PADDR, PPC4xx_PCI_LCFG_SIZE, _PAGE_IO);
 130 #endif
 131 }
 132
 133 void __init
 134 ppc4xx_init_IRQ(void)
 135 {
 136         ppc4xx_pic_init();
 137 }
 138
 139 static void
 140 ppc4xx_restart(char *cmd)
 141 {
 142         printk("%s\n", cmd);
 143         abort();
 144 }
 145
 146 static void
 147 ppc4xx_power_off(void)
 148 {
 149         printk("System Halted\n");
 150         local_irq_disable();
 151         while (1) ;
 152 }
 153
 154 static void
 155 ppc4xx_halt(void)
 156 {
 157         printk("System Halted\n");
 158         local_irq_disable();
 159         while (1) ;
 160 }
 161
 162 /*
 163  * This routine retrieves the internal processor frequency from the board
 164  * information structure, sets up the kernel timer decrementer based on
 165  * that value, enables the 4xx programmable interval timer (PIT) and sets
 166  * it up for auto-reload.
 167  */
 168 static void __init
 169 ppc4xx_calibrate_decr(void)
 170 {
 171         unsigned int freq;
 172         bd_t *bip = &__res;
 173
 174 #if defined(CONFIG_WALNUT) || defined(CONFIG_ASH) || defined(CONFIG_SYCAMORE)
 175         /* Walnut boot rom sets DCR CHCR1 (aka CPC0_CR1) bit CETE to 1 */
 176         mtdcr(DCRN_CHCR1, mfdcr(DCRN_CHCR1) & ~CHR1_CETE);
 177 #endif
 178         freq = bip->bi_tbfreq;
 179         tb_ticks_per_jiffy = freq / HZ;
 180         tb_to_us = mulhwu_scale_factor(freq, 1000000);
 181
 182         /* Set the time base to zero.
 183            ** At 200 Mhz, time base will rollover in ~2925 years.
 184          */
 185
 186         mtspr(SPRN_TBWL, 0);
 187         mtspr(SPRN_TBWU, 0);
 188
 189         /* Clear any pending timer interrupts */
 190
 191         mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_PIS | TSR_FIS);
 192         mtspr(SPRN_TCR, TCR_PIE | TCR_ARE);
 193
 194         /* Set the PIT reload value and just let it run. */
 195         mtspr(SPRN_PIT, tb_ticks_per_jiffy);
 196 }
 197
 198 /*
 199  * IDE stuff.
 200  * should be generic for every IDE PCI chipset
 201  */
 202 #if defined(CONFIG_PCI) && defined(CONFIG_IDE)
 203 static void
 204 ppc4xx_ide_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
 205                            unsigned long ctrl_port, int *irq)
 206 {
 207         int i;
 208
 209         for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; ++i)
 210                 hw->io_ports[i] = data_port + i - IDE_DATA_OFFSET;
 211
 212         hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
 213 }
 214 #endif /* defined(CONFIG_PCI) && defined(CONFIG_IDE) */
 215
 216 TODC_ALLOC();
 217
 218 /*
 219  * Input(s):
 220  *   r3 - Optional pointer to a board information structure.
 221  *   r4 - Optional pointer to the physical starting address of the init RAM
 222  *        disk.
 223  *   r5 - Optional pointer to the physical ending address of the init RAM
 224  *        disk.
 225  *   r6 - Optional pointer to the physical starting address of any kernel
 226  *        command-line parameters.
 227  *   r7 - Optional pointer to the physical ending address of any kernel
 228  *        command-line parameters.
 229  */
 230 void __init
 231 ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5,
 232             unsigned long r6, unsigned long r7)
 233 {
 234         parse_bootinfo(find_bootinfo());
 235
 236         /*
 237          * If we were passed in a board information, copy it into the
 238          * residual data area.
 239          */
 240         if (r3)
 241                 __res = *(bd_t *)(r3 + KERNELBASE);
 242
 243 #if defined(CONFIG_BLK_DEV_INITRD)
 244         /*
 245          * If the init RAM disk has been configured in, and there's a valid
 246          * starting address for it, set it up.
 247          */
 248         if (r4) {
 249                 initrd_start = r4 + KERNELBASE;
 250                 initrd_end = r5 + KERNELBASE;
 251         }
 252 #endif                          /* CONFIG_BLK_DEV_INITRD */
 253
 254         /* Copy the kernel command line arguments to a safe place. */
 255
 256         if (r6) {
 257                 *(char *) (r7 + KERNELBASE) = 0;
 258                 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
 259         }
 260 #if defined(CONFIG_PPC405_WDT)
 261 /* Look for wdt= option on command line */
 262         if (strstr(cmd_line, "wdt=")) {
 263                 int valid_wdt = 0;
 264                 char *p, *q;
 265                 for (q = cmd_line; (p = strstr(q, "wdt=")) != 0;) {
 266                         q = p + 4;
 267                         if (p > cmd_line && p[-1] != ' ')
 268                                 continue;
 269                         wdt_period = simple_strtoul(q, &q, 0);
 270                         valid_wdt = 1;
 271                         ++q;
 272                 }
 273                 wdt_enable = valid_wdt;
 274         }
 275 #endif
 276
 277         /* Initialize machine-dependent vectors */
 278
 279         ppc_md.setup_arch = ppc4xx_setup_arch;
 280         ppc_md.show_percpuinfo = ppc4xx_show_percpuinfo;
 281         ppc_md.show_cpuinfo = ppc4xx_show_cpuinfo;
 282         ppc_md.init_IRQ = ppc4xx_init_IRQ;
 283
 284         ppc_md.restart = ppc4xx_restart;
 285         ppc_md.power_off = ppc4xx_power_off;
 286         ppc_md.halt = ppc4xx_halt;
 287
 288         ppc_md.calibrate_decr = ppc4xx_calibrate_decr;
 289
 290 #ifdef CONFIG_PPC405_WDT
 291         ppc_md.heartbeat = ppc4xx_wdt_heartbeat;
 292 #endif
 293         ppc_md.heartbeat_count = 0;
 294
 295         ppc_md.find_end_of_memory = ppc4xx_find_end_of_memory;
 296         ppc_md.setup_io_mappings = ppc4xx_map_io;
 297
 298 #ifdef CONFIG_SERIAL_TEXT_DEBUG
 299         ppc_md.progress = gen550_progress;
 300 #endif
 301
 302 #if defined(CONFIG_PCI) && defined(CONFIG_IDE)
 303         ppc_ide_md.ide_init_hwif = ppc4xx_ide_init_hwif_ports;
 304 #endif /* defined(CONFIG_PCI) && defined(CONFIG_IDE) */
 305 }
 306
 307 /* Called from MachineCheckException */
 308 void platform_machine_check(struct pt_regs *regs)
 309 {
 310 #if defined(DCRN_PLB0_BEAR)
 311         printk("PLB0: BEAR= 0x%08x ACR=   0x%08x BESR=  0x%08x\n",
 312             mfdcr(DCRN_PLB0_BEAR), mfdcr(DCRN_PLB0_ACR),
 313             mfdcr(DCRN_PLB0_BESR));
 314 #endif
 315 #if defined(DCRN_POB0_BEAR)
 316         printk("PLB0 to OPB: BEAR= 0x%08x BESR0= 0x%08x BESR1= 0x%08x\n",
 317             mfdcr(DCRN_POB0_BEAR), mfdcr(DCRN_POB0_BESR0),
 318             mfdcr(DCRN_POB0_BESR1));
 319 #endif
 320
 321 }