arch/ppc64/kernel/u3_iommu.c

   1 /*
   2  * arch/ppc64/kernel/u3_iommu.c
   3  *
   4  * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation
   5  *
   6  * Based on pSeries_iommu.c:
   7  * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
   8  * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation
   9  *
  10  * Dynamic DMA mapping support, Apple U3 & IBM CPC925 "DART" iommu.
  11  *
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  26  */
  27
  28 #include <linux/config.h>
  29 #include <linux/init.h>
  30 #include <linux/types.h>
  31 #include <linux/slab.h>
  32 #include <linux/mm.h>
  33 #include <linux/spinlock.h>
  34 #include <linux/string.h>
  35 #include <linux/pci.h>
  36 #include <linux/dma-mapping.h>
  37 #include <linux/vmalloc.h>
  38 #include <asm/io.h>
  39 #include <asm/prom.h>
  40 #include <asm/ppcdebug.h>
  41 #include <asm/iommu.h>
  42 #include <asm/pci-bridge.h>
  43 #include <asm/machdep.h>
  44 #include <asm/abs_addr.h>
  45 #include <asm/cacheflush.h>
  46 #include <asm/lmb.h>
  47
  48 #include "pci.h"
  49
  50 extern int iommu_force_on;
  51
  52 /* physical base of DART registers */
  53 #define DART_BASE        0xf8033000UL
  54
  55 /* Offset from base to control register */
  56 #define DARTCNTL   0
  57 /* Offset from base to exception register */
  58 #define DARTEXCP   0x10
  59 /* Offset from base to TLB tag registers */
  60 #define DARTTAG    0x1000
  61
  62
  63 /* Control Register fields */
  64
  65 /* base address of table (pfn) */
  66 #define DARTCNTL_BASE_MASK    0xfffff
  67 #define DARTCNTL_BASE_SHIFT   12
  68
  69 #define DARTCNTL_FLUSHTLB     0x400
  70 #define DARTCNTL_ENABLE       0x200
  71
  72 /* size of table in pages */
  73 #define DARTCNTL_SIZE_MASK    0x1ff
  74 #define DARTCNTL_SIZE_SHIFT   0
  75
  76 /* DART table fields */
  77 #define DARTMAP_VALID   0x80000000
  78 #define DARTMAP_RPNMASK 0x00ffffff
  79
  80 /* Physical base address and size of the DART table */
  81 unsigned long dart_tablebase; /* exported to htab_initialize */
  82 static unsigned long dart_tablesize;
  83
  84 /* Virtual base address of the DART table */
  85 static u32 *dart_vbase;
  86
  87 /* Mapped base address for the dart */
  88 static unsigned int *dart;
  89
  90 /* Dummy val that entries are set to when unused */
  91 static unsigned int dart_emptyval;
  92
  93 static struct iommu_table iommu_table_u3;
  94 static int iommu_table_u3_inited;
  95 static int dart_dirty;
  96
  97 #define DBG(...)
  98
  99 static inline void dart_tlb_invalidate_all(void)
 100 {
 101         unsigned long l = 0;
 102         unsigned int reg;
 103         unsigned long limit;
 104
 105         DBG("dart: flush\n");
 106
 107         /* To invalidate the DART, set the DARTCNTL_FLUSHTLB bit in the
 108          * control register and wait for it to clear.
 109          *
 110          * Gotcha: Sometimes, the DART won't detect that the bit gets
 111          * set. If so, clear it and set it again.
 112          */
 113
 114         limit = 0;
 115
 116 retry:
 117         reg = in_be32((unsigned int *)dart+DARTCNTL);
 118         reg |= DARTCNTL_FLUSHTLB;
 119         out_be32((unsigned int *)dart+DARTCNTL, reg);
 120
 121         l = 0;
 122         while ((in_be32((unsigned int *)dart+DARTCNTL) & DARTCNTL_FLUSHTLB) &&
 123                 l < (1L<<limit)) {
 124                 l++;
 125         }
 126         if (l == (1L<<limit)) {
 127                 if (limit < 4) {
 128                         limit++;
 129                         reg = in_be32((unsigned int *)dart+DARTCNTL);
 130                         reg &= ~DARTCNTL_FLUSHTLB;
 131                         out_be32((unsigned int *)dart+DARTCNTL, reg);
 132                         goto retry;
 133                 } else
 134                         panic("U3-DART: TLB did not flush after waiting a long "
 135                               "time. Buggy U3 ?");
 136         }
 137 }
 138
 139 static void dart_flush(struct iommu_table *tbl)
 140 {
 141         if (dart_dirty)
 142                 dart_tlb_invalidate_all();
 143         dart_dirty = 0;
 144 }
 145
 146 static void dart_build(struct iommu_table *tbl, long index,
 147                        long npages, unsigned long uaddr,
 148                        enum dma_data_direction direction)
 149 {
 150         unsigned int *dp;
 151         unsigned int rpn;
 152
 153         DBG("dart: build at: %lx, %lx, addr: %x\n", index, npages, uaddr);
 154
 155         dp = ((unsigned int*)tbl->it_base) + index;
 156
 157         /* On U3, all memory is contigous, so we can move this
 158          * out of the loop.
 159          */
 160         while (npages--) {
 161                 rpn = virt_to_abs(uaddr) >> PAGE_SHIFT;
 162
 163                 *(dp++) = DARTMAP_VALID | (rpn & DARTMAP_RPNMASK);
 164
 165                 rpn++;
 166                 uaddr += PAGE_SIZE;
 167         }
 168
 169         dart_dirty = 1;
 170 }
 171
 172
 173 static void dart_free(struct iommu_table *tbl, long index, long npages)
 174 {
 175         unsigned int *dp;
 176
 177         /* We don't worry about flushing the TLB cache. The only drawback of
 178          * not doing it is that we won't catch buggy device drivers doing
 179          * bad DMAs, but then no 32-bit architecture ever does either.
 180          */
 181
 182         DBG("dart: free at: %lx, %lx\n", index, npages);
 183
 184         dp  = ((unsigned int *)tbl->it_base) + index;
 185
 186         while (npages--)
 187                 *(dp++) = dart_emptyval;
 188 }
 189
 190
 191 static int dart_init(struct device_node *dart_node)
 192 {
 193         unsigned int regword;
 194         unsigned int i;
 195         unsigned long tmp;
 196
 197         if (dart_tablebase == 0 || dart_tablesize == 0) {
 198                 printk(KERN_INFO "U3-DART: table not allocated, using direct DMA\n");
 199                 return -ENODEV;
 200         }
 201
 202         /* Make sure nothing from the DART range remains in the CPU cache
 203          * from a previous mapping that existed before the kernel took
 204          * over
 205          */
 206         flush_dcache_phys_range(dart_tablebase, dart_tablebase + dart_tablesize);
 207
 208         /* Allocate a spare page to map all invalid DART pages. We need to do
 209          * that to work around what looks like a problem with the HT bridge
 210          * prefetching into invalid pages and corrupting data
 211          */
 212         tmp = lmb_alloc(PAGE_SIZE, PAGE_SIZE);
 213         if (!tmp)
 214                 panic("U3-DART: Cannot allocate spare page!");
 215         dart_emptyval = DARTMAP_VALID | ((tmp >> PAGE_SHIFT) & DARTMAP_RPNMASK);
 216
 217         /* Map in DART registers. FIXME: Use device node to get base address */
 218         dart = ioremap(DART_BASE, 0x7000);
 219         if (dart == NULL)
 220                 panic("U3-DART: Cannot map registers!");
 221
 222         /* Set initial control register contents: table base,
 223          * table size and enable bit
 224          */
 225         regword = DARTCNTL_ENABLE |
 226                 ((dart_tablebase >> PAGE_SHIFT) << DARTCNTL_BASE_SHIFT) |
 227                 (((dart_tablesize >> PAGE_SHIFT) & DARTCNTL_SIZE_MASK)
 228                                  << DARTCNTL_SIZE_SHIFT);
 229         dart_vbase = ioremap(virt_to_abs(dart_tablebase), dart_tablesize);
 230
 231         /* Fill initial table */
 232         for (i = 0; i < dart_tablesize/4; i++)
 233                 dart_vbase[i] = dart_emptyval;
 234
 235         /* Initialize DART with table base and enable it. */
 236         out_be32((unsigned int *)dart, regword);
 237
 238         /* Invalidate DART to get rid of possible stale TLBs */
 239         dart_tlb_invalidate_all();
 240
 241         printk(KERN_INFO "U3/CPC925 DART IOMMU initialized\n");
 242
 243         return 0;
 244 }
 245
 246 static void iommu_table_u3_setup(void)
 247 {
 248         iommu_table_u3.it_busno = 0;
 249         iommu_table_u3.it_offset = 0;
 250         /* it_size is in number of entries */
 251         iommu_table_u3.it_size = dart_tablesize / sizeof(u32);
 252
 253         /* Initialize the common IOMMU code */
 254         iommu_table_u3.it_base = (unsigned long)dart_vbase;
 255         iommu_table_u3.it_index = 0;
 256         iommu_table_u3.it_blocksize = 1;
 257         iommu_init_table(&iommu_table_u3);
 258
 259         /* Reserve the last page of the DART to avoid possible prefetch
 260          * past the DART mapped area
 261          */
 262         set_bit(iommu_table_u3.it_size - 1, iommu_table_u3.it_map);
 263 }
 264
 265 static void iommu_dev_setup_u3(struct pci_dev *dev)
 266 {
 267         struct device_node *dn;
 268
 269         /* We only have one iommu table on the mac for now, which makes
 270          * things simple. Setup all PCI devices to point to this table
 271          *
 272          * We must use pci_device_to_OF_node() to make sure that
 273          * we get the real "final" pointer to the device in the
 274          * pci_dev sysdata and not the temporary PHB one
 275          */
 276         dn = pci_device_to_OF_node(dev);
 277
 278         if (dn)
 279                 dn->iommu_table = &iommu_table_u3;
 280 }
 281
 282 static void iommu_bus_setup_u3(struct pci_bus *bus)
 283 {
 284         struct device_node *dn;
 285
 286         if (!iommu_table_u3_inited) {
 287                 iommu_table_u3_inited = 1;
 288                 iommu_table_u3_setup();
 289         }
 290
 291         dn = pci_bus_to_OF_node(bus);
 292
 293         if (dn)
 294                 dn->iommu_table = &iommu_table_u3;
 295 }
 296
 297 static void iommu_dev_setup_null(struct pci_dev *dev) { }
 298 static void iommu_bus_setup_null(struct pci_bus *bus) { }
 299
 300 void iommu_init_early_u3(void)
 301 {
 302         struct device_node *dn;
 303
 304         /* Find the DART in the device-tree */
 305         dn = of_find_compatible_node(NULL, "dart", "u3-dart");
 306         if (dn == NULL)
 307                 return;
 308
 309         /* Setup low level TCE operations for the core IOMMU code */
 310         ppc_md.tce_build = dart_build;
 311         ppc_md.tce_free  = dart_free;
 312         ppc_md.tce_flush = dart_flush;
 313
 314         /* Initialize the DART HW */
 315         if (dart_init(dn)) {
 316                 /* If init failed, use direct iommu and null setup functions */
 317                 ppc_md.iommu_dev_setup = iommu_dev_setup_null;
 318                 ppc_md.iommu_bus_setup = iommu_bus_setup_null;
 319
 320                 /* Setup pci_dma ops */
 321                 pci_direct_iommu_init();
 322         } else {
 323                 ppc_md.iommu_dev_setup = iommu_dev_setup_u3;
 324                 ppc_md.iommu_bus_setup = iommu_bus_setup_u3;
 325
 326                 /* Setup pci_dma ops */
 327                 pci_iommu_init();
 328         }
 329 }
 330
 331
 332 void __init alloc_u3_dart_table(void)
 333 {
 334         /* Only reserve DART space if machine has more than 2GB of RAM
 335          * or if requested with iommu=on on cmdline.
 336          */
 337         if (lmb_end_of_DRAM() <= 0x80000000ull && !iommu_force_on)
 338                 return;
 339
 340         /* 512 pages (2MB) is max DART tablesize. */
 341         dart_tablesize = 1UL << 21;
 342         /* 16MB (1 << 24) alignment. We allocate a full 16Mb chuck since we
 343          * will blow up an entire large page anyway in the kernel mapping
 344          */
 345         dart_tablebase = (unsigned long)
 346                 abs_to_virt(lmb_alloc_base(1UL<<24, 1UL<<24, 0x80000000L));
 347
 348         printk(KERN_INFO "U3-DART allocated at: %lx\n", dart_tablebase);
 349 }