arch/sh64/kernel/dma.c

   1 /*
   2  * arch/sh64/kernel/dma.c
   3  *
   4  * DMA routines for the SH-5 DMAC.
   5  *
   6  * Copyright (C) 2003  Paul Mundt
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/types.h>
  16 #include <linux/irq.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/mm.h>
  19 #include <asm/hardware.h>
  20 #include <asm/dma.h>
  21 #include <asm/signal.h>
  22 #include <asm/errno.h>
  23 #include <asm/io.h>
  24
  25 typedef struct {
  26         unsigned long dev_addr;
  27         unsigned long mem_addr;
  28
  29         unsigned int mode;
  30         unsigned int count;
  31 } dma_info_t;
  32
  33 static dma_info_t dma_info[MAX_DMA_CHANNELS];
  34 static DEFINE_SPINLOCK(dma_spin_lock);
  35
  36 /* arch/sh64/kernel/irq_intc.c */
  37 extern void make_intc_irq(unsigned int irq);
  38
  39 /* DMAC Interrupts */
  40 #define DMA_IRQ_DMTE0   18
  41 #define DMA_IRQ_DERR    22
  42
  43 #define DMAC_COMMON_BASE        (dmac_base + 0x08)
  44 #define DMAC_SAR_BASE           (dmac_base + 0x10)
  45 #define DMAC_DAR_BASE           (dmac_base + 0x18)
  46 #define DMAC_COUNT_BASE         (dmac_base + 0x20)
  47 #define DMAC_CTRL_BASE          (dmac_base + 0x28)
  48 #define DMAC_STATUS_BASE        (dmac_base + 0x30)
  49
  50 #define DMAC_SAR(n)     (DMAC_SAR_BASE    + ((n) * 0x28))
  51 #define DMAC_DAR(n)     (DMAC_DAR_BASE    + ((n) * 0x28))
  52 #define DMAC_COUNT(n)   (DMAC_COUNT_BASE  + ((n) * 0x28))
  53 #define DMAC_CTRL(n)    (DMAC_CTRL_BASE   + ((n) * 0x28))
  54 #define DMAC_STATUS(n)  (DMAC_STATUS_BASE + ((n) * 0x28))
  55
  56 /* DMAC.COMMON Bit Definitions */
  57 #define DMAC_COMMON_PR  0x00000001      /* Priority */
  58                                         /* Bits 1-2 Reserved */
  59 #define DMAC_COMMON_ME  0x00000008      /* Master Enable */
  60 #define DMAC_COMMON_NMI 0x00000010      /* NMI Flag */
  61                                         /* Bits 5-6 Reserved */
  62 #define DMAC_COMMON_ER  0x00000780      /* Error Response */
  63 #define DMAC_COMMON_AAE 0x00007800      /* Address Alignment Error */
  64                                         /* Bits 15-63 Reserved */
  65
  66 /* DMAC.SAR Bit Definitions */
  67 #define DMAC_SAR_ADDR   0xffffffff      /* Source Address */
  68
  69 /* DMAC.DAR Bit Definitions */
  70 #define DMAC_DAR_ADDR   0xffffffff      /* Destination Address */
  71
  72 /* DMAC.COUNT Bit Definitions */
  73 #define DMAC_COUNT_CNT  0xffffffff      /* Transfer Count */
  74
  75 /* DMAC.CTRL Bit Definitions */
  76 #define DMAC_CTRL_TS    0x00000007      /* Transfer Size */
  77 #define DMAC_CTRL_SI    0x00000018      /* Source Increment */
  78 #define DMAC_CTRL_DI    0x00000060      /* Destination Increment */
  79 #define DMAC_CTRL_RS    0x00000780      /* Resource Select */
  80 #define DMAC_CTRL_IE    0x00000800      /* Interrupt Enable */
  81 #define DMAC_CTRL_TE    0x00001000      /* Transfer Enable */
  82                                         /* Bits 15-63 Reserved */
  83
  84 /* DMAC.STATUS Bit Definitions */
  85 #define DMAC_STATUS_TE  0x00000001      /* Transfer End */
  86 #define DMAC_STATUS_AAE 0x00000002      /* Address Alignment Error */
  87                                         /* Bits 2-63 Reserved */
  88
  89 static unsigned long dmac_base;
  90
  91 void set_dma_count(unsigned int chan, unsigned int count);
  92 void set_dma_addr(unsigned int chan, unsigned int addr);
  93
  94 static irqreturn_t dma_mte(int irq, void *dev_id, struct pt_regs *regs)
  95 {
  96         unsigned int chan = irq - DMA_IRQ_DMTE0;
  97         dma_info_t *info = dma_info + chan;
  98         u64 status;
  99
 100         if (info->mode & DMA_MODE_WRITE) {
 101                 sh64_out64(info->mem_addr & DMAC_SAR_ADDR, DMAC_SAR(chan));
 102         } else {
 103                 sh64_out64(info->mem_addr & DMAC_DAR_ADDR, DMAC_DAR(chan));
 104         }
 105
 106         set_dma_count(chan, info->count);
 107
 108         /* Clear the TE bit */
 109         status = sh64_in64(DMAC_STATUS(chan));
 110         status &= ~DMAC_STATUS_TE;
 111         sh64_out64(status, DMAC_STATUS(chan));
 112
 113         return IRQ_HANDLED;
 114 }
 115
 116 static struct irqaction irq_dmte = {
 117         .handler        = dma_mte,
 118         .flags          = SA_INTERRUPT,
 119         .name           = "DMA MTE",
 120 };
 121
 122 static irqreturn_t dma_err(int irq, void *dev_id, struct pt_regs *regs)
 123 {
 124         u64 tmp;
 125         u8 chan;
 126
 127         printk(KERN_NOTICE "DMAC: Got a DMA Error!\n");
 128
 129         tmp = sh64_in64(DMAC_COMMON_BASE);
 130
 131         /* Check for the type of error */
 132         if ((chan = tmp & DMAC_COMMON_AAE)) {
 133                 /* It's an address alignment error.. */
 134                 printk(KERN_NOTICE "DMAC: Alignment error on channel %d, ", chan);
 135
 136                 printk(KERN_NOTICE "SAR: 0x%08llx, DAR: 0x%08llx, COUNT: %lld\n",
 137                        (sh64_in64(DMAC_SAR(chan)) & DMAC_SAR_ADDR),
 138                        (sh64_in64(DMAC_DAR(chan)) & DMAC_DAR_ADDR),
 139                        (sh64_in64(DMAC_COUNT(chan)) & DMAC_COUNT_CNT));
 140
 141         } else if ((chan = tmp & DMAC_COMMON_ER)) {
 142                 /* Something else went wrong.. */
 143                 printk(KERN_NOTICE "DMAC: Error on channel %d\n", chan);
 144         }
 145
 146         /* Reset the ME bit to clear the interrupt */
 147         tmp |= DMAC_COMMON_ME;
 148         sh64_out64(tmp, DMAC_COMMON_BASE);
 149
 150         return IRQ_HANDLED;
 151 }
 152
 153 static struct irqaction irq_derr = {
 154         .handler        = dma_err,
 155         .flags          = SA_INTERRUPT,
 156         .name           = "DMA Error",
 157 };
 158
 159 static inline unsigned long calc_xmit_shift(unsigned int chan)
 160 {
 161         return sh64_in64(DMAC_CTRL(chan)) & 0x03;
 162 }
 163
 164 void setup_dma(unsigned int chan, dma_info_t *info)
 165 {
 166         unsigned int irq = DMA_IRQ_DMTE0 + chan;
 167         dma_info_t *dma = dma_info + chan;
 168
 169         make_intc_irq(irq);
 170         setup_irq(irq, &irq_dmte);
 171         dma = info;
 172 }
 173
 174 void enable_dma(unsigned int chan)
 175 {
 176         u64 ctrl;
 177
 178         ctrl = sh64_in64(DMAC_CTRL(chan));
 179         ctrl |= DMAC_CTRL_TE;
 180         sh64_out64(ctrl, DMAC_CTRL(chan));
 181 }
 182
 183 void disable_dma(unsigned int chan)
 184 {
 185         u64 ctrl;
 186
 187         ctrl = sh64_in64(DMAC_CTRL(chan));
 188         ctrl &= ~DMAC_CTRL_TE;
 189         sh64_out64(ctrl, DMAC_CTRL(chan));
 190 }
 191
 192 void set_dma_mode(unsigned int chan, char mode)
 193 {
 194         dma_info_t *info = dma_info + chan;
 195
 196         info->mode = mode;
 197
 198         set_dma_addr(chan, info->mem_addr);
 199         set_dma_count(chan, info->count);
 200 }
 201
 202 void set_dma_addr(unsigned int chan, unsigned int addr)
 203 {
 204         dma_info_t *info = dma_info + chan;
 205         unsigned long sar, dar;
 206
 207         info->mem_addr = addr;
 208         sar = (info->mode & DMA_MODE_WRITE) ? info->mem_addr : info->dev_addr;
 209         dar = (info->mode & DMA_MODE_WRITE) ? info->dev_addr : info->mem_addr;
 210
 211         sh64_out64(sar & DMAC_SAR_ADDR, DMAC_SAR(chan));
 212         sh64_out64(dar & DMAC_SAR_ADDR, DMAC_DAR(chan));
 213 }
 214
 215 void set_dma_count(unsigned int chan, unsigned int count)
 216 {
 217         dma_info_t *info = dma_info + chan;
 218         u64 tmp;
 219
 220         info->count = count;
 221
 222         tmp = (info->count >> calc_xmit_shift(chan)) & DMAC_COUNT_CNT;
 223
 224         sh64_out64(tmp, DMAC_COUNT(chan));
 225 }
 226
 227 unsigned long claim_dma_lock(void)
 228 {
 229         unsigned long flags;
 230
 231         spin_lock_irqsave(&dma_spin_lock, flags);
 232
 233         return flags;
 234 }
 235
 236 void release_dma_lock(unsigned long flags)
 237 {
 238         spin_unlock_irqrestore(&dma_spin_lock, flags);
 239 }
 240
 241 int get_dma_residue(unsigned int chan)
 242 {
 243         return sh64_in64(DMAC_COUNT(chan) << calc_xmit_shift(chan));
 244 }
 245
 246 int __init init_dma(void)
 247 {
 248         struct vcr_info vcr;
 249         u64 tmp;
 250
 251         /* Remap the DMAC */
 252         dmac_base = onchip_remap(PHYS_DMAC_BLOCK, 1024, "DMAC");
 253         if (!dmac_base) {
 254                 printk(KERN_ERR "Unable to remap DMAC\n");
 255                 return -ENOMEM;
 256         }
 257
 258         /* Report DMAC.VCR Info */
 259         vcr = sh64_get_vcr_info(dmac_base);
 260         printk("DMAC: Module ID: 0x%04x, Module version: 0x%04x\n",
 261                vcr.mod_id, vcr.mod_vers);
 262
 263         /* Set the ME bit */
 264         tmp = sh64_in64(DMAC_COMMON_BASE);
 265         tmp |= DMAC_COMMON_ME;
 266         sh64_out64(tmp, DMAC_COMMON_BASE);
 267
 268         /* Enable the DMAC Error Interrupt */
 269         make_intc_irq(DMA_IRQ_DERR);
 270         setup_irq(DMA_IRQ_DERR, &irq_derr);
 271
 272         return 0;
 273 }
 274
 275 static void __exit exit_dma(void)
 276 {
 277         onchip_unmap(dmac_base);
 278         free_irq(DMA_IRQ_DERR, 0);
 279 }
 280
 281 module_init(init_dma);
 282 module_exit(exit_dma);
 283
 284 MODULE_AUTHOR("Paul Mundt");
 285 MODULE_DESCRIPTION("DMA API for SH-5 DMAC");
 286 MODULE_LICENSE("GPL");
 287
 288 EXPORT_SYMBOL(setup_dma);
 289 EXPORT_SYMBOL(claim_dma_lock);
 290 EXPORT_SYMBOL(release_dma_lock);
 291 EXPORT_SYMBOL(enable_dma);
 292 EXPORT_SYMBOL(disable_dma);
 293 EXPORT_SYMBOL(set_dma_mode);
 294 EXPORT_SYMBOL(set_dma_addr);
 295 EXPORT_SYMBOL(set_dma_count);
 296 EXPORT_SYMBOL(get_dma_residue);
 297