arch/sh64/kernel/irq_intc.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * arch/sh64/kernel/irq_intc.c
   7  *
   8  * Copyright (C) 2000, 2001  Paolo Alberelli
   9  * Copyright (C) 2003  Paul Mundt
  10  *
  11  * Interrupt Controller support for SH5 INTC.
  12  * Per-interrupt selective. IRLM=0 (Fixed priority) is not
  13  * supported being useless without a cascaded interrupt
  14  * controller.
  15  *
  16  */
  17
  18 #include <linux/config.h>
  19 #include <linux/init.h>
  20 #include <linux/irq.h>
  21 #include <linux/kernel.h>
  22 #include <linux/stddef.h>
  23 #include <linux/bitops.h>       /* this includes also <asm/registers.h */
  24                                 /* which is required to remap register */
  25                                 /* names used into __asm__ blocks...   */
  26
  27 #include <asm/hardware.h>
  28 #include <asm/platform.h>
  29 #include <asm/page.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32
  33 /*
  34  * Maybe the generic Peripheral block could move to a more
  35  * generic include file. INTC Block will be defined here
  36  * and only here to make INTC self-contained in a single
  37  * file.
  38  */
  39 #define INTC_BLOCK_OFFSET       0x01000000
  40
  41 /* Base */
  42 #define INTC_BASE               PHYS_PERIPHERAL_BLOCK + \
  43                                 INTC_BLOCK_OFFSET
  44
  45 /* Address */
  46 #define INTC_ICR_SET            (intc_virt + 0x0)
  47 #define INTC_ICR_CLEAR          (intc_virt + 0x8)
  48 #define INTC_INTPRI_0           (intc_virt + 0x10)
  49 #define INTC_INTSRC_0           (intc_virt + 0x50)
  50 #define INTC_INTSRC_1           (intc_virt + 0x58)
  51 #define INTC_INTREQ_0           (intc_virt + 0x60)
  52 #define INTC_INTREQ_1           (intc_virt + 0x68)
  53 #define INTC_INTENB_0           (intc_virt + 0x70)
  54 #define INTC_INTENB_1           (intc_virt + 0x78)
  55 #define INTC_INTDSB_0           (intc_virt + 0x80)
  56 #define INTC_INTDSB_1           (intc_virt + 0x88)
  57
  58 #define INTC_ICR_IRLM           0x1
  59 #define INTC_INTPRI_PREGS       8               /* 8 Priority Registers */
  60 #define INTC_INTPRI_PPREG       8               /* 8 Priorities per Register */
  61
  62
  63 /*
  64  * Mapper between the vector ordinal and the IRQ number
  65  * passed to kernel/device drivers.
  66  */
  67 int intc_evt_to_irq[(0xE20/0x20)+1] = {
  68         -1, -1, -1, -1, -1, -1, -1, -1, /* 0x000 - 0x0E0 */
  69         -1, -1, -1, -1, -1, -1, -1, -1, /* 0x100 - 0x1E0 */
  70          0,  0,  0,  0,  0,  1,  0,  0, /* 0x200 - 0x2E0 */
  71          2,  0,  0,  3,  0,  0,  0, -1, /* 0x300 - 0x3E0 */
  72         32, 33, 34, 35, 36, 37, 38, -1, /* 0x400 - 0x4E0 */
  73         -1, -1, -1, 63, -1, -1, -1, -1, /* 0x500 - 0x5E0 */
  74         -1, -1, 18, 19, 20, 21, 22, -1, /* 0x600 - 0x6E0 */
  75         39, 40, 41, 42, -1, -1, -1, -1, /* 0x700 - 0x7E0 */
  76          4,  5,  6,  7, -1, -1, -1, -1, /* 0x800 - 0x8E0 */
  77         -1, -1, -1, -1, -1, -1, -1, -1, /* 0x900 - 0x9E0 */
  78         12, 13, 14, 15, 16, 17, -1, -1, /* 0xA00 - 0xAE0 */
  79         -1, -1, -1, -1, -1, -1, -1, -1, /* 0xB00 - 0xBE0 */
  80         -1, -1, -1, -1, -1, -1, -1, -1, /* 0xC00 - 0xCE0 */
  81         -1, -1, -1, -1, -1, -1, -1, -1, /* 0xD00 - 0xDE0 */
  82         -1, -1                          /* 0xE00 - 0xE20 */
  83 };
  84
  85 /*
  86  * Opposite mapper.
  87  */
  88 static int IRQ_to_vectorN[NR_INTC_IRQS] = {
  89         0x12, 0x15, 0x18, 0x1B, 0x40, 0x41, 0x42, 0x43, /*  0- 7 */
  90           -1,   -1,   -1,   -1, 0x50, 0x51, 0x52, 0x53, /*  8-15 */
  91         0x54, 0x55, 0x32, 0x33, 0x34, 0x35, 0x36,   -1, /* 16-23 */
  92           -1,   -1,   -1,   -1,   -1,   -1,   -1,   -1, /* 24-31 */
  93         0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x38, /* 32-39 */
  94         0x39, 0x3A, 0x3B,   -1,   -1,   -1,   -1,   -1, /* 40-47 */
  95           -1,   -1,   -1,   -1,   -1,   -1,   -1,   -1, /* 48-55 */
  96           -1,   -1,   -1,   -1,   -1,   -1,   -1, 0x2B, /* 56-63 */
  97
  98 };
  99
 100 static unsigned long intc_virt;
 101
 102 static unsigned int startup_intc_irq(unsigned int irq);
 103 static void shutdown_intc_irq(unsigned int irq);
 104 static void enable_intc_irq(unsigned int irq);
 105 static void disable_intc_irq(unsigned int irq);
 106 static void mask_and_ack_intc(unsigned int);
 107 static void end_intc_irq(unsigned int irq);
 108
 109 static struct hw_interrupt_type intc_irq_type = {
 110         "INTC",
 111         startup_intc_irq,
 112         shutdown_intc_irq,
 113         enable_intc_irq,
 114         disable_intc_irq,
 115         mask_and_ack_intc,
 116         end_intc_irq
 117 };
 118
 119 static int irlm;                /* IRL mode */
 120
 121 static unsigned int startup_intc_irq(unsigned int irq)
 122 {
 123         enable_intc_irq(irq);
 124         return 0; /* never anything pending */
 125 }
 126
 127 static void shutdown_intc_irq(unsigned int irq)
 128 {
 129         disable_intc_irq(irq);
 130 }
 131
 132 static void enable_intc_irq(unsigned int irq)
 133 {
 134         unsigned long reg;
 135         unsigned long bitmask;
 136
 137         if ((irq <= IRQ_IRL3) && (irlm == NO_PRIORITY))
 138                 printk("Trying to use straight IRL0-3 with an encoding platform.\n");
 139
 140         if (irq < 32) {
 141                 reg = INTC_INTENB_0;
 142                 bitmask = 1 << irq;
 143         } else {
 144                 reg = INTC_INTENB_1;
 145                 bitmask = 1 << (irq - 32);
 146         }
 147
 148         ctrl_outl(bitmask, reg);
 149 }
 150
 151 static void disable_intc_irq(unsigned int irq)
 152 {
 153         unsigned long reg;
 154         unsigned long bitmask;
 155
 156         if (irq < 32) {
 157                 reg = INTC_INTDSB_0;
 158                 bitmask = 1 << irq;
 159         } else {
 160                 reg = INTC_INTDSB_1;
 161                 bitmask = 1 << (irq - 32);
 162         }
 163
 164         ctrl_outl(bitmask, reg);
 165 }
 166
 167 static void mask_and_ack_intc(unsigned int irq)
 168 {
 169         disable_intc_irq(irq);
 170 }
 171
 172 static void end_intc_irq(unsigned int irq)
 173 {
 174         enable_intc_irq(irq);
 175 }
 176
 177 /* For future use, if we ever support IRLM=0) */
 178 void make_intc_irq(unsigned int irq)
 179 {
 180         disable_irq_nosync(irq);
 181         irq_desc[irq].handler = &intc_irq_type;
 182         disable_intc_irq(irq);
 183 }
 184
 185 #if defined(CONFIG_PROC_FS) && defined(CONFIG_SYSCTL)
 186 int intc_irq_describe(char* p, int irq)
 187 {
 188         if (irq < NR_INTC_IRQS)
 189                 return sprintf(p, "(0x%3x)", IRQ_to_vectorN[irq]*0x20);
 190         else
 191                 return 0;
 192 }
 193 #endif
 194
 195 void __init init_IRQ(void)
 196 {
 197         unsigned long long __dummy0, __dummy1=~0x00000000100000f0;
 198         unsigned long reg;
 199         unsigned long data;
 200         int i;
 201
 202         intc_virt = onchip_remap(INTC_BASE, 1024, "INTC");
 203         if (!intc_virt) {
 204                 panic("Unable to remap INTC\n");
 205         }
 206
 207
 208         /* Set default: per-line enable/disable, priority driven ack/eoi */
 209         for (i = 0; i < NR_INTC_IRQS; i++) {
 210                 if (platform_int_priority[i] != NO_PRIORITY) {
 211                         irq_desc[i].handler = &intc_irq_type;
 212                 }
 213         }
 214
 215
 216         /* Disable all interrupts and set all priorities to 0 to avoid trouble */
 217         ctrl_outl(-1, INTC_INTDSB_0);
 218         ctrl_outl(-1, INTC_INTDSB_1);
 219
 220         for (reg = INTC_INTPRI_0, i = 0; i < INTC_INTPRI_PREGS; i++, reg += 8)
 221                 ctrl_outl( NO_PRIORITY, reg);
 222
 223
 224         /* Set IRLM */
 225         /* If all the priorities are set to 'no priority', then
 226          * assume we are using encoded mode.
 227          */
 228         irlm = platform_int_priority[IRQ_IRL0] + platform_int_priority[IRQ_IRL1] + \
 229                 platform_int_priority[IRQ_IRL2] + platform_int_priority[IRQ_IRL3];
 230
 231         if (irlm == NO_PRIORITY) {
 232                 /* IRLM = 0 */
 233                 reg = INTC_ICR_CLEAR;
 234                 i = IRQ_INTA;
 235                 printk("Trying to use encoded IRL0-3. IRLs unsupported.\n");
 236         } else {
 237                 /* IRLM = 1 */
 238                 reg = INTC_ICR_SET;
 239                 i = IRQ_IRL0;
 240         }
 241         ctrl_outl(INTC_ICR_IRLM, reg);
 242
 243         /* Set interrupt priorities according to platform description */
 244         for (data = 0, reg = INTC_INTPRI_0; i < NR_INTC_IRQS; i++) {
 245                 data |= platform_int_priority[i] << ((i % INTC_INTPRI_PPREG) * 4);
 246                 if ((i % INTC_INTPRI_PPREG) == (INTC_INTPRI_PPREG - 1)) {
 247                         /* Upon the 7th, set Priority Register */
 248                         ctrl_outl(data, reg);
 249                         data = 0;
 250                         reg += 8;
 251                 }
 252         }
 253
 254 #ifdef CONFIG_SH_CAYMAN
 255         {
 256                 extern void init_cayman_irq(void);
 257
 258                 init_cayman_irq();
 259         }
 260 #endif
 261
 262         /*
 263          * And now let interrupts come in.
 264          * sti() is not enough, we need to
 265          * lower priority, too.
 266          */
 267         __asm__ __volatile__("getcon    " __SR ", %0\n\t"
 268                              "and       %0, %1, %0\n\t"
 269                              "putcon    %0, " __SR "\n\t"
 270                              : "=&r" (__dummy0)
 271                              : "r" (__dummy1));
 272 }