1 /* $Id: semaphore.c,v 1.9 2001/11/18 00:12:56 davem Exp $
2 * semaphore.c: Sparc64 semaphore implementation.
4 * This is basically the PPC semaphore scheme ported to use
5 * the sparc64 atomic instructions, so see the PPC code for
9 #include <linux/sched.h>
10 #include <linux/errno.h>
11 #include <linux/init.h>
14 * Atomically update sem->count.
15 * This does the equivalent of the following:
17 * old_count = sem->count;
18 * tmp = MAX(old_count, 0) + incr;
22 static __inline__
int __sem_update_count(struct semaphore
*sem
, int incr
)
26 __asm__
__volatile__("\n"
27 " ! __sem_update_count old_count(%0) tmp(%1) incr(%4) &sem->count(%3)\n"
31 " movl %%icc, 0, %1\n"
36 " membar #StoreLoad | #StoreStore\n"
37 : "=&r" (old_count
), "=&r" (tmp
), "=m" (sem
->count
)
38 : "r" (&sem
->count
), "r" (incr
), "m" (sem
->count
)
44 static void __up(struct semaphore
*sem
)
46 __sem_update_count(sem
, 1);
50 void up(struct semaphore
*sem
)
52 /* This atomically does:
53 * old_val = sem->count;
54 * new_val = sem->count + 1;
55 * sem->count = new_val;
59 * The (old_val < 0) test is equivalent to
60 * the more straightforward (new_val <= 0),
61 * but it is easier to test the former because
62 * of how the CAS instruction works.
65 __asm__
__volatile__("\n"
67 " membar #StoreLoad | #LoadLoad\n"
68 "1: lduw [%0], %%g1\n"
69 " add %%g1, 1, %%g7\n"
70 " cas [%0], %%g1, %%g7\n"
73 " addcc %%g7, 1, %%g0\n"
75 " membar #StoreLoad | #StoreStore\n"
79 " save %%sp, -160, %%sp\n"
85 : : "r" (sem
), "i" (__up
)
86 : "g1", "g2", "g3", "g7", "memory", "cc");
89 static void __sched
__down(struct semaphore
* sem
)
91 struct task_struct
*tsk
= current
;
92 DECLARE_WAITQUEUE(wait
, tsk
);
94 tsk
->state
= TASK_UNINTERRUPTIBLE
;
95 add_wait_queue_exclusive(&sem
->wait
, &wait
);
97 while (__sem_update_count(sem
, -1) <= 0) {
99 tsk
->state
= TASK_UNINTERRUPTIBLE
;
101 remove_wait_queue(&sem
->wait
, &wait
);
102 tsk
->state
= TASK_RUNNING
;
107 void __sched
down(struct semaphore
*sem
)
110 /* This atomically does:
111 * old_val = sem->count;
112 * new_val = sem->count - 1;
113 * sem->count = new_val;
117 * The (old_val < 1) test is equivalent to
118 * the more straightforward (new_val < 0),
119 * but it is easier to test the former because
120 * of how the CAS instruction works.
123 __asm__
__volatile__("\n"
125 "1: lduw [%0], %%g1\n"
126 " sub %%g1, 1, %%g7\n"
127 " cas [%0], %%g1, %%g7\n"
129 " bne,pn %%icc, 1b\n"
132 " membar #StoreLoad | #StoreStore\n"
136 " save %%sp, -160, %%sp\n"
142 : : "r" (sem
), "i" (__down
)
143 : "g1", "g2", "g3", "g7", "memory", "cc");
146 int down_trylock(struct semaphore
*sem
)
150 /* This atomically does:
151 * old_val = sem->count;
152 * new_val = sem->count - 1;
156 * sem->count = new_val;
160 * The (old_val < 1) test is equivalent to
161 * the more straightforward (new_val < 0),
162 * but it is easier to test the former because
163 * of how the CAS instruction works.
166 __asm__
__volatile__("\n"
167 " ! down_trylock sem(%1) ret(%0)\n"
168 "1: lduw [%1], %%g1\n"
169 " sub %%g1, 1, %%g7\n"
173 " cas [%1], %%g1, %%g7\n"
175 " bne,pn %%icc, 1b\n"
177 " membar #StoreLoad | #StoreStore\n"
181 : "g1", "g7", "memory", "cc");
186 static int __sched
__down_interruptible(struct semaphore
* sem
)
189 struct task_struct
*tsk
= current
;
190 DECLARE_WAITQUEUE(wait
, tsk
);
192 tsk
->state
= TASK_INTERRUPTIBLE
;
193 add_wait_queue_exclusive(&sem
->wait
, &wait
);
195 while (__sem_update_count(sem
, -1) <= 0) {
196 if (signal_pending(current
)) {
197 __sem_update_count(sem
, 0);
202 tsk
->state
= TASK_INTERRUPTIBLE
;
204 tsk
->state
= TASK_RUNNING
;
205 remove_wait_queue(&sem
->wait
, &wait
);
210 int __sched
down_interruptible(struct semaphore
*sem
)
215 /* This atomically does:
216 * old_val = sem->count;
217 * new_val = sem->count - 1;
218 * sem->count = new_val;
220 * ret = __down_interruptible(sem);
222 * The (old_val < 1) test is equivalent to
223 * the more straightforward (new_val < 0),
224 * but it is easier to test the former because
225 * of how the CAS instruction works.
228 __asm__
__volatile__("\n"
229 " ! down_interruptible sem(%2) ret(%0)\n"
230 "1: lduw [%2], %%g1\n"
231 " sub %%g1, 1, %%g7\n"
232 " cas [%2], %%g1, %%g7\n"
234 " bne,pn %%icc, 1b\n"
237 " membar #StoreLoad | #StoreStore\n"
241 " save %%sp, -160, %%sp\n"
248 : "0" (ret
), "r" (sem
), "i" (__down_interruptible
)
249 : "g1", "g2", "g3", "g7", "memory", "cc");