arch/v850/kernel/gbus_int.c

   1 /*
   2  * arch/v850/kernel/gbus_int.c -- Midas labs GBUS interrupt support
   3  *
   4  *  Copyright (C) 2001,02,03  NEC Electronics Corporation
   5  *  Copyright (C) 2001,02,03  Miles Bader <miles@gnu.org>
   6  *
   7  * This file is subject to the terms and conditions of the GNU General
   8  * Public License.  See the file COPYING in the main directory of this
   9  * archive for more details.
  10  *
  11  * Written by Miles Bader <miles@gnu.org>
  12  */
  13
  14 #include <linux/types.h>
  15 #include <linux/init.h>
  16 #include <linux/irq.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/signal.h>
  19
  20 #include <asm/machdep.h>
  21
  22
  23 /* The number of shared GINT interrupts. */
  24 #define NUM_GINTS       4
  25
  26 /* For each GINT interrupt, how many GBUS interrupts are using it.  */
  27 static unsigned gint_num_active_irqs[NUM_GINTS] = { 0 };
  28
  29 /* A table of GINTn interrupts we actually use.
  30    Note that we don't use GINT0 because all the boards we support treat it
  31    specially.  */
  32 struct used_gint {
  33         unsigned gint;
  34         unsigned priority;
  35 } used_gint[] = {
  36         { 1, GBUS_INT_PRIORITY_HIGH },
  37         { 3, GBUS_INT_PRIORITY_LOW }
  38 };
  39 #define NUM_USED_GINTS  (sizeof used_gint / sizeof used_gint[0])
  40
  41 /* A table of which GINT is used by each GBUS interrupts (they are
  42    assigned based on priority).  */
  43 static unsigned char gbus_int_gint[IRQ_GBUS_INT_NUM];
  44
  45 \f
  46 /* Interrupt enabling/disabling.  */
  47
  48 /* Enable interrupt handling for interrupt IRQ.  */
  49 void gbus_int_enable_irq (unsigned irq)
  50 {
  51         unsigned gint = gbus_int_gint[irq - GBUS_INT_BASE_IRQ];
  52         GBUS_INT_ENABLE (GBUS_INT_IRQ_WORD(irq), gint)
  53                 |= GBUS_INT_IRQ_MASK (irq);
  54 }
  55
  56 /* Disable interrupt handling for interrupt IRQ.  Note that any
  57    interrupts received while disabled will be delivered once the
  58    interrupt is enabled again, unless they are explicitly cleared using
  59    `gbus_int_clear_pending_irq'.  */
  60 void gbus_int_disable_irq (unsigned irq)
  61 {
  62         unsigned gint = gbus_int_gint[irq - GBUS_INT_BASE_IRQ];
  63         GBUS_INT_ENABLE (GBUS_INT_IRQ_WORD(irq), gint)
  64                 &= ~GBUS_INT_IRQ_MASK (irq);
  65 }
  66
  67 /* Return true if interrupt handling for interrupt IRQ is enabled.  */
  68 int gbus_int_irq_enabled (unsigned irq)
  69 {
  70         unsigned gint = gbus_int_gint[irq - GBUS_INT_BASE_IRQ];
  71         return (GBUS_INT_ENABLE (GBUS_INT_IRQ_WORD(irq), gint)
  72                 & GBUS_INT_IRQ_MASK(irq));
  73 }
  74
  75 /* Disable all GBUS irqs.  */
  76 void gbus_int_disable_irqs ()
  77 {
  78         unsigned w, n;
  79         for (w = 0; w < GBUS_INT_NUM_WORDS; w++)
  80                 for (n = 0; n < IRQ_GINT_NUM; n++)
  81                         GBUS_INT_ENABLE (w, n) = 0;
  82 }
  83
  84 /* Clear any pending interrupts for IRQ.  */
  85 void gbus_int_clear_pending_irq (unsigned irq)
  86 {
  87         GBUS_INT_CLEAR (GBUS_INT_IRQ_WORD(irq)) = GBUS_INT_IRQ_MASK (irq);
  88 }
  89
  90 /* Return true if interrupt IRQ is pending (but disabled).  */
  91 int gbus_int_irq_pending (unsigned irq)
  92 {
  93         return (GBUS_INT_STATUS (GBUS_INT_IRQ_WORD(irq))
  94                 & GBUS_INT_IRQ_MASK(irq));
  95 }
  96
  97 \f
  98 /* Delegating interrupts.  */
  99
 100 /* Handle a shared GINT interrupt by passing to the appropriate GBUS
 101    interrupt handler.  */
 102 static irqreturn_t gbus_int_handle_irq (int irq, void *dev_id,
 103                                         struct pt_regs *regs)
 104 {
 105         unsigned w;
 106         irqreturn_t rval = IRQ_NONE;
 107         unsigned gint = irq - IRQ_GINT (0);
 108
 109         for (w = 0; w < GBUS_INT_NUM_WORDS; w++) {
 110                 unsigned status = GBUS_INT_STATUS (w);
 111                 unsigned enable = GBUS_INT_ENABLE (w, gint);
 112
 113                 /* Only pay attention to enabled interrupts.  */
 114                 status &= enable;
 115                 if (status) {
 116                         irq = IRQ_GBUS_INT (w * GBUS_INT_BITS_PER_WORD);
 117                         do {
 118                                 /* There's an active interrupt in word
 119                                    W, find out which one, and call its
 120                                    handler.  */
 121
 122                                 while (! (status & 0x1)) {
 123                                         irq++;
 124                                         status >>= 1;
 125                                 }
 126                                 status &= ~0x1;
 127
 128                                 /* Recursively call handle_irq to handle it. */
 129                                 handle_irq (irq, regs);
 130                                 rval = IRQ_HANDLED;
 131                         } while (status);
 132                 }
 133         }
 134
 135         /* Toggle the `all enable' bit back and forth, which should cause
 136            another edge transition if there are any other interrupts
 137            still pending, and so result in another CPU interrupt.  */
 138         GBUS_INT_ENABLE (0, gint) &= ~0x1;
 139         GBUS_INT_ENABLE (0, gint) |=  0x1;
 140
 141         return rval;
 142 }
 143
 144 \f
 145 /* Initialize GBUS interrupt sources.  */
 146
 147 static void irq_nop (unsigned irq) { }
 148
 149 static unsigned gbus_int_startup_irq (unsigned irq)
 150 {
 151         unsigned gint = gbus_int_gint[irq - GBUS_INT_BASE_IRQ];
 152
 153         if (gint_num_active_irqs[gint] == 0) {
 154                 /* First enable the CPU interrupt.  */
 155                 int rval =
 156                         request_irq (IRQ_GINT(gint), gbus_int_handle_irq,
 157                                      SA_INTERRUPT,
 158                                      "gbus_int_handler",
 159                                      &gint_num_active_irqs[gint]);
 160                 if (rval != 0)
 161                         return rval;
 162         }
 163
 164         gint_num_active_irqs[gint]++;
 165
 166         gbus_int_clear_pending_irq (irq);
 167         gbus_int_enable_irq (irq);
 168
 169         return 0;
 170 }
 171
 172 static void gbus_int_shutdown_irq (unsigned irq)
 173 {
 174         unsigned gint = gbus_int_gint[irq - GBUS_INT_BASE_IRQ];
 175
 176         gbus_int_disable_irq (irq);
 177
 178         if (--gint_num_active_irqs[gint] == 0)
 179                 /* Disable the CPU interrupt.  */
 180                 free_irq (IRQ_GINT(gint), &gint_num_active_irqs[gint]);
 181 }
 182
 183 /* Initialize HW_IRQ_TYPES for INTC-controlled irqs described in array
 184    INITS (which is terminated by an entry with the name field == 0).  */
 185 void __init gbus_int_init_irq_types (struct gbus_int_irq_init *inits,
 186                                      struct hw_interrupt_type *hw_irq_types)
 187 {
 188         struct gbus_int_irq_init *init;
 189         for (init = inits; init->name; init++) {
 190                 unsigned i;
 191                 struct hw_interrupt_type *hwit = hw_irq_types++;
 192
 193                 hwit->typename = init->name;
 194
 195                 hwit->startup  = gbus_int_startup_irq;
 196                 hwit->shutdown = gbus_int_shutdown_irq;
 197                 hwit->enable   = gbus_int_enable_irq;
 198                 hwit->disable  = gbus_int_disable_irq;
 199                 hwit->ack      = irq_nop;
 200                 hwit->end      = irq_nop;
 201
 202                 /* Initialize kernel IRQ infrastructure for this interrupt.  */
 203                 init_irq_handlers(init->base, init->num, init->interval, hwit);
 204
 205                 /* Set the interrupt priorities.  */
 206                 for (i = 0; i < init->num; i++) {
 207                         unsigned j;
 208                         for (j = 0; j < NUM_USED_GINTS; j++)
 209                                 if (used_gint[j].priority > init->priority)
 210                                         break;
 211                         /* Wherever we stopped looking is one past the
 212                            GINT we want. */
 213                         gbus_int_gint[init->base + i * init->interval
 214                                       - GBUS_INT_BASE_IRQ]
 215                                 = used_gint[j > 0 ? j - 1 : 0].gint;
 216                 }
 217         }
 218 }
 219
 220 \f
 221 /* Initialize IRQS.  */
 222
 223 /* Chip interrupts (GINTn) shared among GBUS interrupts.  */
 224 static struct hw_interrupt_type gint_hw_itypes[NUM_USED_GINTS];
 225
 226
 227 /* GBUS interrupts themselves.  */
 228
 229 struct gbus_int_irq_init gbus_irq_inits[] __initdata = {
 230         /* First set defaults.  */
 231         { "GBUS_INT", IRQ_GBUS_INT(0), IRQ_GBUS_INT_NUM, 1, 6},
 232         { 0 }
 233 };
 234 #define NUM_GBUS_IRQ_INITS  \
 235    ((sizeof gbus_irq_inits / sizeof gbus_irq_inits[0]) - 1)
 236
 237 static struct hw_interrupt_type gbus_hw_itypes[NUM_GBUS_IRQ_INITS];
 238
 239
 240 /* Initialize GBUS interrupts.  */
 241 void __init gbus_int_init_irqs (void)
 242 {
 243         unsigned i;
 244
 245         /* First initialize the shared gint interrupts.  */
 246         for (i = 0; i < NUM_USED_GINTS; i++) {
 247                 unsigned gint = used_gint[i].gint;
 248                 struct v850e_intc_irq_init gint_irq_init[2];
 249
 250                 /* We initialize one GINT interrupt at a time.  */
 251                 gint_irq_init[0].name = "GINT";
 252                 gint_irq_init[0].base = IRQ_GINT (gint);
 253                 gint_irq_init[0].num = 1;
 254                 gint_irq_init[0].interval = 1;
 255                 gint_irq_init[0].priority = used_gint[i].priority;
 256
 257                 gint_irq_init[1].name = 0; /* Terminate the vector.  */
 258
 259                 v850e_intc_init_irq_types (gint_irq_init, gint_hw_itypes);
 260         }
 261
 262         /* Then the GBUS interrupts.  */
 263         gbus_int_disable_irqs ();
 264         gbus_int_init_irq_types (gbus_irq_inits, gbus_hw_itypes);
 265         /* Turn on the `all enable' bits, which are ANDed with
 266            individual interrupt enable bits; we only want to bother with
 267            the latter.  They are the first bit in the first word of each
 268            interrupt-enable area.  */
 269         for (i = 0; i < NUM_USED_GINTS; i++)
 270                 GBUS_INT_ENABLE (0, used_gint[i].gint) = 0x1;
 271 }