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[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / drivers / ide / cris / ide-v10.c
blob5b40220d3ddceea457e12c6d8ab0961c36263211
1 /* $Id: ide.c,v 1.4 2004/10/12 07:55:48 starvik Exp $
2 *
3 * Etrax specific IDE functions, like init and PIO-mode setting etc.
4 * Almost the entire ide.c is used for the rest of the Etrax ATA driver.
5 * Copyright (c) 2000-2004 Axis Communications AB
6 *
7 * Authors: Bjorn Wesen (initial version)
8 * Mikael Starvik (pio setup stuff, Linux 2.6 port)
9 */
10
11 /* Regarding DMA:
12 *
13 * There are two forms of DMA - "DMA handshaking" between the interface and the drive,
14 * and DMA between the memory and the interface. We can ALWAYS use the latter, since it's
15 * something built-in in the Etrax. However only some drives support the DMA-mode handshaking
16 * on the ATA-bus. The normal PC driver and Triton interface disables memory-if DMA when the
17 * device can't do DMA handshaking for some stupid reason. We don't need to do that.
18 */
19
20 #undef REALLY_SLOW_IO /* most systems can safely undef this */
21
22 #include <linux/config.h>
23 #include <linux/types.h>
24 #include <linux/kernel.h>
25 #include <linux/timer.h>
26 #include <linux/mm.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/blkdev.h>
30 #include <linux/hdreg.h>
31 #include <linux/ide.h>
32 #include <linux/init.h>
33 #include <linux/scatterlist.h>
34
35 #include <asm/io.h>
36 #include <asm/arch/svinto.h>
37 #include <asm/dma.h>
38
39 /* number of Etrax DMA descriptors */
40 #define MAX_DMA_DESCRS 64
41
42 /* number of times to retry busy-flags when reading/writing IDE-registers
43 * this can't be too high because a hung harddisk might cause the watchdog
44 * to trigger (sometimes INB and OUTB are called with irq's disabled)
45 */
46
47 #define IDE_REGISTER_TIMEOUT 300
48
49 static int e100_read_command = 0;
50
51 #define LOWDB(x)
52 #define D(x)
53
54 static int e100_ide_build_dmatable (ide_drive_t *drive);
55 static ide_startstop_t etrax_dma_intr (ide_drive_t *drive);
56
57 void
58 etrax100_ide_outw(unsigned short data, unsigned long reg) {
59 int timeleft;
60 LOWDB(printk("ow: data 0x%x, reg 0x%x\n", data, reg));
61
62 /* note the lack of handling any timeouts. we stop waiting, but we don't
63 * really notify anybody.
64 */
65
66 timeleft = IDE_REGISTER_TIMEOUT;
67 /* wait for busy flag */
68 while(timeleft && (*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)))
69 timeleft--;
70
71 /*
72 * Fall through at a timeout, so the ongoing command will be
73 * aborted by the write below, which is expected to be a dummy
74 * command to the command register. This happens when a faulty
75 * drive times out on a command. See comment on timeout in
76 * INB.
77 */
78 if(!timeleft)
79 printk("ATA timeout reg 0x%lx := 0x%x\n", reg, data);
80
81 *R_ATA_CTRL_DATA = reg | data; /* write data to the drive's register */
82
83 timeleft = IDE_REGISTER_TIMEOUT;
84 /* wait for transmitter ready */
85 while(timeleft && !(*R_ATA_STATUS_DATA &
86 IO_MASK(R_ATA_STATUS_DATA, tr_rdy)))
87 timeleft--;
88 }
89
90 void
91 etrax100_ide_outb(unsigned char data, unsigned long reg)
92 {
93 etrax100_ide_outw(data, reg);
94 }
95
96 void
97 etrax100_ide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port)
98 {
99 etrax100_ide_outw(addr, port);
100 }
101
102 unsigned short
103 etrax100_ide_inw(unsigned long reg) {
104 int status;
105 int timeleft;
106
107 timeleft = IDE_REGISTER_TIMEOUT;
108 /* wait for busy flag */
109 while(timeleft && (*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)))
110 timeleft--;
111
112 if(!timeleft) {
113 /*
114 * If we're asked to read the status register, like for
115 * example when a command does not complete for an
116 * extended time, but the ATA interface is stuck in a
117 * busy state at the *ETRAX* ATA interface level (as has
118 * happened repeatedly with at least one bad disk), then
119 * the best thing to do is to pretend that we read
120 * "busy" in the status register, so the IDE driver will
121 * time-out, abort the ongoing command and perform a
122 * reset sequence. Note that the subsequent OUT_BYTE
123 * call will also timeout on busy, but as long as the
124 * write is still performed, everything will be fine.
125 */
126 if ((reg & IO_MASK (R_ATA_CTRL_DATA, addr))
127 == IO_FIELD (R_ATA_CTRL_DATA, addr, IDE_STATUS_OFFSET))
128 return BUSY_STAT;
129 else
130 /* For other rare cases we assume 0 is good enough. */
131 return 0;
132 }
133
134 *R_ATA_CTRL_DATA = reg | IO_STATE(R_ATA_CTRL_DATA, rw, read); /* read data */
135
136 timeleft = IDE_REGISTER_TIMEOUT;
137 /* wait for available */
138 while(timeleft && !((status = *R_ATA_STATUS_DATA) &
139 IO_MASK(R_ATA_STATUS_DATA, dav)))
140 timeleft--;
141
142 if(!timeleft)
143 return 0;
144
145 LOWDB(printk("inb: 0x%x from reg 0x%x\n", status & 0xff, reg));
146
147 return (unsigned short)status;
148 }
149
150 unsigned char
151 etrax100_ide_inb(unsigned long reg)
152 {
153 return (unsigned char)etrax100_ide_inw(reg);
154 }
155
156 /* PIO timing (in R_ATA_CONFIG)
157 *
158 * _____________________________
159 * ADDRESS : ________/
160 *
161 * _______________
162 * DIOR : ____________/ \__________
163 *
164 * _______________
165 * DATA : XXXXXXXXXXXXXXXX_______________XXXXXXXX
166 *
167 *
168 * DIOR is unbuffered while address and data is buffered.
169 * This creates two problems:
170 * 1. The DIOR pulse is to early (because it is unbuffered)
171 * 2. The rise time of DIOR is long
172 *
173 * There are at least three different plausible solutions
174 * 1. Use a pad capable of larger currents in Etrax
175 * 2. Use an external buffer
176 * 3. Make the strobe pulse longer
177 *
178 * Some of the strobe timings below are modified to compensate
179 * for this. This implies a slight performance decrease.
180 *
181 * THIS SHOULD NEVER BE CHANGED!
182 *
183 * TODO: Is this true for the latest LX boards still ?
184 */
185
186 #define ATA_DMA2_STROBE 4
187 #define ATA_DMA2_HOLD 0
188 #define ATA_DMA1_STROBE 4
189 #define ATA_DMA1_HOLD 1
190 #define ATA_DMA0_STROBE 12
191 #define ATA_DMA0_HOLD 9
192 #define ATA_PIO4_SETUP 1
193 #define ATA_PIO4_STROBE 5
194 #define ATA_PIO4_HOLD 0
195 #define ATA_PIO3_SETUP 1
196 #define ATA_PIO3_STROBE 5
197 #define ATA_PIO3_HOLD 1
198 #define ATA_PIO2_SETUP 1
199 #define ATA_PIO2_STROBE 6
200 #define ATA_PIO2_HOLD 2
201 #define ATA_PIO1_SETUP 2
202 #define ATA_PIO1_STROBE 11
203 #define ATA_PIO1_HOLD 4
204 #define ATA_PIO0_SETUP 4
205 #define ATA_PIO0_STROBE 19
206 #define ATA_PIO0_HOLD 4
207
208 static int e100_dma_check (ide_drive_t *drive);
209 static void e100_dma_start(ide_drive_t *drive);
210 static int e100_dma_end (ide_drive_t *drive);
211 static void e100_ide_input_data (ide_drive_t *drive, void *, unsigned int);
212 static void e100_ide_output_data (ide_drive_t *drive, void *, unsigned int);
213 static void e100_atapi_input_bytes(ide_drive_t *drive, void *, unsigned int);
214 static void e100_atapi_output_bytes(ide_drive_t *drive, void *, unsigned int);
215 static int e100_dma_off (ide_drive_t *drive);
216
217
218 /*
219 * good_dma_drives() lists the model names (from "hdparm -i")
220 * of drives which do not support mword2 DMA but which are
221 * known to work fine with this interface under Linux.
222 */
223
224 const char *good_dma_drives[] = {"Micropolis 2112A",
225 "CONNER CTMA 4000",
226 "CONNER CTT8000-A",
227 NULL};
228
229 static void tune_e100_ide(ide_drive_t *drive, byte pio)
230 {
231 pio = 4;
232 /* pio = ide_get_best_pio_mode(drive, pio, 4, NULL); */
233
234 /* set pio mode! */
235
236 switch(pio) {
237 case 0:
238 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) |
239 IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
240 IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) |
241 IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO0_SETUP ) |
242 IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO0_STROBE ) |
243 IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO0_HOLD ) );
244 break;
245 case 1:
246 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) |
247 IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
248 IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) |
249 IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO1_SETUP ) |
250 IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO1_STROBE ) |
251 IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO1_HOLD ) );
252 break;
253 case 2:
254 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) |
255 IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
256 IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) |
257 IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO2_SETUP ) |
258 IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO2_STROBE ) |
259 IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO2_HOLD ) );
260 break;
261 case 3:
262 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) |
263 IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
264 IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) |
265 IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO3_SETUP ) |
266 IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO3_STROBE ) |
267 IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO3_HOLD ) );
268 break;
269 case 4:
270 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) |
271 IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
272 IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) |
273 IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO4_SETUP ) |
274 IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO4_STROBE ) |
275 IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO4_HOLD ) );
276 break;
277 }
278 }
279
280 static int e100_dma_setup(ide_drive_t *drive)
281 {
282 struct request *rq = drive->hwif->hwgroup->rq;
283
284 if (rq_data_dir(rq)) {
285 e100_read_command = 0;
286
287 RESET_DMA(ATA_TX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */
288 WAIT_DMA(ATA_TX_DMA_NBR);
289 } else {
290 e100_read_command = 1;
291
292 RESET_DMA(ATA_RX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */
293 WAIT_DMA(ATA_RX_DMA_NBR);
294 }
295
296 /* set up the Etrax DMA descriptors */
297 if (e100_ide_build_dmatable(drive)) {
298 ide_map_sg(drive, rq);
299 return 1;
300 }
301
302 return 0;
303 }
304
305 static void e100_dma_exec_cmd(ide_drive_t *drive, u8 command)
306 {
307 /* set the irq handler which will finish the request when DMA is done */
308 ide_set_handler(drive, &etrax_dma_intr, WAIT_CMD, NULL);
309
310 /* issue cmd to drive */
311 etrax100_ide_outb(command, IDE_COMMAND_REG);
312 }
313
314 void __init
315 init_e100_ide (void)
316 {
317 volatile unsigned int dummy;
318 int h;
319
320 printk("ide: ETRAX 100LX built-in ATA DMA controller\n");
321
322 /* first fill in some stuff in the ide_hwifs fields */
323
324 for(h = 0; h < MAX_HWIFS; h++) {
325 ide_hwif_t *hwif = &ide_hwifs[h];
326 hwif->mmio = 2;
327 hwif->chipset = ide_etrax100;
328 hwif->tuneproc = &tune_e100_ide;
329 hwif->ata_input_data = &e100_ide_input_data;
330 hwif->ata_output_data = &e100_ide_output_data;
331 hwif->atapi_input_bytes = &e100_atapi_input_bytes;
332 hwif->atapi_output_bytes = &e100_atapi_output_bytes;
333 hwif->ide_dma_check = &e100_dma_check;
334 hwif->ide_dma_end = &e100_dma_end;
335 hwif->dma_setup = &e100_dma_setup;
336 hwif->dma_exec_cmd = &e100_dma_exec_cmd;
337 hwif->dma_start = &e100_dma_start;
338 hwif->OUTB = &etrax100_ide_outb;
339 hwif->OUTW = &etrax100_ide_outw;
340 hwif->OUTBSYNC = &etrax100_ide_outbsync;
341 hwif->INB = &etrax100_ide_inb;
342 hwif->INW = &etrax100_ide_inw;
343 hwif->ide_dma_off_quietly = &e100_dma_off;
344 }
345
346 /* actually reset and configure the etrax100 ide/ata interface */
347
348 *R_ATA_CTRL_DATA = 0;
349 *R_ATA_TRANSFER_CNT = 0;
350 *R_ATA_CONFIG = 0;
351
352 genconfig_shadow = (genconfig_shadow &
353 ~IO_MASK(R_GEN_CONFIG, dma2) &
354 ~IO_MASK(R_GEN_CONFIG, dma3) &
355 ~IO_MASK(R_GEN_CONFIG, ata)) |
356 ( IO_STATE( R_GEN_CONFIG, dma3, ata ) |
357 IO_STATE( R_GEN_CONFIG, dma2, ata ) |
358 IO_STATE( R_GEN_CONFIG, ata, select ) );
359
360 *R_GEN_CONFIG = genconfig_shadow;
361
362 /* pull the chosen /reset-line low */
363
364 #ifdef CONFIG_ETRAX_IDE_G27_RESET
365 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, 27, 0);
366 #endif
367 #ifdef CONFIG_ETRAX_IDE_CSE1_16_RESET
368 REG_SHADOW_SET(port_cse1_addr, port_cse1_shadow, 16, 0);
369 #endif
370 #ifdef CONFIG_ETRAX_IDE_CSP0_8_RESET
371 REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, 8, 0);
372 #endif
373 #ifdef CONFIG_ETRAX_IDE_PB7_RESET
374 port_pb_dir_shadow = port_pb_dir_shadow |
375 IO_STATE(R_PORT_PB_DIR, dir7, output);
376 *R_PORT_PB_DIR = port_pb_dir_shadow;
377 REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 7, 1);
378 #endif
379
380 /* wait some */
381
382 udelay(25);
383
384 /* de-assert bus-reset */
385
386 #ifdef CONFIG_ETRAX_IDE_CSE1_16_RESET
387 REG_SHADOW_SET(port_cse1_addr, port_cse1_shadow, 16, 1);
388 #endif
389 #ifdef CONFIG_ETRAX_IDE_CSP0_8_RESET
390 REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, 8, 1);
391 #endif
392 #ifdef CONFIG_ETRAX_IDE_G27_RESET
393 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, 27, 1);
394 #endif
395
396 /* make a dummy read to set the ata controller in a proper state */
397 dummy = *R_ATA_STATUS_DATA;
398
399 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) |
400 IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
401 IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) |
402 IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO4_SETUP ) |
403 IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO4_STROBE ) |
404 IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO4_HOLD ) );
405
406 *R_ATA_CTRL_DATA = ( IO_STATE( R_ATA_CTRL_DATA, rw, read) |
407 IO_FIELD( R_ATA_CTRL_DATA, addr, 1 ) );
408
409 while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)); /* wait for busy flag*/
410
411 *R_IRQ_MASK0_SET = ( IO_STATE( R_IRQ_MASK0_SET, ata_irq0, set ) |
412 IO_STATE( R_IRQ_MASK0_SET, ata_irq1, set ) |
413 IO_STATE( R_IRQ_MASK0_SET, ata_irq2, set ) |
414 IO_STATE( R_IRQ_MASK0_SET, ata_irq3, set ) );
415
416 printk("ide: waiting %d seconds for drives to regain consciousness\n",
417 CONFIG_ETRAX_IDE_DELAY);
418
419 h = jiffies + (CONFIG_ETRAX_IDE_DELAY * HZ);
420 while(time_before(jiffies, h)) /* nothing */ ;
421
422 /* reset the dma channels we will use */
423
424 RESET_DMA(ATA_TX_DMA_NBR);
425 RESET_DMA(ATA_RX_DMA_NBR);
426 WAIT_DMA(ATA_TX_DMA_NBR);
427 WAIT_DMA(ATA_RX_DMA_NBR);
428
429 }
430
431 static int e100_dma_off (ide_drive_t *drive)
432 {
433 return 0;
434 }
435
436 static etrax_dma_descr mydescr;
437
438 /*
439 * The following routines are mainly used by the ATAPI drivers.
440 *
441 * These routines will round up any request for an odd number of bytes,
442 * so if an odd bytecount is specified, be sure that there's at least one
443 * extra byte allocated for the buffer.
444 */
445 static void
446 e100_atapi_input_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount)
447 {
448 unsigned long data_reg = IDE_DATA_REG;
449
450 D(printk("atapi_input_bytes, dreg 0x%x, buffer 0x%x, count %d\n",
451 data_reg, buffer, bytecount));
452
453 if(bytecount & 1) {
454 printk("warning, odd bytecount in cdrom_in_bytes = %d.\n", bytecount);
455 bytecount++; /* to round off */
456 }
457
458 /* make sure the DMA channel is available */
459 RESET_DMA(ATA_RX_DMA_NBR);
460 WAIT_DMA(ATA_RX_DMA_NBR);
461
462 /* setup DMA descriptor */
463
464 mydescr.sw_len = bytecount;
465 mydescr.ctrl = d_eol;
466 mydescr.buf = virt_to_phys(buffer);
467
468 /* start the dma channel */
469
470 *R_DMA_CH3_FIRST = virt_to_phys(&mydescr);
471 *R_DMA_CH3_CMD = IO_STATE(R_DMA_CH3_CMD, cmd, start);
472
473 /* initiate a multi word dma read using PIO handshaking */
474
475 *R_ATA_TRANSFER_CNT = IO_FIELD(R_ATA_TRANSFER_CNT, count, bytecount >> 1);
476
477 *R_ATA_CTRL_DATA = data_reg |
478 IO_STATE(R_ATA_CTRL_DATA, rw, read) |
479 IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) |
480 IO_STATE(R_ATA_CTRL_DATA, handsh, pio) |
481 IO_STATE(R_ATA_CTRL_DATA, multi, on) |
482 IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
483
484 /* wait for completion */
485
486 LED_DISK_READ(1);
487 WAIT_DMA(ATA_RX_DMA_NBR);
488 LED_DISK_READ(0);
489
490 #if 0
491 /* old polled transfer code
492 * this should be moved into a new function that can do polled
493 * transfers if DMA is not available
494 */
495
496 /* initiate a multi word read */
497
498 *R_ATA_TRANSFER_CNT = wcount << 1;
499
500 *R_ATA_CTRL_DATA = data_reg |
501 IO_STATE(R_ATA_CTRL_DATA, rw, read) |
502 IO_STATE(R_ATA_CTRL_DATA, src_dst, register) |
503 IO_STATE(R_ATA_CTRL_DATA, handsh, pio) |
504 IO_STATE(R_ATA_CTRL_DATA, multi, on) |
505 IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
506
507 /* svinto has a latency until the busy bit actually is set */
508
509 nop(); nop();
510 nop(); nop();
511 nop(); nop();
512 nop(); nop();
513 nop(); nop();
514
515 /* unit should be busy during multi transfer */
516 while((status = *R_ATA_STATUS_DATA) & IO_MASK(R_ATA_STATUS_DATA, busy)) {
517 while(!(status & IO_MASK(R_ATA_STATUS_DATA, dav)))
518 status = *R_ATA_STATUS_DATA;
519 *ptr++ = (unsigned short)(status & 0xffff);
520 }
521 #endif
522 }
523
524 static void
525 e100_atapi_output_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount)
526 {
527 unsigned long data_reg = IDE_DATA_REG;
528
529 D(printk("atapi_output_bytes, dreg 0x%x, buffer 0x%x, count %d\n",
530 data_reg, buffer, bytecount));
531
532 if(bytecount & 1) {
533 printk("odd bytecount %d in atapi_out_bytes!\n", bytecount);
534 bytecount++;
535 }
536
537 /* make sure the DMA channel is available */
538 RESET_DMA(ATA_TX_DMA_NBR);
539 WAIT_DMA(ATA_TX_DMA_NBR);
540
541 /* setup DMA descriptor */
542
543 mydescr.sw_len = bytecount;
544 mydescr.ctrl = d_eol;
545 mydescr.buf = virt_to_phys(buffer);
546
547 /* start the dma channel */
548
549 *R_DMA_CH2_FIRST = virt_to_phys(&mydescr);
550 *R_DMA_CH2_CMD = IO_STATE(R_DMA_CH2_CMD, cmd, start);
551
552 /* initiate a multi word dma write using PIO handshaking */
553
554 *R_ATA_TRANSFER_CNT = IO_FIELD(R_ATA_TRANSFER_CNT, count, bytecount >> 1);
555
556 *R_ATA_CTRL_DATA = data_reg |
557 IO_STATE(R_ATA_CTRL_DATA, rw, write) |
558 IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) |
559 IO_STATE(R_ATA_CTRL_DATA, handsh, pio) |
560 IO_STATE(R_ATA_CTRL_DATA, multi, on) |
561 IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
562
563 /* wait for completion */
564
565 LED_DISK_WRITE(1);
566 WAIT_DMA(ATA_TX_DMA_NBR);
567 LED_DISK_WRITE(0);
568
569 #if 0
570 /* old polled write code - see comment in input_bytes */
571
572 /* wait for busy flag */
573 while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy));
574
575 /* initiate a multi word write */
576
577 *R_ATA_TRANSFER_CNT = bytecount >> 1;
578
579 ctrl = data_reg |
580 IO_STATE(R_ATA_CTRL_DATA, rw, write) |
581 IO_STATE(R_ATA_CTRL_DATA, src_dst, register) |
582 IO_STATE(R_ATA_CTRL_DATA, handsh, pio) |
583 IO_STATE(R_ATA_CTRL_DATA, multi, on) |
584 IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
585
586 LED_DISK_WRITE(1);
587
588 /* Etrax will set busy = 1 until the multi pio transfer has finished
589 * and tr_rdy = 1 after each successful word transfer.
590 * When the last byte has been transferred Etrax will first set tr_tdy = 1
591 * and then busy = 0 (not in the same cycle). If we read busy before it
592 * has been set to 0 we will think that we should transfer more bytes
593 * and then tr_rdy would be 0 forever. This is solved by checking busy
594 * in the inner loop.
595 */
596
597 do {
598 *R_ATA_CTRL_DATA = ctrl | *ptr++;
599 while(!(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, tr_rdy)) &&
600 (*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)));
601 } while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy));
602
603 LED_DISK_WRITE(0);
604 #endif
605
606 }
607
608 /*
609 * This is used for most PIO data transfers *from* the IDE interface
610 */
611 static void
612 e100_ide_input_data (ide_drive_t *drive, void *buffer, unsigned int wcount)
613 {
614 e100_atapi_input_bytes(drive, buffer, wcount << 2);
615 }
616
617 /*
618 * This is used for most PIO data transfers *to* the IDE interface
619 */
620 static void
621 e100_ide_output_data (ide_drive_t *drive, void *buffer, unsigned int wcount)
622 {
623 e100_atapi_output_bytes(drive, buffer, wcount << 2);
624 }
625
626 /* we only have one DMA channel on the chip for ATA, so we can keep these statically */
627 static etrax_dma_descr ata_descrs[MAX_DMA_DESCRS];
628 static unsigned int ata_tot_size;
629
630 /*
631 * e100_ide_build_dmatable() prepares a dma request.
632 * Returns 0 if all went okay, returns 1 otherwise.
633 */
634 static int e100_ide_build_dmatable (ide_drive_t *drive)
635 {
636 ide_hwif_t *hwif = HWIF(drive);
637 struct scatterlist* sg;
638 struct request *rq = HWGROUP(drive)->rq;
639 unsigned long size, addr;
640 unsigned int count = 0;
641 int i = 0;
642
643 sg = hwif->sg_table;
644
645 ata_tot_size = 0;
646
647 ide_map_sg(drive, rq);
648
649 i = hwif->sg_nents;
650
651 while(i) {
652 /*
653 * Determine addr and size of next buffer area. We assume that
654 * individual virtual buffers are always composed linearly in
655 * physical memory. For example, we assume that any 8kB buffer
656 * is always composed of two adjacent physical 4kB pages rather
657 * than two possibly non-adjacent physical 4kB pages.
658 */
659 /* group sequential buffers into one large buffer */
660 addr = page_to_phys(sg->page) + sg->offset;
661 size = sg_dma_len(sg);
662 while (sg++, --i) {
663 if ((addr + size) != page_to_phys(sg->page) + sg->offset)
664 break;
665 size += sg_dma_len(sg);
666 }
667
668 /* did we run out of descriptors? */
669
670 if(count >= MAX_DMA_DESCRS) {
671 printk("%s: too few DMA descriptors\n", drive->name);
672 return 1;
673 }
674
675 /* however, this case is more difficult - R_ATA_TRANSFER_CNT cannot be more
676 than 65536 words per transfer, so in that case we need to either
677 1) use a DMA interrupt to re-trigger R_ATA_TRANSFER_CNT and continue with
678 the descriptors, or
679 2) simply do the request here, and get dma_intr to only ide_end_request on
680 those blocks that were actually set-up for transfer.
681 */
682
683 if(ata_tot_size + size > 131072) {
684 printk("too large total ATA DMA request, %d + %d!\n", ata_tot_size, (int)size);
685 return 1;
686 }
687
688 /* If size > 65536 it has to be splitted into new descriptors. Since we don't handle
689 size > 131072 only one split is necessary */
690
691 if(size > 65536) {
692 /* ok we want to do IO at addr, size bytes. set up a new descriptor entry */
693 ata_descrs[count].sw_len = 0; /* 0 means 65536, this is a 16-bit field */
694 ata_descrs[count].ctrl = 0;
695 ata_descrs[count].buf = addr;
696 ata_descrs[count].next = virt_to_phys(&ata_descrs[count + 1]);
697 count++;
698 ata_tot_size += 65536;
699 /* size and addr should refere to not handled data */
700 size -= 65536;
701 addr += 65536;
702 }
703 /* ok we want to do IO at addr, size bytes. set up a new descriptor entry */
704 if(size == 65536) {
705 ata_descrs[count].sw_len = 0; /* 0 means 65536, this is a 16-bit field */
706 } else {
707 ata_descrs[count].sw_len = size;
708 }
709 ata_descrs[count].ctrl = 0;
710 ata_descrs[count].buf = addr;
711 ata_descrs[count].next = virt_to_phys(&ata_descrs[count + 1]);
712 count++;
713 ata_tot_size += size;
714 }
715
716 if (count) {
717 /* set the end-of-list flag on the last descriptor */
718 ata_descrs[count - 1].ctrl |= d_eol;
719 /* return and say all is ok */
720 return 0;
721 }
722
723 printk("%s: empty DMA table?\n", drive->name);
724 return 1; /* let the PIO routines handle this weirdness */
725 }
726
727 static int config_drive_for_dma (ide_drive_t *drive)
728 {
729 const char **list;
730 struct hd_driveid *id = drive->id;
731
732 if (id && (id->capability & 1)) {
733 /* Enable DMA on any drive that supports mword2 DMA */
734 if ((id->field_valid & 2) && (id->dma_mword & 0x404) == 0x404) {
735 drive->using_dma = 1;
736 return 0; /* DMA enabled */
737 }
738
739 /* Consult the list of known "good" drives */
740 list = good_dma_drives;
741 while (*list) {
742 if (!strcmp(*list++,id->model)) {
743 drive->using_dma = 1;
744 return 0; /* DMA enabled */
745 }
746 }
747 }
748 return 1; /* DMA not enabled */
749 }
750
751 /*
752 * etrax_dma_intr() is the handler for disk read/write DMA interrupts
753 */
754 static ide_startstop_t etrax_dma_intr (ide_drive_t *drive)
755 {
756 LED_DISK_READ(0);
757 LED_DISK_WRITE(0);
758
759 return ide_dma_intr(drive);
760 }
761
762 /*
763 * Functions below initiates/aborts DMA read/write operations on a drive.
764 *
765 * The caller is assumed to have selected the drive and programmed the drive's
766 * sector address using CHS or LBA. All that remains is to prepare for DMA
767 * and then issue the actual read/write DMA/PIO command to the drive.
768 *
769 * Returns 0 if all went well.
770 * Returns 1 if DMA read/write could not be started, in which case
771 * the caller should revert to PIO for the current request.
772 */
773
774 static int e100_dma_check(ide_drive_t *drive)
775 {
776 return config_drive_for_dma (drive);
777 }
778
779 static int e100_dma_end(ide_drive_t *drive)
780 {
781 /* TODO: check if something went wrong with the DMA */
782 return 0;
783 }
784
785 static void e100_dma_start(ide_drive_t *drive)
786 {
787 if (e100_read_command) {
788 /* begin DMA */
789
790 /* need to do this before RX DMA due to a chip bug
791 * it is enough to just flush the part of the cache that
792 * corresponds to the buffers we start, but since HD transfers
793 * usually are more than 8 kB, it is easier to optimize for the
794 * normal case and just flush the entire cache. its the only
795 * way to be sure! (OB movie quote)
796 */
797 flush_etrax_cache();
798 *R_DMA_CH3_FIRST = virt_to_phys(ata_descrs);
799 *R_DMA_CH3_CMD = IO_STATE(R_DMA_CH3_CMD, cmd, start);
800
801 /* initiate a multi word dma read using DMA handshaking */
802
803 *R_ATA_TRANSFER_CNT =
804 IO_FIELD(R_ATA_TRANSFER_CNT, count, ata_tot_size >> 1);
805
806 *R_ATA_CTRL_DATA =
807 IO_FIELD(R_ATA_CTRL_DATA, data, IDE_DATA_REG) |
808 IO_STATE(R_ATA_CTRL_DATA, rw, read) |
809 IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) |
810 IO_STATE(R_ATA_CTRL_DATA, handsh, dma) |
811 IO_STATE(R_ATA_CTRL_DATA, multi, on) |
812 IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
813
814 LED_DISK_READ(1);
815
816 D(printk("dma read of %d bytes.\n", ata_tot_size));
817
818 } else {
819 /* writing */
820 /* begin DMA */
821
822 *R_DMA_CH2_FIRST = virt_to_phys(ata_descrs);
823 *R_DMA_CH2_CMD = IO_STATE(R_DMA_CH2_CMD, cmd, start);
824
825 /* initiate a multi word dma write using DMA handshaking */
826
827 *R_ATA_TRANSFER_CNT =
828 IO_FIELD(R_ATA_TRANSFER_CNT, count, ata_tot_size >> 1);
829
830 *R_ATA_CTRL_DATA =
831 IO_FIELD(R_ATA_CTRL_DATA, data, IDE_DATA_REG) |
832 IO_STATE(R_ATA_CTRL_DATA, rw, write) |
833 IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) |
834 IO_STATE(R_ATA_CTRL_DATA, handsh, dma) |
835 IO_STATE(R_ATA_CTRL_DATA, multi, on) |
836 IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
837
838 LED_DISK_WRITE(1);
839
840 D(printk("dma write of %d bytes.\n", ata_tot_size));
841 }
842 }
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