drivers/ide/pci/cy82c693.c

   1 /*
   2  * linux/drivers/ide/pci/cy82c693.c             Version 0.40    Sep. 10, 2002
   3  *
   4  *  Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
   5  *  Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
   6  *
   7  * CYPRESS CY82C693 chipset IDE controller
   8  *
   9  * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
  10  * Writing the driver was quite simple, since most of the job is
  11  * done by the generic pci-ide support.
  12  * The hard part was finding the CY82C693's datasheet on Cypress's
  13  * web page :-(. But Altavista solved this problem :-).
  14  *
  15  *
  16  * Notes:
  17  * - I recently got a 16.8G IBM DTTA, so I was able to test it with
  18  *   a large and fast disk - the results look great, so I'd say the
  19  *   driver is working fine :-)
  20  *   hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA
  21  * - this is my first linux driver, so there's probably a lot  of room
  22  *   for optimizations and bug fixing, so feel free to do it.
  23  * - use idebus=xx parameter to set PCI bus speed - needed to calc
  24  *   timings for PIO modes (default will be 40)
  25  * - if using PIO mode it's a good idea to set the PIO mode and
  26  *   32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda
  27  * - I had some problems with my IBM DHEA with PIO modes < 2
  28  *   (lost interrupts) ?????
  29  * - first tests with DMA look okay, they seem to work, but there is a
  30  *   problem with sound - the BusMaster IDE TimeOut should fixed this
  31  *
  32  * Ancient History:
  33  * AMH@1999-08-24: v0.34 init_cy82c693_chip moved to pci_init_cy82c693
  34  * ASK@1999-01-23: v0.33 made a few minor code clean ups
  35  *                       removed DMA clock speed setting by default
  36  *                       added boot message
  37  * ASK@1998-11-01: v0.32 added support to set BusMaster IDE TimeOut
  38  *                       added support to set DMA Controller Clock Speed
  39  * ASK@1998-10-31: v0.31 fixed problem with setting to high DMA modes
  40  *                       on some drives.
  41  * ASK@1998-10-29: v0.3 added support to set DMA modes
  42  * ASK@1998-10-28: v0.2 added support to set PIO modes
  43  * ASK@1998-10-27: v0.1 first version - chipset detection
  44  *
  45  */
  46
  47 #include <linux/config.h>
  48 #include <linux/module.h>
  49 #include <linux/types.h>
  50 #include <linux/pci.h>
  51 #include <linux/delay.h>
  52 #include <linux/ide.h>
  53 #include <linux/init.h>
  54
  55 #include <asm/io.h>
  56
  57 /* the current version */
  58 #define CY82_VERSION    "CY82C693U driver v0.34 99-13-12 Andreas S. Krebs (akrebs@altavista.net)"
  59
  60 /*
  61  *      The following are used to debug the driver.
  62  */
  63 #define CY82C693_DEBUG_LOGS     0
  64 #define CY82C693_DEBUG_INFO     0
  65
  66 /* define CY82C693_SETDMA_CLOCK to set DMA Controller Clock Speed to ATCLK */
  67 #undef CY82C693_SETDMA_CLOCK
  68
  69 /*
  70  *      NOTE: the value for busmaster timeout is tricky and I got it by
  71  *      trial and error!  By using a to low value will cause DMA timeouts
  72  *      and drop IDE performance, and by using a to high value will cause
  73  *      audio playback to scatter.
  74  *      If you know a better value or how to calc it, please let me know.
  75  */
  76
  77 /* twice the value written in cy82c693ub datasheet */
  78 #define BUSMASTER_TIMEOUT       0x50
  79 /*
  80  * the value above was tested on my machine and it seems to work okay
  81  */
  82
  83 /* here are the offset definitions for the registers */
  84 #define CY82_IDE_CMDREG         0x04
  85 #define CY82_IDE_ADDRSETUP      0x48
  86 #define CY82_IDE_MASTER_IOR     0x4C
  87 #define CY82_IDE_MASTER_IOW     0x4D
  88 #define CY82_IDE_SLAVE_IOR      0x4E
  89 #define CY82_IDE_SLAVE_IOW      0x4F
  90 #define CY82_IDE_MASTER_8BIT    0x50
  91 #define CY82_IDE_SLAVE_8BIT     0x51
  92
  93 #define CY82_INDEX_PORT         0x22
  94 #define CY82_DATA_PORT          0x23
  95
  96 #define CY82_INDEX_CTRLREG1     0x01
  97 #define CY82_INDEX_CHANNEL0     0x30
  98 #define CY82_INDEX_CHANNEL1     0x31
  99 #define CY82_INDEX_TIMEOUT      0x32
 100
 101 /* the max PIO mode - from datasheet */
 102 #define CY82C693_MAX_PIO        4
 103
 104 /* the min and max PCI bus speed in MHz - from datasheet */
 105 #define CY82C963_MIN_BUS_SPEED  25
 106 #define CY82C963_MAX_BUS_SPEED  33
 107
 108 /* the struct for the PIO mode timings */
 109 typedef struct pio_clocks_s {
 110         u8      address_time;   /* Address setup (clocks) */
 111         u8      time_16r;       /* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */
 112         u8      time_16w;       /* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */
 113         u8      time_8;         /* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */
 114 } pio_clocks_t;
 115
 116 /*
 117  * calc clocks using bus_speed
 118  * returns (rounded up) time in bus clocks for time in ns
 119  */
 120 static int calc_clk (int time, int bus_speed)
 121 {
 122         int clocks;
 123
 124         clocks = (time*bus_speed+999)/1000 -1;
 125
 126         if (clocks < 0)
 127                 clocks = 0;
 128
 129         if (clocks > 0x0F)
 130                 clocks = 0x0F;
 131
 132         return clocks;
 133 }
 134
 135 /*
 136  * compute the values for the clock registers for PIO
 137  * mode and pci_clk [MHz] speed
 138  *
 139  * NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used
 140  *       for mode 3 and 4 drives 8 and 16-bit timings are the same
 141  *
 142  */
 143 static void compute_clocks (u8 pio, pio_clocks_t *p_pclk)
 144 {
 145         int clk1, clk2;
 146         int bus_speed = system_bus_clock();     /* get speed of PCI bus */
 147
 148         /* we don't check against CY82C693's min and max speed,
 149          * so you can play with the idebus=xx parameter
 150          */
 151
 152         if (pio > CY82C693_MAX_PIO)
 153                 pio = CY82C693_MAX_PIO;
 154
 155         /* let's calc the address setup time clocks */
 156         p_pclk->address_time = (u8)calc_clk(ide_pio_timings[pio].setup_time, bus_speed);
 157
 158         /* let's calc the active and recovery time clocks */
 159         clk1 = calc_clk(ide_pio_timings[pio].active_time, bus_speed);
 160
 161         /* calc recovery timing */
 162         clk2 =  ide_pio_timings[pio].cycle_time -
 163                 ide_pio_timings[pio].active_time -
 164                 ide_pio_timings[pio].setup_time;
 165
 166         clk2 = calc_clk(clk2, bus_speed);
 167
 168         clk1 = (clk1<<4)|clk2;  /* combine active and recovery clocks */
 169
 170         /* note: we use the same values for 16bit IOR and IOW
 171          *      those are all the same, since I don't have other
 172          *      timings than those from ide-lib.c
 173          */
 174
 175         p_pclk->time_16r = (u8)clk1;
 176         p_pclk->time_16w = (u8)clk1;
 177
 178         /* what are good values for 8bit ?? */
 179         p_pclk->time_8 = (u8)clk1;
 180 }
 181
 182 /*
 183  * set DMA mode a specific channel for CY82C693
 184  */
 185
 186 static void cy82c693_dma_enable (ide_drive_t *drive, int mode, int single)
 187 {
 188         u8 index = 0, data = 0;
 189
 190         if (mode>2)     /* make sure we set a valid mode */
 191                 mode = 2;
 192
 193         if (mode > drive->id->tDMA)  /* to be absolutly sure we have a valid mode */
 194                 mode = drive->id->tDMA;
 195
 196         index = (HWIF(drive)->channel==0) ? CY82_INDEX_CHANNEL0 : CY82_INDEX_CHANNEL1;
 197
 198 #if CY82C693_DEBUG_LOGS
 199         /* for debug let's show the previous values */
 200
 201         HWIF(drive)->OUTB(index, CY82_INDEX_PORT);
 202         data = HWIF(drive)->INB(CY82_DATA_PORT);
 203
 204         printk (KERN_INFO "%s (ch=%d, dev=%d): DMA mode is %d (single=%d)\n",
 205                 drive->name, HWIF(drive)->channel, drive->select.b.unit,
 206                 (data&0x3), ((data>>2)&1));
 207 #endif /* CY82C693_DEBUG_LOGS */
 208
 209         data = (u8)mode|(u8)(single<<2);
 210
 211         HWIF(drive)->OUTB(index, CY82_INDEX_PORT);
 212         HWIF(drive)->OUTB(data, CY82_DATA_PORT);
 213
 214 #if CY82C693_DEBUG_INFO
 215         printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n",
 216                 drive->name, HWIF(drive)->channel, drive->select.b.unit,
 217                 mode, single);
 218 #endif /* CY82C693_DEBUG_INFO */
 219
 220         /*
 221          * note: below we set the value for Bus Master IDE TimeOut Register
 222          * I'm not absolutly sure what this does, but it solved my problem
 223          * with IDE DMA and sound, so I now can play sound and work with
 224          * my IDE driver at the same time :-)
 225          *
 226          * If you know the correct (best) value for this register please
 227          * let me know - ASK
 228          */
 229
 230         data = BUSMASTER_TIMEOUT;
 231         HWIF(drive)->OUTB(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
 232         HWIF(drive)->OUTB(data, CY82_DATA_PORT);
 233
 234 #if CY82C693_DEBUG_INFO
 235         printk (KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n",
 236                 drive->name, data);
 237 #endif /* CY82C693_DEBUG_INFO */
 238 }
 239
 240 /*
 241  * used to set DMA mode for CY82C693 (single and multi modes)
 242  */
 243 static int cy82c693_ide_dma_on (ide_drive_t *drive)
 244 {
 245         struct hd_driveid *id = drive->id;
 246
 247 #if CY82C693_DEBUG_INFO
 248         printk (KERN_INFO "dma_on: %s\n", drive->name);
 249 #endif /* CY82C693_DEBUG_INFO */
 250
 251         if (id != NULL) {
 252                 /* Enable DMA on any drive that has DMA
 253                  * (multi or single) enabled
 254                  */
 255                 if (id->field_valid & 2) {      /* regular DMA */
 256                         int mmode, smode;
 257
 258                         mmode = id->dma_mword & (id->dma_mword >> 8);
 259                         smode = id->dma_1word & (id->dma_1word >> 8);
 260
 261                         if (mmode != 0) {
 262                                 /* enable multi */
 263                                 cy82c693_dma_enable(drive, (mmode >> 1), 0);
 264                         } else if (smode != 0) {
 265                                 /* enable single */
 266                                 cy82c693_dma_enable(drive, (smode >> 1), 1);
 267                         }
 268                 }
 269         }
 270         return __ide_dma_on(drive);
 271 }
 272
 273 /*
 274  * tune ide drive - set PIO mode
 275  */
 276 static void cy82c693_tune_drive (ide_drive_t *drive, u8 pio)
 277 {
 278         ide_hwif_t *hwif = HWIF(drive);
 279         struct pci_dev *dev = hwif->pci_dev;
 280         pio_clocks_t pclk;
 281         unsigned int addrCtrl;
 282
 283         /* select primary or secondary channel */
 284         if (hwif->index > 0) {  /* drive is on the secondary channel */
 285                 dev = pci_find_slot(dev->bus->number, dev->devfn+1);
 286                 if (!dev) {
 287                         printk(KERN_ERR "%s: tune_drive: "
 288                                 "Cannot find secondary interface!\n",
 289                                 drive->name);
 290                         return;
 291                 }
 292         }
 293
 294 #if CY82C693_DEBUG_LOGS
 295         /* for debug let's show the register values */
 296
 297         if (drive->select.b.unit == 0) {
 298                 /*
 299                  * get master drive registers
 300                  * address setup control register
 301                  * is 32 bit !!!
 302                  */
 303                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 304                 addrCtrl &= 0x0F;
 305
 306                 /* now let's get the remaining registers */
 307                 pci_read_config_byte(dev, CY82_IDE_MASTER_IOR, &pclk.time_16r);
 308                 pci_read_config_byte(dev, CY82_IDE_MASTER_IOW, &pclk.time_16w);
 309                 pci_read_config_byte(dev, CY82_IDE_MASTER_8BIT, &pclk.time_8);
 310         } else {
 311                 /*
 312                  * set slave drive registers
 313                  * address setup control register
 314                  * is 32 bit !!!
 315                  */
 316                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 317
 318                 addrCtrl &= 0xF0;
 319                 addrCtrl >>= 4;
 320
 321                 /* now let's get the remaining registers */
 322                 pci_read_config_byte(dev, CY82_IDE_SLAVE_IOR, &pclk.time_16r);
 323                 pci_read_config_byte(dev, CY82_IDE_SLAVE_IOW, &pclk.time_16w);
 324                 pci_read_config_byte(dev, CY82_IDE_SLAVE_8BIT, &pclk.time_8);
 325         }
 326
 327         printk(KERN_INFO "%s (ch=%d, dev=%d): PIO timing is "
 328                 "(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
 329                 drive->name, hwif->channel, drive->select.b.unit,
 330                 addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
 331 #endif /* CY82C693_DEBUG_LOGS */
 332
 333         /* first let's calc the pio modes */
 334         pio = ide_get_best_pio_mode(drive, pio, CY82C693_MAX_PIO, NULL);
 335
 336 #if CY82C693_DEBUG_INFO
 337         printk (KERN_INFO "%s: Selected PIO mode %d\n", drive->name, pio);
 338 #endif /* CY82C693_DEBUG_INFO */
 339
 340         /* let's calc the values for this PIO mode */
 341         compute_clocks(pio, &pclk);
 342
 343         /* now let's write  the clocks registers */
 344         if (drive->select.b.unit == 0) {
 345                 /*
 346                  * set master drive
 347                  * address setup control register
 348                  * is 32 bit !!!
 349                  */
 350                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 351
 352                 addrCtrl &= (~0xF);
 353                 addrCtrl |= (unsigned int)pclk.address_time;
 354                 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
 355
 356                 /* now let's set the remaining registers */
 357                 pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r);
 358                 pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w);
 359                 pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8);
 360
 361                 addrCtrl &= 0xF;
 362         } else {
 363                 /*
 364                  * set slave drive
 365                  * address setup control register
 366                  * is 32 bit !!!
 367                  */
 368                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 369
 370                 addrCtrl &= (~0xF0);
 371                 addrCtrl |= ((unsigned int)pclk.address_time<<4);
 372                 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
 373
 374                 /* now let's set the remaining registers */
 375                 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r);
 376                 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w);
 377                 pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8);
 378
 379                 addrCtrl >>= 4;
 380                 addrCtrl &= 0xF;
 381         }
 382
 383 #if CY82C693_DEBUG_INFO
 384         printk(KERN_INFO "%s (ch=%d, dev=%d): set PIO timing to "
 385                 "(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
 386                 drive->name, hwif->channel, drive->select.b.unit,
 387                 addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
 388 #endif /* CY82C693_DEBUG_INFO */
 389 }
 390
 391 /*
 392  * this function is called during init and is used to setup the cy82c693 chip
 393  */
 394 static unsigned int __init init_chipset_cy82c693(struct pci_dev *dev, const char *name)
 395 {
 396         if (PCI_FUNC(dev->devfn) != 1)
 397                 return 0;
 398
 399 #ifdef CY82C693_SETDMA_CLOCK
 400         u8 data = 0;
 401 #endif /* CY82C693_SETDMA_CLOCK */
 402
 403         /* write info about this verion of the driver */
 404         printk(KERN_INFO CY82_VERSION "\n");
 405
 406 #ifdef CY82C693_SETDMA_CLOCK
 407        /* okay let's set the DMA clock speed */
 408
 409         outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
 410         data = inb(CY82_DATA_PORT);
 411
 412 #if CY82C693_DEBUG_INFO
 413         printk(KERN_INFO "%s: Peripheral Configuration Register: 0x%X\n",
 414                 name, data);
 415 #endif /* CY82C693_DEBUG_INFO */
 416
 417         /*
 418          * for some reason sometimes the DMA controller
 419          * speed is set to ATCLK/2 ???? - we fix this here
 420          *
 421          * note: i don't know what causes this strange behaviour,
 422          *       but even changing the dma speed doesn't solve it :-(
 423          *       the ide performance is still only half the normal speed
 424          *
 425          *       if anybody knows what goes wrong with my machine, please
 426          *       let me know - ASK
 427          */
 428
 429         data |= 0x03;
 430
 431         outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
 432         outb(data, CY82_DATA_PORT);
 433
 434 #if CY82C693_DEBUG_INFO
 435         printk (KERN_INFO "%s: New Peripheral Configuration Register: 0x%X\n",
 436                 name, data);
 437 #endif /* CY82C693_DEBUG_INFO */
 438
 439 #endif /* CY82C693_SETDMA_CLOCK */
 440         return 0;
 441 }
 442
 443 /*
 444  * the init function - called for each ide channel once
 445  */
 446 static void __init init_hwif_cy82c693(ide_hwif_t *hwif)
 447 {
 448         hwif->autodma = 0;
 449
 450         hwif->chipset = ide_cy82c693;
 451         hwif->tuneproc = &cy82c693_tune_drive;
 452
 453         if (!hwif->dma_base) {
 454                 hwif->drives[0].autotune = 1;
 455                 hwif->drives[1].autotune = 1;
 456                 return;
 457         }
 458
 459         hwif->atapi_dma = 1;
 460         hwif->mwdma_mask = 0x04;
 461         hwif->swdma_mask = 0x04;
 462
 463         hwif->ide_dma_on = &cy82c693_ide_dma_on;
 464         if (!noautodma)
 465                 hwif->autodma = 1;
 466         hwif->drives[0].autodma = hwif->autodma;
 467         hwif->drives[1].autodma = hwif->autodma;
 468 }
 469
 470 static __initdata ide_hwif_t *primary;
 471
 472 void __init init_iops_cy82c693(ide_hwif_t *hwif)
 473 {
 474         if (PCI_FUNC(hwif->pci_dev->devfn) == 1)
 475                 primary = hwif;
 476         else {
 477                 hwif->mate = primary;
 478                 hwif->channel = 1;
 479         }
 480 }
 481
 482 static ide_pci_device_t cy82c693_chipsets[] __devinitdata = {
 483         {       /* 0 */
 484                 .name           = "CY82C693",
 485                 .init_chipset   = init_chipset_cy82c693,
 486                 .init_iops      = init_iops_cy82c693,
 487                 .init_hwif      = init_hwif_cy82c693,
 488                 .channels       = 1,
 489                 .autodma        = AUTODMA,
 490                 .bootable       = ON_BOARD,
 491         }
 492 };
 493
 494 static int __devinit cy82c693_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 495 {
 496         ide_pci_device_t *d = &cy82c693_chipsets[id->driver_data];
 497         struct pci_dev *dev2;
 498         int ret = -ENODEV;
 499
 500         /* CY82C693 is more than only a IDE controller.
 501            Function 1 is primary IDE channel, function 2 - secondary. */
 502         if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
 503             PCI_FUNC(dev->devfn) == 1) {
 504                 dev2 = pci_find_slot(dev->bus->number, dev->devfn + 1);
 505                 ret = ide_setup_pci_devices(dev, dev2, d);
 506         }
 507         return ret;
 508 }
 509
 510 static struct pci_device_id cy82c693_pci_tbl[] = {
 511         { PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 512         { 0, },
 513 };
 514 MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl);
 515
 516 static struct pci_driver driver = {
 517         .name           = "Cypress_IDE",
 518         .id_table       = cy82c693_pci_tbl,
 519         .probe          = cy82c693_init_one,
 520 };
 521
 522 static int cy82c693_ide_init(void)
 523 {
 524         return ide_pci_register_driver(&driver);
 525 }
 526
 527 module_init(cy82c693_ide_init);
 528
 529 MODULE_AUTHOR("Andreas Krebs, Andre Hedrick");
 530 MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE");
 531 MODULE_LICENSE("GPL");