drivers/ide/pci/it8172.c

   1 /*
   2  *
   3  * BRIEF MODULE DESCRIPTION
   4  *      IT8172 IDE controller support
   5  *
   6  * Copyright 2000 MontaVista Software Inc.
   7  * Author: MontaVista Software, Inc.
   8  *              stevel@mvista.com or source@mvista.com
   9  *
  10  *  This program is free software; you can redistribute  it and/or modify it
  11  *  under  the terms of  the GNU General  Public License as published by the
  12  *  Free Software Foundation;  either version 2 of the  License, or (at your
  13  *  option) any later version.
  14  *
  15  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  16  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  17  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  18  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  19  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  21  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  22  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  23  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  24  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  *  You should have received a copy of the  GNU General Public License along
  27  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  28  *  675 Mass Ave, Cambridge, MA 02139, USA.
  29  */
  30
  31 #include <linux/config.h>
  32 #include <linux/module.h>
  33 #include <linux/types.h>
  34 #include <linux/kernel.h>
  35 #include <linux/ioport.h>
  36 #include <linux/pci.h>
  37 #include <linux/hdreg.h>
  38 #include <linux/ide.h>
  39 #include <linux/delay.h>
  40 #include <linux/init.h>
  41
  42 #include <asm/io.h>
  43 #include <asm/it8172/it8172_int.h>
  44
  45 /*
  46  * Prototypes
  47  */
  48 static u8 it8172_ratemask (ide_drive_t *drive)
  49 {
  50         return 1;
  51 }
  52
  53 static void it8172_tune_drive (ide_drive_t *drive, u8 pio)
  54 {
  55         ide_hwif_t *hwif        = HWIF(drive);
  56         struct pci_dev *dev     = hwif->pci_dev;
  57         int is_slave            = (&hwif->drives[1] == drive);
  58         unsigned long flags;
  59         u16 drive_enables;
  60         u32 drive_timing;
  61
  62         pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
  63         spin_lock_irqsave(&ide_lock, flags);
  64         pci_read_config_word(dev, 0x40, &drive_enables);
  65         pci_read_config_dword(dev, 0x44, &drive_timing);
  66
  67         /*
  68          * FIX! The DIOR/DIOW pulse width and recovery times in port 0x44
  69          * are being left at the default values of 8 PCI clocks (242 nsec
  70          * for a 33 MHz clock). These can be safely shortened at higher
  71          * PIO modes. The DIOR/DIOW pulse width and recovery times only
  72          * apply to PIO modes, not to the DMA modes.
  73          */
  74
  75         /*
  76          * Enable port 0x44. The IT8172G spec is confused; it calls
  77          * this register the "Slave IDE Timing Register", but in fact,
  78          * it controls timing for both master and slave drives.
  79          */
  80         drive_enables |= 0x4000;
  81
  82         if (is_slave) {
  83                 drive_enables &= 0xc006;
  84                 if (pio > 1)
  85                         /* enable prefetch and IORDY sample-point */
  86                         drive_enables |= 0x0060;
  87         } else {
  88                 drive_enables &= 0xc060;
  89                 if (pio > 1)
  90                         /* enable prefetch and IORDY sample-point */
  91                         drive_enables |= 0x0006;
  92         }
  93
  94         pci_write_config_word(dev, 0x40, drive_enables);
  95         spin_unlock_irqrestore(&ide_lock, flags);
  96 }
  97
  98 static u8 it8172_dma_2_pio (u8 xfer_rate)
  99 {
 100         switch(xfer_rate) {
 101                 case XFER_UDMA_5:
 102                 case XFER_UDMA_4:
 103                 case XFER_UDMA_3:
 104                 case XFER_UDMA_2:
 105                 case XFER_UDMA_1:
 106                 case XFER_UDMA_0:
 107                 case XFER_MW_DMA_2:
 108                 case XFER_PIO_4:
 109                         return 4;
 110                 case XFER_MW_DMA_1:
 111                 case XFER_PIO_3:
 112                         return 3;
 113                 case XFER_SW_DMA_2:
 114                 case XFER_PIO_2:
 115                         return 2;
 116                 case XFER_MW_DMA_0:
 117                 case XFER_SW_DMA_1:
 118                 case XFER_SW_DMA_0:
 119                 case XFER_PIO_1:
 120                 case XFER_PIO_0:
 121                 case XFER_PIO_SLOW:
 122                 default:
 123                         return 0;
 124         }
 125 }
 126
 127 static int it8172_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 128 {
 129         ide_hwif_t *hwif        = HWIF(drive);
 130         struct pci_dev *dev     = hwif->pci_dev;
 131         u8 speed        = ide_rate_filter(it8172_ratemask(drive), xferspeed);
 132         int a_speed             = 3 << (drive->dn * 4);
 133         int u_flag              = 1 << drive->dn;
 134         int u_speed             = 0;
 135         u8 reg48, reg4a;
 136
 137         pci_read_config_byte(dev, 0x48, &reg48);
 138         pci_read_config_byte(dev, 0x4a, &reg4a);
 139
 140     /*
 141      * Setting the DMA cycle time to 2 or 3 PCI clocks (60 and 91 nsec
 142      * at 33 MHz PCI clock) seems to cause BadCRC errors during DMA
 143      * transfers on some drives, even though both numbers meet the minimum
 144      * ATAPI-4 spec of 73 and 54 nsec for UDMA 1 and 2 respectively.
 145      * So the faster times are just commented out here. The good news is
 146      * that the slower cycle time has very little affect on transfer
 147      * performance.
 148      */
 149
 150         switch(speed) {
 151                 case XFER_UDMA_4:
 152                 case XFER_UDMA_2:       //u_speed = 2 << (drive->dn * 4); break;
 153                 case XFER_UDMA_5:
 154                 case XFER_UDMA_3:
 155                 case XFER_UDMA_1:       //u_speed = 1 << (drive->dn * 4); break;
 156                 case XFER_UDMA_0:       u_speed = 0 << (drive->dn * 4); break;
 157                 case XFER_MW_DMA_2:
 158                 case XFER_MW_DMA_1:
 159                 case XFER_MW_DMA_0:
 160                 case XFER_SW_DMA_2:     break;
 161                 case XFER_PIO_4:
 162                 case XFER_PIO_3:
 163                 case XFER_PIO_2:
 164                 case XFER_PIO_0:        break;
 165                 default:                return -1;
 166         }
 167
 168         if (speed >= XFER_UDMA_0) {
 169                 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
 170                 reg4a &= ~a_speed;
 171                 pci_write_config_byte(dev, 0x4a, reg4a | u_speed);
 172         } else {
 173                 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
 174                 pci_write_config_byte(dev, 0x4a, reg4a & ~a_speed);
 175         }
 176
 177         it8172_tune_drive(drive, it8172_dma_2_pio(speed));
 178         return (ide_config_drive_speed(drive, speed));
 179 }
 180
 181 static int it8172_config_chipset_for_dma (ide_drive_t *drive)
 182 {
 183         u8 speed = ide_dma_speed(drive, it8172_ratemask(drive));
 184
 185         if (!(speed)) {
 186                 u8 tspeed = ide_get_best_pio_mode(drive, 255, 4, NULL);
 187                 speed = it8172_dma_2_pio(XFER_PIO_0 + tspeed);
 188         }
 189
 190         (void) it8172_tune_chipset(drive, speed);
 191         return ide_dma_enable(drive);
 192 }
 193
 194 static int it8172_config_drive_xfer_rate (ide_drive_t *drive)
 195 {
 196         ide_hwif_t *hwif        = HWIF(drive);
 197         struct hd_driveid *id   = drive->id;
 198
 199         drive->init_speed = 0;
 200
 201         if (id && (id->capability & 1) && drive->autodma) {
 202
 203                 if (ide_use_dma(drive)) {
 204                         if (it8172_config_chipset_for_dma(drive))
 205                                 return hwif->ide_dma_on(drive);
 206                 }
 207
 208                 goto fast_ata_pio;
 209
 210         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 211 fast_ata_pio:
 212                 it8172_tune_drive(drive, 5);
 213                 return hwif->ide_dma_off_quietly(drive);
 214         }
 215         /* IORDY not supported */
 216         return 0;
 217 }
 218
 219 static unsigned int __init init_chipset_it8172 (struct pci_dev *dev, const char *name)
 220 {
 221         unsigned char progif;
 222
 223         /*
 224          * Place both IDE interfaces into PCI "native" mode
 225          */
 226         pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
 227         pci_write_config_byte(dev, PCI_CLASS_PROG, progif | 0x05);
 228
 229         return IT8172_IDE_IRQ;
 230 }
 231
 232
 233 static void __init init_hwif_it8172 (ide_hwif_t *hwif)
 234 {
 235         struct pci_dev* dev = hwif->pci_dev;
 236         unsigned long cmdBase, ctrlBase;
 237
 238         hwif->autodma = 0;
 239         hwif->tuneproc = &it8172_tune_drive;
 240         hwif->speedproc = &it8172_tune_chipset;
 241
 242         cmdBase = dev->resource[0].start;
 243         ctrlBase = dev->resource[1].start;
 244
 245         ide_init_hwif_ports(&hwif->hw, cmdBase, ctrlBase | 2, NULL);
 246         memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
 247         hwif->noprobe = 0;
 248
 249         if (!hwif->dma_base) {
 250                 hwif->drives[0].autotune = 1;
 251                 hwif->drives[1].autotune = 1;
 252                 return;
 253         }
 254
 255         hwif->atapi_dma = 1;
 256         hwif->ultra_mask = 0x07;
 257         hwif->mwdma_mask = 0x06;
 258         hwif->swdma_mask = 0x04;
 259
 260         hwif->ide_dma_check = &it8172_config_drive_xfer_rate;
 261         if (!noautodma)
 262                 hwif->autodma = 1;
 263         hwif->drives[0].autodma = hwif->autodma;
 264         hwif->drives[1].autodma = hwif->autodma;
 265 }
 266
 267 static ide_pci_device_t it8172_chipsets[] __devinitdata = {
 268         {       /* 0 */
 269                 .name           = "IT8172G",
 270                 .init_chipset   = init_chipset_it8172,
 271                 .init_hwif      = init_hwif_it8172,
 272                 .channels       = 2,
 273                 .autodma        = AUTODMA,
 274                 .enablebits     = {{0x00,0x00,0x00}, {0x40,0x00,0x01}},
 275                 .bootable       = ON_BOARD,
 276         }
 277 };
 278
 279 static int __devinit it8172_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 280 {
 281         if ((!(PCI_FUNC(dev->devfn) & 1) ||
 282             (!((dev->class >> 8) == PCI_CLASS_STORAGE_IDE))))
 283                 return -ENODEV; /* IT8172 is more than an IDE controller */
 284         return ide_setup_pci_device(dev, &it8172_chipsets[id->driver_data]);
 285 }
 286
 287 static struct pci_device_id it8172_pci_tbl[] = {
 288         { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_IT8172G, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 289         { 0, },
 290 };
 291 MODULE_DEVICE_TABLE(pci, it8172_pci_tbl);
 292
 293 static struct pci_driver driver = {
 294         .name           = "IT8172_IDE",
 295         .id_table       = it8172_pci_tbl,
 296         .probe          = it8172_init_one,
 297 };
 298
 299 static int it8172_ide_init(void)
 300 {
 301         return ide_pci_register_driver(&driver);
 302 }
 303
 304 module_init(it8172_ide_init);
 305
 306 MODULE_AUTHOR("SteveL@mvista.com");
 307 MODULE_DESCRIPTION("PCI driver module for ITE 8172 IDE");
 308 MODULE_LICENSE("GPL");