drivers/ide/pci/piix.c

   1 /*
   2  *  linux/drivers/ide/pci/piix.c        Version 0.44    March 20, 2003
   3  *
   4  *  Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
   5  *  Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
   6  *  Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
   7  *
   8  *  May be copied or modified under the terms of the GNU General Public License
   9  *
  10  *  PIO mode setting function for Intel chipsets.
  11  *  For use instead of BIOS settings.
  12  *
  13  * 40-41
  14  * 42-43
  15  *
  16  *                 41
  17  *                 43
  18  *
  19  * | PIO 0       | c0 | 80 | 0 |        piix_tune_drive(drive, 0);
  20  * | PIO 2 | SW2 | d0 | 90 | 4 |        piix_tune_drive(drive, 2);
  21  * | PIO 3 | MW1 | e1 | a1 | 9 |        piix_tune_drive(drive, 3);
  22  * | PIO 4 | MW2 | e3 | a3 | b |        piix_tune_drive(drive, 4);
  23  *
  24  * sitre = word40 & 0x4000; primary
  25  * sitre = word42 & 0x4000; secondary
  26  *
  27  * 44 8421|8421    hdd|hdb
  28  *
  29  * 48 8421         hdd|hdc|hdb|hda udma enabled
  30  *
  31  *    0001         hda
  32  *    0010         hdb
  33  *    0100         hdc
  34  *    1000         hdd
  35  *
  36  * 4a 84|21        hdb|hda
  37  * 4b 84|21        hdd|hdc
  38  *
  39  *    ata-33/82371AB
  40  *    ata-33/82371EB
  41  *    ata-33/82801AB            ata-66/82801AA
  42  *    00|00 udma 0              00|00 reserved
  43  *    01|01 udma 1              01|01 udma 3
  44  *    10|10 udma 2              10|10 udma 4
  45  *    11|11 reserved            11|11 reserved
  46  *
  47  * 54 8421|8421    ata66 drive|ata66 enable
  48  *
  49  * pci_read_config_word(HWIF(drive)->pci_dev, 0x40, &reg40);
  50  * pci_read_config_word(HWIF(drive)->pci_dev, 0x42, &reg42);
  51  * pci_read_config_word(HWIF(drive)->pci_dev, 0x44, &reg44);
  52  * pci_read_config_byte(HWIF(drive)->pci_dev, 0x48, &reg48);
  53  * pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, &reg4a);
  54  * pci_read_config_byte(HWIF(drive)->pci_dev, 0x54, &reg54);
  55  *
  56  * Documentation
  57  *      Publically available from Intel web site. Errata documentation
  58  * is also publically available. As an aide to anyone hacking on this
  59  * driver the list of errata that are relevant is below.going back to
  60  * PIIX4. Older device documentation is now a bit tricky to find.
  61  *
  62  * Errata of note:
  63  *
  64  * Unfixable
  65  *      PIIX4    errata #9      - Only on ultra obscure hw
  66  *      ICH3     errata #13     - Not observed to affect real hw
  67  *                                by Intel
  68  *
  69  * Things we must deal with
  70  *      PIIX4   errata #10      - BM IDE hang with non UDMA
  71  *                                (must stop/start dma to recover)
  72  *      440MX   errata #15      - As PIIX4 errata #10
  73  *      PIIX4   errata #15      - Must not read control registers
  74  *                                during a PIO transfer
  75  *      440MX   errata #13      - As PIIX4 errata #15
  76  *      ICH2    errata #21      - DMA mode 0 doesn't work right
  77  *      ICH0/1  errata #55      - As ICH2 errata #21
  78  *      ICH2    spec c #9       - Extra operations needed to handle
  79  *                                drive hotswap [NOT YET SUPPORTED]
  80  *      ICH2    spec c #20      - IDE PRD must not cross a 64K boundary
  81  *                                and must be dword aligned
  82  *      ICH2    spec c #24      - UDMA mode 4,5 t85/86 should be 6ns not 3.3
  83  *
  84  * Should have been BIOS fixed:
  85  *      450NX:  errata #19      - DMA hangs on old 450NX
  86  *      450NX:  errata #20      - DMA hangs on old 450NX
  87  *      450NX:  errata #25      - Corruption with DMA on old 450NX
  88  *      ICH3    errata #15      - IDE deadlock under high load
  89  *                                (BIOS must set dev 31 fn 0 bit 23)
  90  *      ICH3    errata #18      - Don't use native mode
  91  */
  92
  93 #include <linux/config.h>
  94 #include <linux/types.h>
  95 #include <linux/module.h>
  96 #include <linux/kernel.h>
  97 #include <linux/ioport.h>
  98 #include <linux/pci.h>
  99 #include <linux/hdreg.h>
 100 #include <linux/ide.h>
 101 #include <linux/delay.h>
 102 #include <linux/init.h>
 103
 104 #include <asm/io.h>
 105
 106 static int no_piix_dma;
 107
 108 /**
 109  *      piix_ratemask           -       compute rate mask for PIIX IDE
 110  *      @drive: IDE drive to compute for
 111  *
 112  *      Returns the available modes for the PIIX IDE controller.
 113  */
 114
 115 static u8 piix_ratemask (ide_drive_t *drive)
 116 {
 117         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 118         u8 mode;
 119
 120         switch(dev->device) {
 121                 case PCI_DEVICE_ID_INTEL_82801EB_1:
 122                         mode = 3;
 123                         break;
 124                 /* UDMA 100 capable */
 125                 case PCI_DEVICE_ID_INTEL_82801BA_8:
 126                 case PCI_DEVICE_ID_INTEL_82801BA_9:
 127                 case PCI_DEVICE_ID_INTEL_82801CA_10:
 128                 case PCI_DEVICE_ID_INTEL_82801CA_11:
 129                 case PCI_DEVICE_ID_INTEL_82801E_11:
 130                 case PCI_DEVICE_ID_INTEL_82801DB_1:
 131                 case PCI_DEVICE_ID_INTEL_82801DB_10:
 132                 case PCI_DEVICE_ID_INTEL_82801DB_11:
 133                 case PCI_DEVICE_ID_INTEL_82801EB_11:
 134                 case PCI_DEVICE_ID_INTEL_ESB_2:
 135                 case PCI_DEVICE_ID_INTEL_ICH6_19:
 136                 case PCI_DEVICE_ID_INTEL_ICH7_21:
 137                 case PCI_DEVICE_ID_INTEL_ESB2_18:
 138                         mode = 3;
 139                         break;
 140                 /* UDMA 66 capable */
 141                 case PCI_DEVICE_ID_INTEL_82801AA_1:
 142                 case PCI_DEVICE_ID_INTEL_82372FB_1:
 143                         mode = 2;
 144                         break;
 145                 /* UDMA 33 capable */
 146                 case PCI_DEVICE_ID_INTEL_82371AB:
 147                 case PCI_DEVICE_ID_INTEL_82443MX_1:
 148                 case PCI_DEVICE_ID_INTEL_82451NX:
 149                 case PCI_DEVICE_ID_INTEL_82801AB_1:
 150                         return 1;
 151                 /* Non UDMA capable (MWDMA2) */
 152                 case PCI_DEVICE_ID_INTEL_82371SB_1:
 153                 case PCI_DEVICE_ID_INTEL_82371FB_1:
 154                 case PCI_DEVICE_ID_INTEL_82371FB_0:
 155                 case PCI_DEVICE_ID_INTEL_82371MX:
 156                 default:
 157                         return 0;
 158         }
 159
 160         /*
 161          *      If we are UDMA66 capable fall back to UDMA33
 162          *      if the drive cannot see an 80pin cable.
 163          */
 164         if (!eighty_ninty_three(drive))
 165                 mode = min(mode, (u8)1);
 166         return mode;
 167 }
 168
 169 /**
 170  *      piix_dma_2_pio          -       return the PIO mode matching DMA
 171  *      @xfer_rate: transfer speed
 172  *
 173  *      Returns the nearest equivalent PIO timing for the PIO or DMA
 174  *      mode requested by the controller.
 175  */
 176
 177 static u8 piix_dma_2_pio (u8 xfer_rate) {
 178         switch(xfer_rate) {
 179                 case XFER_UDMA_6:
 180                 case XFER_UDMA_5:
 181                 case XFER_UDMA_4:
 182                 case XFER_UDMA_3:
 183                 case XFER_UDMA_2:
 184                 case XFER_UDMA_1:
 185                 case XFER_UDMA_0:
 186                 case XFER_MW_DMA_2:
 187                 case XFER_PIO_4:
 188                         return 4;
 189                 case XFER_MW_DMA_1:
 190                 case XFER_PIO_3:
 191                         return 3;
 192                 case XFER_SW_DMA_2:
 193                 case XFER_PIO_2:
 194                         return 2;
 195                 case XFER_MW_DMA_0:
 196                 case XFER_SW_DMA_1:
 197                 case XFER_SW_DMA_0:
 198                 case XFER_PIO_1:
 199                 case XFER_PIO_0:
 200                 case XFER_PIO_SLOW:
 201                 default:
 202                         return 0;
 203         }
 204 }
 205
 206 /**
 207  *      piix_tune_drive         -       tune a drive attached to a PIIX
 208  *      @drive: drive to tune
 209  *      @pio: desired PIO mode
 210  *
 211  *      Set the interface PIO mode based upon  the settings done by AMI BIOS
 212  *      (might be useful if drive is not registered in CMOS for any reason).
 213  */
 214 static void piix_tune_drive (ide_drive_t *drive, u8 pio)
 215 {
 216         ide_hwif_t *hwif        = HWIF(drive);
 217         struct pci_dev *dev     = hwif->pci_dev;
 218         int is_slave            = (&hwif->drives[1] == drive);
 219         int master_port         = hwif->channel ? 0x42 : 0x40;
 220         int slave_port          = 0x44;
 221         unsigned long flags;
 222         u16 master_data;
 223         u8 slave_data;
 224                                  /* ISP  RTC */
 225         u8 timings[][2] = { { 0, 0 },
 226                             { 0, 0 },
 227                             { 1, 0 },
 228                             { 2, 1 },
 229                             { 2, 3 }, };
 230
 231         pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
 232         spin_lock_irqsave(&ide_lock, flags);
 233         pci_read_config_word(dev, master_port, &master_data);
 234         if (is_slave) {
 235                 master_data = master_data | 0x4000;
 236                 if (pio > 1)
 237                         /* enable PPE, IE and TIME */
 238                         master_data = master_data | 0x0070;
 239                 pci_read_config_byte(dev, slave_port, &slave_data);
 240                 slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0);
 241                 slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0));
 242         } else {
 243                 master_data = master_data & 0xccf8;
 244                 if (pio > 1)
 245                         /* enable PPE, IE and TIME */
 246                         master_data = master_data | 0x0007;
 247                 master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
 248         }
 249         pci_write_config_word(dev, master_port, master_data);
 250         if (is_slave)
 251                 pci_write_config_byte(dev, slave_port, slave_data);
 252         spin_unlock_irqrestore(&ide_lock, flags);
 253 }
 254
 255 /**
 256  *      piix_tune_chipset       -       tune a PIIX interface
 257  *      @drive: IDE drive to tune
 258  *      @xferspeed: speed to configure
 259  *
 260  *      Set a PIIX interface channel to the desired speeds. This involves
 261  *      requires the right timing data into the PIIX configuration space
 262  *      then setting the drive parameters appropriately
 263  */
 264
 265 static int piix_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 266 {
 267         ide_hwif_t *hwif        = HWIF(drive);
 268         struct pci_dev *dev     = hwif->pci_dev;
 269         u8 maslave              = hwif->channel ? 0x42 : 0x40;
 270         u8 speed                = ide_rate_filter(piix_ratemask(drive), xferspeed);
 271         int a_speed             = 3 << (drive->dn * 4);
 272         int u_flag              = 1 << drive->dn;
 273         int v_flag              = 0x01 << drive->dn;
 274         int w_flag              = 0x10 << drive->dn;
 275         int u_speed             = 0;
 276         int                     sitre;
 277         u16                     reg4042, reg4a;
 278         u8                      reg48, reg54, reg55;
 279
 280         pci_read_config_word(dev, maslave, &reg4042);
 281         sitre = (reg4042 & 0x4000) ? 1 : 0;
 282         pci_read_config_byte(dev, 0x48, &reg48);
 283         pci_read_config_word(dev, 0x4a, &reg4a);
 284         pci_read_config_byte(dev, 0x54, &reg54);
 285         pci_read_config_byte(dev, 0x55, &reg55);
 286
 287         switch(speed) {
 288                 case XFER_UDMA_4:
 289                 case XFER_UDMA_2:       u_speed = 2 << (drive->dn * 4); break;
 290                 case XFER_UDMA_5:
 291                 case XFER_UDMA_3:
 292                 case XFER_UDMA_1:       u_speed = 1 << (drive->dn * 4); break;
 293                 case XFER_UDMA_0:       u_speed = 0 << (drive->dn * 4); break;
 294                 case XFER_MW_DMA_2:
 295                 case XFER_MW_DMA_1:
 296                 case XFER_SW_DMA_2:     break;
 297                 case XFER_PIO_4:
 298                 case XFER_PIO_3:
 299                 case XFER_PIO_2:
 300                 case XFER_PIO_0:        break;
 301                 default:                return -1;
 302         }
 303
 304         if (speed >= XFER_UDMA_0) {
 305                 if (!(reg48 & u_flag))
 306                         pci_write_config_byte(dev, 0x48, reg48 | u_flag);
 307                 if (speed == XFER_UDMA_5) {
 308                         pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
 309                 } else {
 310                         pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
 311                 }
 312                 if ((reg4a & a_speed) != u_speed)
 313                         pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
 314                 if (speed > XFER_UDMA_2) {
 315                         if (!(reg54 & v_flag))
 316                                 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
 317                 } else
 318                         pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
 319         } else {
 320                 if (reg48 & u_flag)
 321                         pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
 322                 if (reg4a & a_speed)
 323                         pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
 324                 if (reg54 & v_flag)
 325                         pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
 326                 if (reg55 & w_flag)
 327                         pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
 328         }
 329
 330         piix_tune_drive(drive, piix_dma_2_pio(speed));
 331         return (ide_config_drive_speed(drive, speed));
 332 }
 333
 334 /**
 335  *      piix_faulty_dma0                -       check for DMA0 errata
 336  *      @hwif: IDE interface to check
 337  *
 338  *      If an ICH/ICH0/ICH2 interface is is operating in multi-word
 339  *      DMA mode with 600nS cycle time the IDE PIO prefetch buffer will
 340  *      inadvertently provide an extra piece of secondary data to the primary
 341  *      device resulting in data corruption.
 342  *
 343  *      With such a device this test function returns true. This allows
 344  *      our tuning code to follow Intel recommendations and use PIO on
 345  *      such devices.
 346  */
 347
 348 static int piix_faulty_dma0(ide_hwif_t *hwif)
 349 {
 350         switch(hwif->pci_dev->device)
 351         {
 352                 case PCI_DEVICE_ID_INTEL_82801AA_1:     /* ICH */
 353                 case PCI_DEVICE_ID_INTEL_82801AB_1:     /* ICH0 */
 354                 case PCI_DEVICE_ID_INTEL_82801BA_8:     /* ICH2 */
 355                 case PCI_DEVICE_ID_INTEL_82801BA_9:     /* ICH2 */
 356                         return 1;
 357         }
 358         return 0;
 359 }
 360
 361 /**
 362  *      piix_config_drive_for_dma       -       configure drive for DMA
 363  *      @drive: IDE drive to configure
 364  *
 365  *      Set up a PIIX interface channel for the best available speed.
 366  *      We prefer UDMA if it is available and then MWDMA. If DMA is
 367  *      not available we switch to PIO and return 0.
 368  */
 369
 370 static int piix_config_drive_for_dma (ide_drive_t *drive)
 371 {
 372         u8 speed = ide_dma_speed(drive, piix_ratemask(drive));
 373
 374         /* Some ICH devices cannot support DMA mode 0 */
 375         if(speed == XFER_MW_DMA_0 && piix_faulty_dma0(HWIF(drive)))
 376                 speed = 0;
 377
 378         /* If no DMA speed was available or the chipset has DMA bugs
 379            then disable DMA and use PIO */
 380
 381         if (!speed || no_piix_dma) {
 382                 u8 tspeed = ide_get_best_pio_mode(drive, 255, 5, NULL);
 383                 speed = piix_dma_2_pio(XFER_PIO_0 + tspeed);
 384         }
 385
 386         (void) piix_tune_chipset(drive, speed);
 387         return ide_dma_enable(drive);
 388 }
 389
 390 /**
 391  *      piix_config_drive_xfer_rate     -       set up an IDE device
 392  *      @drive: IDE drive to configure
 393  *
 394  *      Set up the PIIX interface for the best available speed on this
 395  *      interface, preferring DMA to PIO.
 396  */
 397
 398 static int piix_config_drive_xfer_rate (ide_drive_t *drive)
 399 {
 400         ide_hwif_t *hwif        = HWIF(drive);
 401         struct hd_driveid *id   = drive->id;
 402
 403         drive->init_speed = 0;
 404
 405         if ((id->capability & 1) && drive->autodma) {
 406
 407                 if (ide_use_dma(drive)) {
 408                         if (piix_config_drive_for_dma(drive))
 409                                 return hwif->ide_dma_on(drive);
 410                 }
 411
 412                 goto fast_ata_pio;
 413
 414         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 415 fast_ata_pio:
 416                 /* Find best PIO mode. */
 417                 hwif->tuneproc(drive, 255);
 418                 return hwif->ide_dma_off_quietly(drive);
 419         }
 420         /* IORDY not supported */
 421         return 0;
 422 }
 423
 424 /**
 425  *      init_chipset_piix       -       set up the PIIX chipset
 426  *      @dev: PCI device to set up
 427  *      @name: Name of the device
 428  *
 429  *      Initialize the PCI device as required. For the PIIX this turns
 430  *      out to be nice and simple
 431  */
 432
 433 static unsigned int __devinit init_chipset_piix (struct pci_dev *dev, const char *name)
 434 {
 435         switch(dev->device) {
 436                 case PCI_DEVICE_ID_INTEL_82801EB_1:
 437                 case PCI_DEVICE_ID_INTEL_82801AA_1:
 438                 case PCI_DEVICE_ID_INTEL_82801AB_1:
 439                 case PCI_DEVICE_ID_INTEL_82801BA_8:
 440                 case PCI_DEVICE_ID_INTEL_82801BA_9:
 441                 case PCI_DEVICE_ID_INTEL_82801CA_10:
 442                 case PCI_DEVICE_ID_INTEL_82801CA_11:
 443                 case PCI_DEVICE_ID_INTEL_82801DB_1:
 444                 case PCI_DEVICE_ID_INTEL_82801DB_10:
 445                 case PCI_DEVICE_ID_INTEL_82801DB_11:
 446                 case PCI_DEVICE_ID_INTEL_82801EB_11:
 447                 case PCI_DEVICE_ID_INTEL_82801E_11:
 448                 case PCI_DEVICE_ID_INTEL_ESB_2:
 449                 case PCI_DEVICE_ID_INTEL_ICH6_19:
 450                 case PCI_DEVICE_ID_INTEL_ICH7_21:
 451                 case PCI_DEVICE_ID_INTEL_ESB2_18:
 452                 {
 453                         unsigned int extra = 0;
 454                         pci_read_config_dword(dev, 0x54, &extra);
 455                         pci_write_config_dword(dev, 0x54, extra|0x400);
 456                 }
 457                 default:
 458                         break;
 459         }
 460
 461         return 0;
 462 }
 463
 464 /**
 465  *      init_hwif_piix          -       fill in the hwif for the PIIX
 466  *      @hwif: IDE interface
 467  *
 468  *      Set up the ide_hwif_t for the PIIX interface according to the
 469  *      capabilities of the hardware.
 470  */
 471
 472 static void __devinit init_hwif_piix(ide_hwif_t *hwif)
 473 {
 474         u8 reg54h = 0, reg55h = 0, ata66 = 0;
 475         u8 mask = hwif->channel ? 0xc0 : 0x30;
 476
 477 #ifndef CONFIG_IA64
 478         if (!hwif->irq)
 479                 hwif->irq = hwif->channel ? 15 : 14;
 480 #endif /* CONFIG_IA64 */
 481
 482         if (hwif->pci_dev->device == PCI_DEVICE_ID_INTEL_82371MX) {
 483                 /* This is a painful system best to let it self tune for now */
 484                 return;
 485         }
 486
 487         hwif->autodma = 0;
 488         hwif->tuneproc = &piix_tune_drive;
 489         hwif->speedproc = &piix_tune_chipset;
 490         hwif->drives[0].autotune = 1;
 491         hwif->drives[1].autotune = 1;
 492
 493         if (!hwif->dma_base)
 494                 return;
 495
 496         hwif->atapi_dma = 1;
 497         hwif->ultra_mask = 0x3f;
 498         hwif->mwdma_mask = 0x06;
 499         hwif->swdma_mask = 0x04;
 500
 501         switch(hwif->pci_dev->device) {
 502                 case PCI_DEVICE_ID_INTEL_82371MX:
 503                         hwif->mwdma_mask = 0x80;
 504                         hwif->swdma_mask = 0x80;
 505                 case PCI_DEVICE_ID_INTEL_82371FB_0:
 506                 case PCI_DEVICE_ID_INTEL_82371FB_1:
 507                 case PCI_DEVICE_ID_INTEL_82371SB_1:
 508                         hwif->ultra_mask = 0x80;
 509                         break;
 510                 case PCI_DEVICE_ID_INTEL_82371AB:
 511                 case PCI_DEVICE_ID_INTEL_82443MX_1:
 512                 case PCI_DEVICE_ID_INTEL_82451NX:
 513                 case PCI_DEVICE_ID_INTEL_82801AB_1:
 514                         hwif->ultra_mask = 0x07;
 515                         break;
 516                 default:
 517                         pci_read_config_byte(hwif->pci_dev, 0x54, &reg54h);
 518                         pci_read_config_byte(hwif->pci_dev, 0x55, &reg55h);
 519                         ata66 = (reg54h & mask) ? 1 : 0;
 520                         break;
 521         }
 522
 523         if (!(hwif->udma_four))
 524                 hwif->udma_four = ata66;
 525         hwif->ide_dma_check = &piix_config_drive_xfer_rate;
 526         if (!noautodma)
 527                 hwif->autodma = 1;
 528
 529         hwif->drives[1].autodma = hwif->autodma;
 530         hwif->drives[0].autodma = hwif->autodma;
 531 }
 532
 533 #define DECLARE_PIIX_DEV(name_str) \
 534         {                                               \
 535                 .name           = name_str,             \
 536                 .init_chipset   = init_chipset_piix,    \
 537                 .init_hwif      = init_hwif_piix,       \
 538                 .channels       = 2,                    \
 539                 .autodma        = AUTODMA,              \
 540                 .enablebits     = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
 541                 .bootable       = ON_BOARD,             \
 542         }
 543
 544 static ide_pci_device_t piix_pci_info[] __devinitdata = {
 545         /*  0 */ DECLARE_PIIX_DEV("PIIXa"),
 546         /*  1 */ DECLARE_PIIX_DEV("PIIXb"),
 547
 548         {       /* 2 */
 549                 .name           = "MPIIX",
 550                 .init_hwif      = init_hwif_piix,
 551                 .channels       = 2,
 552                 .autodma        = NODMA,
 553                 .enablebits     = {{0x6D,0x80,0x80}, {0x6F,0x80,0x80}},
 554                 .bootable       = ON_BOARD,
 555         },
 556
 557         /*  3 */ DECLARE_PIIX_DEV("PIIX3"),
 558         /*  4 */ DECLARE_PIIX_DEV("PIIX4"),
 559         /*  5 */ DECLARE_PIIX_DEV("ICH0"),
 560         /*  6 */ DECLARE_PIIX_DEV("PIIX4"),
 561         /*  7 */ DECLARE_PIIX_DEV("ICH"),
 562         /*  8 */ DECLARE_PIIX_DEV("PIIX4"),
 563         /*  9 */ DECLARE_PIIX_DEV("PIIX4"),
 564         /* 10 */ DECLARE_PIIX_DEV("ICH2"),
 565         /* 11 */ DECLARE_PIIX_DEV("ICH2M"),
 566         /* 12 */ DECLARE_PIIX_DEV("ICH3M"),
 567         /* 13 */ DECLARE_PIIX_DEV("ICH3"),
 568         /* 14 */ DECLARE_PIIX_DEV("ICH4"),
 569         /* 15 */ DECLARE_PIIX_DEV("ICH5"),
 570         /* 16 */ DECLARE_PIIX_DEV("C-ICH"),
 571         /* 17 */ DECLARE_PIIX_DEV("ICH4"),
 572         /* 18 */ DECLARE_PIIX_DEV("ICH5-SATA"),
 573         /* 19 */ DECLARE_PIIX_DEV("ICH5"),
 574         /* 20 */ DECLARE_PIIX_DEV("ICH6"),
 575         /* 21 */ DECLARE_PIIX_DEV("ICH7"),
 576         /* 22 */ DECLARE_PIIX_DEV("ICH4"),
 577         /* 23 */ DECLARE_PIIX_DEV("ESB2"),
 578 };
 579
 580 /**
 581  *      piix_init_one   -       called when a PIIX is found
 582  *      @dev: the piix device
 583  *      @id: the matching pci id
 584  *
 585  *      Called when the PCI registration layer (or the IDE initialization)
 586  *      finds a device matching our IDE device tables.
 587  */
 588
 589 static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 590 {
 591         ide_pci_device_t *d = &piix_pci_info[id->driver_data];
 592
 593         return ide_setup_pci_device(dev, d);
 594 }
 595
 596 /**
 597  *      piix_check_450nx        -       Check for problem 450NX setup
 598  *
 599  *      Check for the present of 450NX errata #19 and errata #25. If
 600  *      they are found, disable use of DMA IDE
 601  */
 602
 603 static void __devinit piix_check_450nx(void)
 604 {
 605         struct pci_dev *pdev = NULL;
 606         u16 cfg;
 607         u8 rev;
 608         while((pdev=pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
 609         {
 610                 /* Look for 450NX PXB. Check for problem configurations
 611                    A PCI quirk checks bit 6 already */
 612                 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
 613                 pci_read_config_word(pdev, 0x41, &cfg);
 614                 /* Only on the original revision: IDE DMA can hang */
 615                 if(rev == 0x00)
 616                         no_piix_dma = 1;
 617                 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
 618                 else if(cfg & (1<<14) && rev < 5)
 619                         no_piix_dma = 2;
 620         }
 621         if(no_piix_dma)
 622                 printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n");
 623         if(no_piix_dma == 2)
 624                 printk(KERN_WARNING "piix: A BIOS update may resolve this.\n");
 625 }
 626
 627 static struct pci_device_id piix_pci_tbl[] = {
 628         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 629         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
 630         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX,   PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
 631         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
 632         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,   PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
 633         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
 634         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
 635         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7},
 636         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82372FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8},
 637         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX,   PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9},
 638         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10},
 639         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11},
 640         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12},
 641         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13},
 642         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14},
 643         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 15},
 644         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_11, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 16},
 645         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 17},
 646 #ifdef CONFIG_BLK_DEV_IDE_SATA
 647         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 18},
 648 #endif
 649         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 19},
 650         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_19, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 20},
 651         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 21},
 652         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 22},
 653         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_18, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 23},
 654         { 0, },
 655 };
 656 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
 657
 658 static struct pci_driver driver = {
 659         .name           = "PIIX_IDE",
 660         .id_table       = piix_pci_tbl,
 661         .probe          = piix_init_one,
 662 };
 663
 664 static int __init piix_ide_init(void)
 665 {
 666         piix_check_450nx();
 667         return ide_pci_register_driver(&driver);
 668 }
 669
 670 module_init(piix_ide_init);
 671
 672 MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
 673 MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
 674 MODULE_LICENSE("GPL");