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[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / drivers / ieee1394 / ohci1394.c
blob36e25ac823dc73c2f69c58e391dd4382af59de55
1 /*
2 * ohci1394.c - driver for OHCI 1394 boards
3 * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
4 * Gord Peters <GordPeters@smarttech.com>
5 * 2001 Ben Collins <bcollins@debian.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software Foundation,
19 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22 /*
23 * Things known to be working:
24 * . Async Request Transmit
25 * . Async Response Receive
26 * . Async Request Receive
27 * . Async Response Transmit
28 * . Iso Receive
29 * . DMA mmap for iso receive
30 * . Config ROM generation
31 *
32 * Things implemented, but still in test phase:
33 * . Iso Transmit
34 * . Async Stream Packets Transmit (Receive done via Iso interface)
35 *
36 * Things not implemented:
37 * . DMA error recovery
38 *
39 * Known bugs:
40 * . devctl BUS_RESET arg confusion (reset type or root holdoff?)
41 * added LONG_RESET_ROOT and SHORT_RESET_ROOT for root holdoff --kk
42 */
43
44 /*
45 * Acknowledgments:
46 *
47 * Adam J Richter <adam@yggdrasil.com>
48 * . Use of pci_class to find device
49 *
50 * Emilie Chung <emilie.chung@axis.com>
51 * . Tip on Async Request Filter
52 *
53 * Pascal Drolet <pascal.drolet@informission.ca>
54 * . Various tips for optimization and functionnalities
55 *
56 * Robert Ficklin <rficklin@westengineering.com>
57 * . Loop in irq_handler
58 *
59 * James Goodwin <jamesg@Filanet.com>
60 * . Various tips on initialization, self-id reception, etc.
61 *
62 * Albrecht Dress <ad@mpifr-bonn.mpg.de>
63 * . Apple PowerBook detection
64 *
65 * Daniel Kobras <daniel.kobras@student.uni-tuebingen.de>
66 * . Reset the board properly before leaving + misc cleanups
67 *
68 * Leon van Stuivenberg <leonvs@iae.nl>
69 * . Bug fixes
70 *
71 * Ben Collins <bcollins@debian.org>
72 * . Working big-endian support
73 * . Updated to 2.4.x module scheme (PCI aswell)
74 * . Config ROM generation
75 *
76 * Manfred Weihs <weihs@ict.tuwien.ac.at>
77 * . Reworked code for initiating bus resets
78 * (long, short, with or without hold-off)
79 *
80 * Nandu Santhi <contactnandu@users.sourceforge.net>
81 * . Added support for nVidia nForce2 onboard Firewire chipset
82 *
83 */
84
85 #include <linux/config.h>
86 #include <linux/kernel.h>
87 #include <linux/list.h>
88 #include <linux/slab.h>
89 #include <linux/interrupt.h>
90 #include <linux/wait.h>
91 #include <linux/errno.h>
92 #include <linux/module.h>
93 #include <linux/moduleparam.h>
94 #include <linux/pci.h>
95 #include <linux/fs.h>
96 #include <linux/poll.h>
97 #include <asm/byteorder.h>
98 #include <asm/atomic.h>
99 #include <asm/uaccess.h>
100 #include <linux/delay.h>
101 #include <linux/spinlock.h>
102
103 #include <asm/pgtable.h>
104 #include <asm/page.h>
105 #include <asm/irq.h>
106 #include <linux/sched.h>
107 #include <linux/types.h>
108 #include <linux/vmalloc.h>
109 #include <linux/init.h>
110
111 #ifdef CONFIG_PPC_PMAC
112 #include <asm/machdep.h>
113 #include <asm/pmac_feature.h>
114 #include <asm/prom.h>
115 #include <asm/pci-bridge.h>
116 #endif
117
118 #include "csr1212.h"
119 #include "ieee1394.h"
120 #include "ieee1394_types.h"
121 #include "hosts.h"
122 #include "dma.h"
123 #include "iso.h"
124 #include "ieee1394_core.h"
125 #include "highlevel.h"
126 #include "ohci1394.h"
127
128 #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
129 #define OHCI1394_DEBUG
130 #endif
131
132 #ifdef DBGMSG
133 #undef DBGMSG
134 #endif
135
136 #ifdef OHCI1394_DEBUG
137 #define DBGMSG(fmt, args...) \
138 printk(KERN_INFO "%s: fw-host%d: " fmt "\n" , OHCI1394_DRIVER_NAME, ohci->host->id , ## args)
139 #else
140 #define DBGMSG(fmt, args...)
141 #endif
142
143 #ifdef CONFIG_IEEE1394_OHCI_DMA_DEBUG
144 #define OHCI_DMA_ALLOC(fmt, args...) \
145 HPSB_ERR("%s(%s)alloc(%d): "fmt, OHCI1394_DRIVER_NAME, __FUNCTION__, \
146 ++global_outstanding_dmas, ## args)
147 #define OHCI_DMA_FREE(fmt, args...) \
148 HPSB_ERR("%s(%s)free(%d): "fmt, OHCI1394_DRIVER_NAME, __FUNCTION__, \
149 --global_outstanding_dmas, ## args)
150 static int global_outstanding_dmas = 0;
151 #else
152 #define OHCI_DMA_ALLOC(fmt, args...)
153 #define OHCI_DMA_FREE(fmt, args...)
154 #endif
155
156 /* print general (card independent) information */
157 #define PRINT_G(level, fmt, args...) \
158 printk(level "%s: " fmt "\n" , OHCI1394_DRIVER_NAME , ## args)
159
160 /* print card specific information */
161 #define PRINT(level, fmt, args...) \
162 printk(level "%s: fw-host%d: " fmt "\n" , OHCI1394_DRIVER_NAME, ohci->host->id , ## args)
163
164 static char version[] __devinitdata =
165 "$Rev: 1250 $ Ben Collins <bcollins@debian.org>";
166
167 /* Module Parameters */
168 static int phys_dma = 1;
169 module_param(phys_dma, int, 0644);
170 MODULE_PARM_DESC(phys_dma, "Enable physical dma (default = 1).");
171
172 static void dma_trm_tasklet(unsigned long data);
173 static void dma_trm_reset(struct dma_trm_ctx *d);
174
175 static int alloc_dma_rcv_ctx(struct ti_ohci *ohci, struct dma_rcv_ctx *d,
176 enum context_type type, int ctx, int num_desc,
177 int buf_size, int split_buf_size, int context_base);
178 static void stop_dma_rcv_ctx(struct dma_rcv_ctx *d);
179 static void free_dma_rcv_ctx(struct dma_rcv_ctx *d);
180
181 static int alloc_dma_trm_ctx(struct ti_ohci *ohci, struct dma_trm_ctx *d,
182 enum context_type type, int ctx, int num_desc,
183 int context_base);
184
185 static void ohci1394_pci_remove(struct pci_dev *pdev);
186
187 #ifndef __LITTLE_ENDIAN
188 static unsigned hdr_sizes[] =
189 {
190 3, /* TCODE_WRITEQ */
191 4, /* TCODE_WRITEB */
192 3, /* TCODE_WRITE_RESPONSE */
193 0, /* ??? */
194 3, /* TCODE_READQ */
195 4, /* TCODE_READB */
196 3, /* TCODE_READQ_RESPONSE */
197 4, /* TCODE_READB_RESPONSE */
198 1, /* TCODE_CYCLE_START (???) */
199 4, /* TCODE_LOCK_REQUEST */
200 2, /* TCODE_ISO_DATA */
201 4, /* TCODE_LOCK_RESPONSE */
202 };
203
204 /* Swap headers */
205 static inline void packet_swab(quadlet_t *data, int tcode)
206 {
207 size_t size = hdr_sizes[tcode];
208
209 if (tcode > TCODE_LOCK_RESPONSE || hdr_sizes[tcode] == 0)
210 return;
211
212 while (size--)
213 data[size] = swab32(data[size]);
214 }
215 #else
216 /* Don't waste cycles on same sex byte swaps */
217 #define packet_swab(w,x)
218 #endif /* !LITTLE_ENDIAN */
219
220 /***********************************
221 * IEEE-1394 functionality section *
222 ***********************************/
223
224 static u8 get_phy_reg(struct ti_ohci *ohci, u8 addr)
225 {
226 int i;
227 unsigned long flags;
228 quadlet_t r;
229
230 spin_lock_irqsave (&ohci->phy_reg_lock, flags);
231
232 reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | 0x00008000);
233
234 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
235 if (reg_read(ohci, OHCI1394_PhyControl) & 0x80000000)
236 break;
237
238 mdelay(1);
239 }
240
241 r = reg_read(ohci, OHCI1394_PhyControl);
242
243 if (i >= OHCI_LOOP_COUNT)
244 PRINT (KERN_ERR, "Get PHY Reg timeout [0x%08x/0x%08x/%d]",
245 r, r & 0x80000000, i);
246
247 spin_unlock_irqrestore (&ohci->phy_reg_lock, flags);
248
249 return (r & 0x00ff0000) >> 16;
250 }
251
252 static void set_phy_reg(struct ti_ohci *ohci, u8 addr, u8 data)
253 {
254 int i;
255 unsigned long flags;
256 u32 r = 0;
257
258 spin_lock_irqsave (&ohci->phy_reg_lock, flags);
259
260 reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | data | 0x00004000);
261
262 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
263 r = reg_read(ohci, OHCI1394_PhyControl);
264 if (!(r & 0x00004000))
265 break;
266
267 mdelay(1);
268 }
269
270 if (i == OHCI_LOOP_COUNT)
271 PRINT (KERN_ERR, "Set PHY Reg timeout [0x%08x/0x%08x/%d]",
272 r, r & 0x00004000, i);
273
274 spin_unlock_irqrestore (&ohci->phy_reg_lock, flags);
275
276 return;
277 }
278
279 /* Or's our value into the current value */
280 static void set_phy_reg_mask(struct ti_ohci *ohci, u8 addr, u8 data)
281 {
282 u8 old;
283
284 old = get_phy_reg (ohci, addr);
285 old |= data;
286 set_phy_reg (ohci, addr, old);
287
288 return;
289 }
290
291 static void handle_selfid(struct ti_ohci *ohci, struct hpsb_host *host,
292 int phyid, int isroot)
293 {
294 quadlet_t *q = ohci->selfid_buf_cpu;
295 quadlet_t self_id_count=reg_read(ohci, OHCI1394_SelfIDCount);
296 size_t size;
297 quadlet_t q0, q1;
298
299 /* Check status of self-id reception */
300
301 if (ohci->selfid_swap)
302 q0 = le32_to_cpu(q[0]);
303 else
304 q0 = q[0];
305
306 if ((self_id_count & 0x80000000) ||
307 ((self_id_count & 0x00FF0000) != (q0 & 0x00FF0000))) {
308 PRINT(KERN_ERR,
309 "Error in reception of SelfID packets [0x%08x/0x%08x] (count: %d)",
310 self_id_count, q0, ohci->self_id_errors);
311
312 /* Tip by James Goodwin <jamesg@Filanet.com>:
313 * We had an error, generate another bus reset in response. */
314 if (ohci->self_id_errors<OHCI1394_MAX_SELF_ID_ERRORS) {
315 set_phy_reg_mask (ohci, 1, 0x40);
316 ohci->self_id_errors++;
317 } else {
318 PRINT(KERN_ERR,
319 "Too many errors on SelfID error reception, giving up!");
320 }
321 return;
322 }
323
324 /* SelfID Ok, reset error counter. */
325 ohci->self_id_errors = 0;
326
327 size = ((self_id_count & 0x00001FFC) >> 2) - 1;
328 q++;
329
330 while (size > 0) {
331 if (ohci->selfid_swap) {
332 q0 = le32_to_cpu(q[0]);
333 q1 = le32_to_cpu(q[1]);
334 } else {
335 q0 = q[0];
336 q1 = q[1];
337 }
338
339 if (q0 == ~q1) {
340 DBGMSG ("SelfID packet 0x%x received", q0);
341 hpsb_selfid_received(host, cpu_to_be32(q0));
342 if (((q0 & 0x3f000000) >> 24) == phyid)
343 DBGMSG ("SelfID for this node is 0x%08x", q0);
344 } else {
345 PRINT(KERN_ERR,
346 "SelfID is inconsistent [0x%08x/0x%08x]", q0, q1);
347 }
348 q += 2;
349 size -= 2;
350 }
351
352 DBGMSG("SelfID complete");
353
354 return;
355 }
356
357 static void ohci_soft_reset(struct ti_ohci *ohci) {
358 int i;
359
360 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
361
362 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
363 if (!(reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_softReset))
364 break;
365 mdelay(1);
366 }
367 DBGMSG ("Soft reset finished");
368 }
369
370
371 /* Generate the dma receive prgs and start the context */
372 static void initialize_dma_rcv_ctx(struct dma_rcv_ctx *d, int generate_irq)
373 {
374 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
375 int i;
376
377 ohci1394_stop_context(ohci, d->ctrlClear, NULL);
378
379 for (i=0; i<d->num_desc; i++) {
380 u32 c;
381
382 c = DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE | DMA_CTL_BRANCH;
383 if (generate_irq)
384 c |= DMA_CTL_IRQ;
385
386 d->prg_cpu[i]->control = cpu_to_le32(c | d->buf_size);
387
388 /* End of descriptor list? */
389 if (i + 1 < d->num_desc) {
390 d->prg_cpu[i]->branchAddress =
391 cpu_to_le32((d->prg_bus[i+1] & 0xfffffff0) | 0x1);
392 } else {
393 d->prg_cpu[i]->branchAddress =
394 cpu_to_le32((d->prg_bus[0] & 0xfffffff0));
395 }
396
397 d->prg_cpu[i]->address = cpu_to_le32(d->buf_bus[i]);
398 d->prg_cpu[i]->status = cpu_to_le32(d->buf_size);
399 }
400
401 d->buf_ind = 0;
402 d->buf_offset = 0;
403
404 if (d->type == DMA_CTX_ISO) {
405 /* Clear contextControl */
406 reg_write(ohci, d->ctrlClear, 0xffffffff);
407
408 /* Set bufferFill, isochHeader, multichannel for IR context */
409 reg_write(ohci, d->ctrlSet, 0xd0000000);
410
411 /* Set the context match register to match on all tags */
412 reg_write(ohci, d->ctxtMatch, 0xf0000000);
413
414 /* Clear the multi channel mask high and low registers */
415 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, 0xffffffff);
416 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, 0xffffffff);
417
418 /* Set up isoRecvIntMask to generate interrupts */
419 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << d->ctx);
420 }
421
422 /* Tell the controller where the first AR program is */
423 reg_write(ohci, d->cmdPtr, d->prg_bus[0] | 0x1);
424
425 /* Run context */
426 reg_write(ohci, d->ctrlSet, 0x00008000);
427
428 DBGMSG("Receive DMA ctx=%d initialized", d->ctx);
429 }
430
431 /* Initialize the dma transmit context */
432 static void initialize_dma_trm_ctx(struct dma_trm_ctx *d)
433 {
434 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
435
436 /* Stop the context */
437 ohci1394_stop_context(ohci, d->ctrlClear, NULL);
438
439 d->prg_ind = 0;
440 d->sent_ind = 0;
441 d->free_prgs = d->num_desc;
442 d->branchAddrPtr = NULL;
443 INIT_LIST_HEAD(&d->fifo_list);
444 INIT_LIST_HEAD(&d->pending_list);
445
446 if (d->type == DMA_CTX_ISO) {
447 /* enable interrupts */
448 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << d->ctx);
449 }
450
451 DBGMSG("Transmit DMA ctx=%d initialized", d->ctx);
452 }
453
454 /* Count the number of available iso contexts */
455 static int get_nb_iso_ctx(struct ti_ohci *ohci, int reg)
456 {
457 int i,ctx=0;
458 u32 tmp;
459
460 reg_write(ohci, reg, 0xffffffff);
461 tmp = reg_read(ohci, reg);
462
463 DBGMSG("Iso contexts reg: %08x implemented: %08x", reg, tmp);
464
465 /* Count the number of contexts */
466 for (i=0; i<32; i++) {
467 if (tmp & 1) ctx++;
468 tmp >>= 1;
469 }
470 return ctx;
471 }
472
473 /* Global initialization */
474 static void ohci_initialize(struct ti_ohci *ohci)
475 {
476 char irq_buf[16];
477 quadlet_t buf;
478 int num_ports, i;
479
480 spin_lock_init(&ohci->phy_reg_lock);
481 spin_lock_init(&ohci->event_lock);
482
483 /* Put some defaults to these undefined bus options */
484 buf = reg_read(ohci, OHCI1394_BusOptions);
485 buf |= 0x60000000; /* Enable CMC and ISC */
486 if (!hpsb_disable_irm)
487 buf |= 0x80000000; /* Enable IRMC */
488 buf &= ~0x00ff0000; /* XXX: Set cyc_clk_acc to zero for now */
489 buf &= ~0x18000000; /* Disable PMC and BMC */
490 reg_write(ohci, OHCI1394_BusOptions, buf);
491
492 /* Set the bus number */
493 reg_write(ohci, OHCI1394_NodeID, 0x0000ffc0);
494
495 /* Enable posted writes */
496 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_postedWriteEnable);
497
498 /* Clear link control register */
499 reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);
500
501 /* Enable cycle timer and cycle master and set the IRM
502 * contender bit in our self ID packets if appropriate. */
503 reg_write(ohci, OHCI1394_LinkControlSet,
504 OHCI1394_LinkControl_CycleTimerEnable |
505 OHCI1394_LinkControl_CycleMaster);
506 set_phy_reg_mask(ohci, 4, PHY_04_LCTRL |
507 (hpsb_disable_irm ? 0 : PHY_04_CONTENDER));
508
509 /* Set up self-id dma buffer */
510 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->selfid_buf_bus);
511
512 /* enable self-id and phys */
513 reg_write(ohci, OHCI1394_LinkControlSet, OHCI1394_LinkControl_RcvSelfID |
514 OHCI1394_LinkControl_RcvPhyPkt);
515
516 /* Set the Config ROM mapping register */
517 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->csr_config_rom_bus);
518
519 /* Now get our max packet size */
520 ohci->max_packet_size =
521 1<<(((reg_read(ohci, OHCI1394_BusOptions)>>12)&0xf)+1);
522
523 /* Don't accept phy packets into AR request context */
524 reg_write(ohci, OHCI1394_LinkControlClear, 0x00000400);
525
526 /* Clear the interrupt mask */
527 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);
528 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);
529
530 /* Clear the interrupt mask */
531 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);
532 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);
533
534 /* Initialize AR dma */
535 initialize_dma_rcv_ctx(&ohci->ar_req_context, 0);
536 initialize_dma_rcv_ctx(&ohci->ar_resp_context, 0);
537
538 /* Initialize AT dma */
539 initialize_dma_trm_ctx(&ohci->at_req_context);
540 initialize_dma_trm_ctx(&ohci->at_resp_context);
541
542 /* Initialize IR Legacy DMA channel mask */
543 ohci->ir_legacy_channels = 0;
544
545 /*
546 * Accept AT requests from all nodes. This probably
547 * will have to be controlled from the subsystem
548 * on a per node basis.
549 */
550 reg_write(ohci,OHCI1394_AsReqFilterHiSet, 0x80000000);
551
552 /* Specify AT retries */
553 reg_write(ohci, OHCI1394_ATRetries,
554 OHCI1394_MAX_AT_REQ_RETRIES |
555 (OHCI1394_MAX_AT_RESP_RETRIES<<4) |
556 (OHCI1394_MAX_PHYS_RESP_RETRIES<<8));
557
558 /* We don't want hardware swapping */
559 reg_write(ohci, OHCI1394_HCControlClear, OHCI1394_HCControl_noByteSwap);
560
561 /* Enable interrupts */
562 reg_write(ohci, OHCI1394_IntMaskSet,
563 OHCI1394_unrecoverableError |
564 OHCI1394_masterIntEnable |
565 OHCI1394_busReset |
566 OHCI1394_selfIDComplete |
567 OHCI1394_RSPkt |
568 OHCI1394_RQPkt |
569 OHCI1394_respTxComplete |
570 OHCI1394_reqTxComplete |
571 OHCI1394_isochRx |
572 OHCI1394_isochTx |
573 OHCI1394_cycleInconsistent);
574
575 /* Enable link */
576 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_linkEnable);
577
578 buf = reg_read(ohci, OHCI1394_Version);
579 #ifndef __sparc__
580 sprintf (irq_buf, "%d", ohci->dev->irq);
581 #else
582 sprintf (irq_buf, "%s", __irq_itoa(ohci->dev->irq));
583 #endif
584 PRINT(KERN_INFO, "OHCI-1394 %d.%d (PCI): IRQ=[%s] "
585 "MMIO=[%lx-%lx] Max Packet=[%d]",
586 ((((buf) >> 16) & 0xf) + (((buf) >> 20) & 0xf) * 10),
587 ((((buf) >> 4) & 0xf) + ((buf) & 0xf) * 10), irq_buf,
588 pci_resource_start(ohci->dev, 0),
589 pci_resource_start(ohci->dev, 0) + OHCI1394_REGISTER_SIZE - 1,
590 ohci->max_packet_size);
591
592 /* Check all of our ports to make sure that if anything is
593 * connected, we enable that port. */
594 num_ports = get_phy_reg(ohci, 2) & 0xf;
595 for (i = 0; i < num_ports; i++) {
596 unsigned int status;
597
598 set_phy_reg(ohci, 7, i);
599 status = get_phy_reg(ohci, 8);
600
601 if (status & 0x20)
602 set_phy_reg(ohci, 8, status & ~1);
603 }
604
605 /* Serial EEPROM Sanity check. */
606 if ((ohci->max_packet_size < 512) ||
607 (ohci->max_packet_size > 4096)) {
608 /* Serial EEPROM contents are suspect, set a sane max packet
609 * size and print the raw contents for bug reports if verbose
610 * debug is enabled. */
611 #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
612 int i;
613 #endif
614
615 PRINT(KERN_DEBUG, "Serial EEPROM has suspicious values, "
616 "attempting to setting max_packet_size to 512 bytes");
617 reg_write(ohci, OHCI1394_BusOptions,
618 (reg_read(ohci, OHCI1394_BusOptions) & 0xf007) | 0x8002);
619 ohci->max_packet_size = 512;
620 #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
621 PRINT(KERN_DEBUG, " EEPROM Present: %d",
622 (reg_read(ohci, OHCI1394_Version) >> 24) & 0x1);
623 reg_write(ohci, OHCI1394_GUID_ROM, 0x80000000);
624
625 for (i = 0;
626 ((i < 1000) &&
627 (reg_read(ohci, OHCI1394_GUID_ROM) & 0x80000000)); i++)
628 udelay(10);
629
630 for (i = 0; i < 0x20; i++) {
631 reg_write(ohci, OHCI1394_GUID_ROM, 0x02000000);
632 PRINT(KERN_DEBUG, " EEPROM %02x: %02x", i,
633 (reg_read(ohci, OHCI1394_GUID_ROM) >> 16) & 0xff);
634 }
635 #endif
636 }
637 }
638
639 /*
640 * Insert a packet in the DMA fifo and generate the DMA prg
641 * FIXME: rewrite the program in order to accept packets crossing
642 * page boundaries.
643 * check also that a single dma descriptor doesn't cross a
644 * page boundary.
645 */
646 static void insert_packet(struct ti_ohci *ohci,
647 struct dma_trm_ctx *d, struct hpsb_packet *packet)
648 {
649 u32 cycleTimer;
650 int idx = d->prg_ind;
651
652 DBGMSG("Inserting packet for node " NODE_BUS_FMT
653 ", tlabel=%d, tcode=0x%x, speed=%d",
654 NODE_BUS_ARGS(ohci->host, packet->node_id), packet->tlabel,
655 packet->tcode, packet->speed_code);
656
657 d->prg_cpu[idx]->begin.address = 0;
658 d->prg_cpu[idx]->begin.branchAddress = 0;
659
660 if (d->type == DMA_CTX_ASYNC_RESP) {
661 /*
662 * For response packets, we need to put a timeout value in
663 * the 16 lower bits of the status... let's try 1 sec timeout
664 */
665 cycleTimer = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
666 d->prg_cpu[idx]->begin.status = cpu_to_le32(
667 (((((cycleTimer>>25)&0x7)+1)&0x7)<<13) |
668 ((cycleTimer&0x01fff000)>>12));
669
670 DBGMSG("cycleTimer: %08x timeStamp: %08x",
671 cycleTimer, d->prg_cpu[idx]->begin.status);
672 } else
673 d->prg_cpu[idx]->begin.status = 0;
674
675 if ( (packet->type == hpsb_async) || (packet->type == hpsb_raw) ) {
676
677 if (packet->type == hpsb_raw) {
678 d->prg_cpu[idx]->data[0] = cpu_to_le32(OHCI1394_TCODE_PHY<<4);
679 d->prg_cpu[idx]->data[1] = cpu_to_le32(packet->header[0]);
680 d->prg_cpu[idx]->data[2] = cpu_to_le32(packet->header[1]);
681 } else {
682 d->prg_cpu[idx]->data[0] = packet->speed_code<<16 |
683 (packet->header[0] & 0xFFFF);
684
685 if (packet->tcode == TCODE_ISO_DATA) {
686 /* Sending an async stream packet */
687 d->prg_cpu[idx]->data[1] = packet->header[0] & 0xFFFF0000;
688 } else {
689 /* Sending a normal async request or response */
690 d->prg_cpu[idx]->data[1] =
691 (packet->header[1] & 0xFFFF) |
692 (packet->header[0] & 0xFFFF0000);
693 d->prg_cpu[idx]->data[2] = packet->header[2];
694 d->prg_cpu[idx]->data[3] = packet->header[3];
695 }
696 packet_swab(d->prg_cpu[idx]->data, packet->tcode);
697 }
698
699 if (packet->data_size) { /* block transmit */
700 if (packet->tcode == TCODE_STREAM_DATA){
701 d->prg_cpu[idx]->begin.control =
702 cpu_to_le32(DMA_CTL_OUTPUT_MORE |
703 DMA_CTL_IMMEDIATE | 0x8);
704 } else {
705 d->prg_cpu[idx]->begin.control =
706 cpu_to_le32(DMA_CTL_OUTPUT_MORE |
707 DMA_CTL_IMMEDIATE | 0x10);
708 }
709 d->prg_cpu[idx]->end.control =
710 cpu_to_le32(DMA_CTL_OUTPUT_LAST |
711 DMA_CTL_IRQ |
712 DMA_CTL_BRANCH |
713 packet->data_size);
714 /*
715 * Check that the packet data buffer
716 * does not cross a page boundary.
717 *
718 * XXX Fix this some day. eth1394 seems to trigger
719 * it, but ignoring it doesn't seem to cause a
720 * problem.
721 */
722 #if 0
723 if (cross_bound((unsigned long)packet->data,
724 packet->data_size)>0) {
725 /* FIXME: do something about it */
726 PRINT(KERN_ERR,
727 "%s: packet data addr: %p size %Zd bytes "
728 "cross page boundary", __FUNCTION__,
729 packet->data, packet->data_size);
730 }
731 #endif
732 d->prg_cpu[idx]->end.address = cpu_to_le32(
733 pci_map_single(ohci->dev, packet->data,
734 packet->data_size,
735 PCI_DMA_TODEVICE));
736 OHCI_DMA_ALLOC("single, block transmit packet");
737
738 d->prg_cpu[idx]->end.branchAddress = 0;
739 d->prg_cpu[idx]->end.status = 0;
740 if (d->branchAddrPtr)
741 *(d->branchAddrPtr) =
742 cpu_to_le32(d->prg_bus[idx] | 0x3);
743 d->branchAddrPtr =
744 &(d->prg_cpu[idx]->end.branchAddress);
745 } else { /* quadlet transmit */
746 if (packet->type == hpsb_raw)
747 d->prg_cpu[idx]->begin.control =
748 cpu_to_le32(DMA_CTL_OUTPUT_LAST |
749 DMA_CTL_IMMEDIATE |
750 DMA_CTL_IRQ |
751 DMA_CTL_BRANCH |
752 (packet->header_size + 4));
753 else
754 d->prg_cpu[idx]->begin.control =
755 cpu_to_le32(DMA_CTL_OUTPUT_LAST |
756 DMA_CTL_IMMEDIATE |
757 DMA_CTL_IRQ |
758 DMA_CTL_BRANCH |
759 packet->header_size);
760
761 if (d->branchAddrPtr)
762 *(d->branchAddrPtr) =
763 cpu_to_le32(d->prg_bus[idx] | 0x2);
764 d->branchAddrPtr =
765 &(d->prg_cpu[idx]->begin.branchAddress);
766 }
767
768 } else { /* iso packet */
769 d->prg_cpu[idx]->data[0] = packet->speed_code<<16 |
770 (packet->header[0] & 0xFFFF);
771 d->prg_cpu[idx]->data[1] = packet->header[0] & 0xFFFF0000;
772 packet_swab(d->prg_cpu[idx]->data, packet->tcode);
773
774 d->prg_cpu[idx]->begin.control =
775 cpu_to_le32(DMA_CTL_OUTPUT_MORE |
776 DMA_CTL_IMMEDIATE | 0x8);
777 d->prg_cpu[idx]->end.control =
778 cpu_to_le32(DMA_CTL_OUTPUT_LAST |
779 DMA_CTL_UPDATE |
780 DMA_CTL_IRQ |
781 DMA_CTL_BRANCH |
782 packet->data_size);
783 d->prg_cpu[idx]->end.address = cpu_to_le32(
784 pci_map_single(ohci->dev, packet->data,
785 packet->data_size, PCI_DMA_TODEVICE));
786 OHCI_DMA_ALLOC("single, iso transmit packet");
787
788 d->prg_cpu[idx]->end.branchAddress = 0;
789 d->prg_cpu[idx]->end.status = 0;
790 DBGMSG("Iso xmit context info: header[%08x %08x]\n"
791 " begin=%08x %08x %08x %08x\n"
792 " %08x %08x %08x %08x\n"
793 " end =%08x %08x %08x %08x",
794 d->prg_cpu[idx]->data[0], d->prg_cpu[idx]->data[1],
795 d->prg_cpu[idx]->begin.control,
796 d->prg_cpu[idx]->begin.address,
797 d->prg_cpu[idx]->begin.branchAddress,
798 d->prg_cpu[idx]->begin.status,
799 d->prg_cpu[idx]->data[0],
800 d->prg_cpu[idx]->data[1],
801 d->prg_cpu[idx]->data[2],
802 d->prg_cpu[idx]->data[3],
803 d->prg_cpu[idx]->end.control,
804 d->prg_cpu[idx]->end.address,
805 d->prg_cpu[idx]->end.branchAddress,
806 d->prg_cpu[idx]->end.status);
807 if (d->branchAddrPtr)
808 *(d->branchAddrPtr) = cpu_to_le32(d->prg_bus[idx] | 0x3);
809 d->branchAddrPtr = &(d->prg_cpu[idx]->end.branchAddress);
810 }
811 d->free_prgs--;
812
813 /* queue the packet in the appropriate context queue */
814 list_add_tail(&packet->driver_list, &d->fifo_list);
815 d->prg_ind = (d->prg_ind + 1) % d->num_desc;
816 }
817
818 /*
819 * This function fills the FIFO with the (eventual) pending packets
820 * and runs or wakes up the DMA prg if necessary.
821 *
822 * The function MUST be called with the d->lock held.
823 */
824 static void dma_trm_flush(struct ti_ohci *ohci, struct dma_trm_ctx *d)
825 {
826 struct hpsb_packet *packet, *ptmp;
827 int idx = d->prg_ind;
828 int z = 0;
829
830 /* insert the packets into the dma fifo */
831 list_for_each_entry_safe(packet, ptmp, &d->pending_list, driver_list) {
832 if (!d->free_prgs)
833 break;
834
835 /* For the first packet only */
836 if (!z)
837 z = (packet->data_size) ? 3 : 2;
838
839 /* Insert the packet */
840 list_del_init(&packet->driver_list);
841 insert_packet(ohci, d, packet);
842 }
843
844 /* Nothing must have been done, either no free_prgs or no packets */
845 if (z == 0)
846 return;
847
848 /* Is the context running ? (should be unless it is
849 the first packet to be sent in this context) */
850 if (!(reg_read(ohci, d->ctrlSet) & 0x8000)) {
851 u32 nodeId = reg_read(ohci, OHCI1394_NodeID);
852
853 DBGMSG("Starting transmit DMA ctx=%d",d->ctx);
854 reg_write(ohci, d->cmdPtr, d->prg_bus[idx] | z);
855
856 /* Check that the node id is valid, and not 63 */
857 if (!(nodeId & 0x80000000) || (nodeId & 0x3f) == 63)
858 PRINT(KERN_ERR, "Running dma failed because Node ID is not valid");
859 else
860 reg_write(ohci, d->ctrlSet, 0x8000);
861 } else {
862 /* Wake up the dma context if necessary */
863 if (!(reg_read(ohci, d->ctrlSet) & 0x400))
864 DBGMSG("Waking transmit DMA ctx=%d",d->ctx);
865
866 /* do this always, to avoid race condition */
867 reg_write(ohci, d->ctrlSet, 0x1000);
868 }
869
870 return;
871 }
872
873 /* Transmission of an async or iso packet */
874 static int ohci_transmit(struct hpsb_host *host, struct hpsb_packet *packet)
875 {
876 struct ti_ohci *ohci = host->hostdata;
877 struct dma_trm_ctx *d;
878 unsigned long flags;
879
880 if (packet->data_size > ohci->max_packet_size) {
881 PRINT(KERN_ERR,
882 "Transmit packet size %Zd is too big",
883 packet->data_size);
884 return -EOVERFLOW;
885 }
886
887 /* Decide whether we have an iso, a request, or a response packet */
888 if (packet->type == hpsb_raw)
889 d = &ohci->at_req_context;
890 else if ((packet->tcode == TCODE_ISO_DATA) && (packet->type == hpsb_iso)) {
891 /* The legacy IT DMA context is initialized on first
892 * use. However, the alloc cannot be run from
893 * interrupt context, so we bail out if that is the
894 * case. I don't see anyone sending ISO packets from
895 * interrupt context anyway... */
896
897 if (ohci->it_legacy_context.ohci == NULL) {
898 if (in_interrupt()) {
899 PRINT(KERN_ERR,
900 "legacy IT context cannot be initialized during interrupt");
901 return -EINVAL;
902 }
903
904 if (alloc_dma_trm_ctx(ohci, &ohci->it_legacy_context,
905 DMA_CTX_ISO, 0, IT_NUM_DESC,
906 OHCI1394_IsoXmitContextBase) < 0) {
907 PRINT(KERN_ERR,
908 "error initializing legacy IT context");
909 return -ENOMEM;
910 }
911
912 initialize_dma_trm_ctx(&ohci->it_legacy_context);
913 }
914
915 d = &ohci->it_legacy_context;
916 } else if ((packet->tcode & 0x02) && (packet->tcode != TCODE_ISO_DATA))
917 d = &ohci->at_resp_context;
918 else
919 d = &ohci->at_req_context;
920
921 spin_lock_irqsave(&d->lock,flags);
922
923 list_add_tail(&packet->driver_list, &d->pending_list);
924
925 dma_trm_flush(ohci, d);
926
927 spin_unlock_irqrestore(&d->lock,flags);
928
929 return 0;
930 }
931
932 static int ohci_devctl(struct hpsb_host *host, enum devctl_cmd cmd, int arg)
933 {
934 struct ti_ohci *ohci = host->hostdata;
935 int retval = 0;
936 unsigned long flags;
937 int phy_reg;
938
939 switch (cmd) {
940 case RESET_BUS:
941 switch (arg) {
942 case SHORT_RESET:
943 phy_reg = get_phy_reg(ohci, 5);
944 phy_reg |= 0x40;
945 set_phy_reg(ohci, 5, phy_reg); /* set ISBR */
946 break;
947 case LONG_RESET:
948 phy_reg = get_phy_reg(ohci, 1);
949 phy_reg |= 0x40;
950 set_phy_reg(ohci, 1, phy_reg); /* set IBR */
951 break;
952 case SHORT_RESET_NO_FORCE_ROOT:
953 phy_reg = get_phy_reg(ohci, 1);
954 if (phy_reg & 0x80) {
955 phy_reg &= ~0x80;
956 set_phy_reg(ohci, 1, phy_reg); /* clear RHB */
957 }
958
959 phy_reg = get_phy_reg(ohci, 5);
960 phy_reg |= 0x40;
961 set_phy_reg(ohci, 5, phy_reg); /* set ISBR */
962 break;
963 case LONG_RESET_NO_FORCE_ROOT:
964 phy_reg = get_phy_reg(ohci, 1);
965 phy_reg &= ~0x80;
966 phy_reg |= 0x40;
967 set_phy_reg(ohci, 1, phy_reg); /* clear RHB, set IBR */
968 break;
969 case SHORT_RESET_FORCE_ROOT:
970 phy_reg = get_phy_reg(ohci, 1);
971 if (!(phy_reg & 0x80)) {
972 phy_reg |= 0x80;
973 set_phy_reg(ohci, 1, phy_reg); /* set RHB */
974 }
975
976 phy_reg = get_phy_reg(ohci, 5);
977 phy_reg |= 0x40;
978 set_phy_reg(ohci, 5, phy_reg); /* set ISBR */
979 break;
980 case LONG_RESET_FORCE_ROOT:
981 phy_reg = get_phy_reg(ohci, 1);
982 phy_reg |= 0xc0;
983 set_phy_reg(ohci, 1, phy_reg); /* set RHB and IBR */
984 break;
985 default:
986 retval = -1;
987 }
988 break;
989
990 case GET_CYCLE_COUNTER:
991 retval = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
992 break;
993
994 case SET_CYCLE_COUNTER:
995 reg_write(ohci, OHCI1394_IsochronousCycleTimer, arg);
996 break;
997
998 case SET_BUS_ID:
999 PRINT(KERN_ERR, "devctl command SET_BUS_ID err");
1000 break;
1001
1002 case ACT_CYCLE_MASTER:
1003 if (arg) {
1004 /* check if we are root and other nodes are present */
1005 u32 nodeId = reg_read(ohci, OHCI1394_NodeID);
1006 if ((nodeId & (1<<30)) && (nodeId & 0x3f)) {
1007 /*
1008 * enable cycleTimer, cycleMaster
1009 */
1010 DBGMSG("Cycle master enabled");
1011 reg_write(ohci, OHCI1394_LinkControlSet,
1012 OHCI1394_LinkControl_CycleTimerEnable |
1013 OHCI1394_LinkControl_CycleMaster);
1014 }
1015 } else {
1016 /* disable cycleTimer, cycleMaster, cycleSource */
1017 reg_write(ohci, OHCI1394_LinkControlClear,
1018 OHCI1394_LinkControl_CycleTimerEnable |
1019 OHCI1394_LinkControl_CycleMaster |
1020 OHCI1394_LinkControl_CycleSource);
1021 }
1022 break;
1023
1024 case CANCEL_REQUESTS:
1025 DBGMSG("Cancel request received");
1026 dma_trm_reset(&ohci->at_req_context);
1027 dma_trm_reset(&ohci->at_resp_context);
1028 break;
1029
1030 case ISO_LISTEN_CHANNEL:
1031 {
1032 u64 mask;
1033 struct dma_rcv_ctx *d = &ohci->ir_legacy_context;
1034 int ir_legacy_active;
1035
1036 if (arg<0 || arg>63) {
1037 PRINT(KERN_ERR,
1038 "%s: IS0 listen channel %d is out of range",
1039 __FUNCTION__, arg);
1040 return -EFAULT;
1041 }
1042
1043 mask = (u64)0x1<<arg;
1044
1045 spin_lock_irqsave(&ohci->IR_channel_lock, flags);
1046
1047 if (ohci->ISO_channel_usage & mask) {
1048 PRINT(KERN_ERR,
1049 "%s: IS0 listen channel %d is already used",
1050 __FUNCTION__, arg);
1051 spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
1052 return -EFAULT;
1053 }
1054
1055 ir_legacy_active = ohci->ir_legacy_channels;
1056
1057 ohci->ISO_channel_usage |= mask;
1058 ohci->ir_legacy_channels |= mask;
1059
1060 spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
1061
1062 if (!ir_legacy_active) {
1063 if (ohci1394_register_iso_tasklet(ohci,
1064 &ohci->ir_legacy_tasklet) < 0) {
1065 PRINT(KERN_ERR, "No IR DMA context available");
1066 return -EBUSY;
1067 }
1068
1069 /* the IR context can be assigned to any DMA context
1070 * by ohci1394_register_iso_tasklet */
1071 d->ctx = ohci->ir_legacy_tasklet.context;
1072 d->ctrlSet = OHCI1394_IsoRcvContextControlSet +
1073 32*d->ctx;
1074 d->ctrlClear = OHCI1394_IsoRcvContextControlClear +
1075 32*d->ctx;
1076 d->cmdPtr = OHCI1394_IsoRcvCommandPtr + 32*d->ctx;
1077 d->ctxtMatch = OHCI1394_IsoRcvContextMatch + 32*d->ctx;
1078
1079 initialize_dma_rcv_ctx(&ohci->ir_legacy_context, 1);
1080
1081 PRINT(KERN_ERR, "IR legacy activated");
1082 }
1083
1084 spin_lock_irqsave(&ohci->IR_channel_lock, flags);
1085
1086 if (arg>31)
1087 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet,
1088 1<<(arg-32));
1089 else
1090 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet,
1091 1<<arg);
1092
1093 spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
1094 DBGMSG("Listening enabled on channel %d", arg);
1095 break;
1096 }
1097 case ISO_UNLISTEN_CHANNEL:
1098 {
1099 u64 mask;
1100
1101 if (arg<0 || arg>63) {
1102 PRINT(KERN_ERR,
1103 "%s: IS0 unlisten channel %d is out of range",
1104 __FUNCTION__, arg);
1105 return -EFAULT;
1106 }
1107
1108 mask = (u64)0x1<<arg;
1109
1110 spin_lock_irqsave(&ohci->IR_channel_lock, flags);
1111
1112 if (!(ohci->ISO_channel_usage & mask)) {
1113 PRINT(KERN_ERR,
1114 "%s: IS0 unlisten channel %d is not used",
1115 __FUNCTION__, arg);
1116 spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
1117 return -EFAULT;
1118 }
1119
1120 ohci->ISO_channel_usage &= ~mask;
1121 ohci->ir_legacy_channels &= ~mask;
1122
1123 if (arg>31)
1124 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear,
1125 1<<(arg-32));
1126 else
1127 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear,
1128 1<<arg);
1129
1130 spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
1131 DBGMSG("Listening disabled on channel %d", arg);
1132
1133 if (ohci->ir_legacy_channels == 0) {
1134 stop_dma_rcv_ctx(&ohci->ir_legacy_context);
1135 DBGMSG("ISO legacy receive context stopped");
1136 }
1137
1138 break;
1139 }
1140 default:
1141 PRINT_G(KERN_ERR, "ohci_devctl cmd %d not implemented yet",
1142 cmd);
1143 break;
1144 }
1145 return retval;
1146 }
1147
1148 /***********************************
1149 * rawiso ISO reception *
1150 ***********************************/
1151
1152 /*
1153 We use either buffer-fill or packet-per-buffer DMA mode. The DMA
1154 buffer is split into "blocks" (regions described by one DMA
1155 descriptor). Each block must be one page or less in size, and
1156 must not cross a page boundary.
1157
1158 There is one little wrinkle with buffer-fill mode: a packet that
1159 starts in the final block may wrap around into the first block. But
1160 the user API expects all packets to be contiguous. Our solution is
1161 to keep the very last page of the DMA buffer in reserve - if a
1162 packet spans the gap, we copy its tail into this page.
1163 */
1164
1165 struct ohci_iso_recv {
1166 struct ti_ohci *ohci;
1167
1168 struct ohci1394_iso_tasklet task;
1169 int task_active;
1170
1171 enum { BUFFER_FILL_MODE = 0,
1172 PACKET_PER_BUFFER_MODE = 1 } dma_mode;
1173
1174 /* memory and PCI mapping for the DMA descriptors */
1175 struct dma_prog_region prog;
1176 struct dma_cmd *block; /* = (struct dma_cmd*) prog.virt */
1177
1178 /* how many DMA blocks fit in the buffer */
1179 unsigned int nblocks;
1180
1181 /* stride of DMA blocks */
1182 unsigned int buf_stride;
1183
1184 /* number of blocks to batch between interrupts */
1185 int block_irq_interval;
1186
1187 /* block that DMA will finish next */
1188 int block_dma;
1189
1190 /* (buffer-fill only) block that the reader will release next */
1191 int block_reader;
1192
1193 /* (buffer-fill only) bytes of buffer the reader has released,
1194 less than one block */
1195 int released_bytes;
1196
1197 /* (buffer-fill only) buffer offset at which the next packet will appear */
1198 int dma_offset;
1199
1200 /* OHCI DMA context control registers */
1201 u32 ContextControlSet;
1202 u32 ContextControlClear;
1203 u32 CommandPtr;
1204 u32 ContextMatch;
1205 };
1206
1207 static void ohci_iso_recv_task(unsigned long data);
1208 static void ohci_iso_recv_stop(struct hpsb_iso *iso);
1209 static void ohci_iso_recv_shutdown(struct hpsb_iso *iso);
1210 static int ohci_iso_recv_start(struct hpsb_iso *iso, int cycle, int tag_mask, int sync);
1211 static void ohci_iso_recv_program(struct hpsb_iso *iso);
1212
1213 static int ohci_iso_recv_init(struct hpsb_iso *iso)
1214 {
1215 struct ti_ohci *ohci = iso->host->hostdata;
1216 struct ohci_iso_recv *recv;
1217 int ctx;
1218 int ret = -ENOMEM;
1219
1220 recv = kmalloc(sizeof(*recv), SLAB_KERNEL);
1221 if (!recv)
1222 return -ENOMEM;
1223
1224 iso->hostdata = recv;
1225 recv->ohci = ohci;
1226 recv->task_active = 0;
1227 dma_prog_region_init(&recv->prog);
1228 recv->block = NULL;
1229
1230 /* use buffer-fill mode, unless irq_interval is 1
1231 (note: multichannel requires buffer-fill) */
1232
1233 if (((iso->irq_interval == 1 && iso->dma_mode == HPSB_ISO_DMA_OLD_ABI) ||
1234 iso->dma_mode == HPSB_ISO_DMA_PACKET_PER_BUFFER) && iso->channel != -1) {
1235 recv->dma_mode = PACKET_PER_BUFFER_MODE;
1236 } else {
1237 recv->dma_mode = BUFFER_FILL_MODE;
1238 }
1239
1240 /* set nblocks, buf_stride, block_irq_interval */
1241
1242 if (recv->dma_mode == BUFFER_FILL_MODE) {
1243 recv->buf_stride = PAGE_SIZE;
1244
1245 /* one block per page of data in the DMA buffer, minus the final guard page */
1246 recv->nblocks = iso->buf_size/PAGE_SIZE - 1;
1247 if (recv->nblocks < 3) {
1248 DBGMSG("ohci_iso_recv_init: DMA buffer too small");
1249 goto err;
1250 }
1251
1252 /* iso->irq_interval is in packets - translate that to blocks */
1253 if (iso->irq_interval == 1)
1254 recv->block_irq_interval = 1;
1255 else
1256 recv->block_irq_interval = iso->irq_interval *
1257 ((recv->nblocks+1)/iso->buf_packets);
1258 if (recv->block_irq_interval*4 > recv->nblocks)
1259 recv->block_irq_interval = recv->nblocks/4;
1260 if (recv->block_irq_interval < 1)
1261 recv->block_irq_interval = 1;
1262
1263 } else {
1264 int max_packet_size;
1265
1266 recv->nblocks = iso->buf_packets;
1267 recv->block_irq_interval = iso->irq_interval;
1268 if (recv->block_irq_interval * 4 > iso->buf_packets)
1269 recv->block_irq_interval = iso->buf_packets / 4;
1270 if (recv->block_irq_interval < 1)
1271 recv->block_irq_interval = 1;
1272
1273 /* choose a buffer stride */
1274 /* must be a power of 2, and <= PAGE_SIZE */
1275
1276 max_packet_size = iso->buf_size / iso->buf_packets;
1277
1278 for (recv->buf_stride = 8; recv->buf_stride < max_packet_size;
1279 recv->buf_stride *= 2);
1280
1281 if (recv->buf_stride*iso->buf_packets > iso->buf_size ||
1282 recv->buf_stride > PAGE_SIZE) {
1283 /* this shouldn't happen, but anyway... */
1284 DBGMSG("ohci_iso_recv_init: problem choosing a buffer stride");
1285 goto err;
1286 }
1287 }
1288
1289 recv->block_reader = 0;
1290 recv->released_bytes = 0;
1291 recv->block_dma = 0;
1292 recv->dma_offset = 0;
1293
1294 /* size of DMA program = one descriptor per block */
1295 if (dma_prog_region_alloc(&recv->prog,
1296 sizeof(struct dma_cmd) * recv->nblocks,
1297 recv->ohci->dev))
1298 goto err;
1299
1300 recv->block = (struct dma_cmd*) recv->prog.kvirt;
1301
1302 ohci1394_init_iso_tasklet(&recv->task,
1303 iso->channel == -1 ? OHCI_ISO_MULTICHANNEL_RECEIVE :
1304 OHCI_ISO_RECEIVE,
1305 ohci_iso_recv_task, (unsigned long) iso);
1306
1307 if (ohci1394_register_iso_tasklet(recv->ohci, &recv->task) < 0) {
1308 ret = -EBUSY;
1309 goto err;
1310 }
1311
1312 recv->task_active = 1;
1313
1314 /* recv context registers are spaced 32 bytes apart */
1315 ctx = recv->task.context;
1316 recv->ContextControlSet = OHCI1394_IsoRcvContextControlSet + 32 * ctx;
1317 recv->ContextControlClear = OHCI1394_IsoRcvContextControlClear + 32 * ctx;
1318 recv->CommandPtr = OHCI1394_IsoRcvCommandPtr + 32 * ctx;
1319 recv->ContextMatch = OHCI1394_IsoRcvContextMatch + 32 * ctx;
1320
1321 if (iso->channel == -1) {
1322 /* clear multi-channel selection mask */
1323 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskHiClear, 0xFFFFFFFF);
1324 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskLoClear, 0xFFFFFFFF);
1325 }
1326
1327 /* write the DMA program */
1328 ohci_iso_recv_program(iso);
1329
1330 DBGMSG("ohci_iso_recv_init: %s mode, DMA buffer is %lu pages"
1331 " (%u bytes), using %u blocks, buf_stride %u, block_irq_interval %d",
1332 recv->dma_mode == BUFFER_FILL_MODE ?
1333 "buffer-fill" : "packet-per-buffer",
1334 iso->buf_size/PAGE_SIZE, iso->buf_size,
1335 recv->nblocks, recv->buf_stride, recv->block_irq_interval);
1336
1337 return 0;
1338
1339 err:
1340 ohci_iso_recv_shutdown(iso);
1341 return ret;
1342 }
1343
1344 static void ohci_iso_recv_stop(struct hpsb_iso *iso)
1345 {
1346 struct ohci_iso_recv *recv = iso->hostdata;
1347
1348 /* disable interrupts */
1349 reg_write(recv->ohci, OHCI1394_IsoRecvIntMaskClear, 1 << recv->task.context);
1350
1351 /* halt DMA */
1352 ohci1394_stop_context(recv->ohci, recv->ContextControlClear, NULL);
1353 }
1354
1355 static void ohci_iso_recv_shutdown(struct hpsb_iso *iso)
1356 {
1357 struct ohci_iso_recv *recv = iso->hostdata;
1358
1359 if (recv->task_active) {
1360 ohci_iso_recv_stop(iso);
1361 ohci1394_unregister_iso_tasklet(recv->ohci, &recv->task);
1362 recv->task_active = 0;
1363 }
1364
1365 dma_prog_region_free(&recv->prog);
1366 kfree(recv);
1367 iso->hostdata = NULL;
1368 }
1369
1370 /* set up a "gapped" ring buffer DMA program */
1371 static void ohci_iso_recv_program(struct hpsb_iso *iso)
1372 {
1373 struct ohci_iso_recv *recv = iso->hostdata;
1374 int blk;
1375
1376 /* address of 'branch' field in previous DMA descriptor */
1377 u32 *prev_branch = NULL;
1378
1379 for (blk = 0; blk < recv->nblocks; blk++) {
1380 u32 control;
1381
1382 /* the DMA descriptor */
1383 struct dma_cmd *cmd = &recv->block[blk];
1384
1385 /* offset of the DMA descriptor relative to the DMA prog buffer */
1386 unsigned long prog_offset = blk * sizeof(struct dma_cmd);
1387
1388 /* offset of this packet's data within the DMA buffer */
1389 unsigned long buf_offset = blk * recv->buf_stride;
1390
1391 if (recv->dma_mode == BUFFER_FILL_MODE) {
1392 control = 2 << 28; /* INPUT_MORE */
1393 } else {
1394 control = 3 << 28; /* INPUT_LAST */
1395 }
1396
1397 control |= 8 << 24; /* s = 1, update xferStatus and resCount */
1398
1399 /* interrupt on last block, and at intervals */
1400 if (blk == recv->nblocks-1 || (blk % recv->block_irq_interval) == 0) {
1401 control |= 3 << 20; /* want interrupt */
1402 }
1403
1404 control |= 3 << 18; /* enable branch to address */
1405 control |= recv->buf_stride;
1406
1407 cmd->control = cpu_to_le32(control);
1408 cmd->address = cpu_to_le32(dma_region_offset_to_bus(&iso->data_buf, buf_offset));
1409 cmd->branchAddress = 0; /* filled in on next loop */
1410 cmd->status = cpu_to_le32(recv->buf_stride);
1411
1412 /* link the previous descriptor to this one */
1413 if (prev_branch) {
1414 *prev_branch = cpu_to_le32(dma_prog_region_offset_to_bus(&recv->prog, prog_offset) | 1);
1415 }
1416
1417 prev_branch = &cmd->branchAddress;
1418 }
1419
1420 /* the final descriptor's branch address and Z should be left at 0 */
1421 }
1422
1423 /* listen or unlisten to a specific channel (multi-channel mode only) */
1424 static void ohci_iso_recv_change_channel(struct hpsb_iso *iso, unsigned char channel, int listen)
1425 {
1426 struct ohci_iso_recv *recv = iso->hostdata;
1427 int reg, i;
1428
1429 if (channel < 32) {
1430 reg = listen ? OHCI1394_IRMultiChanMaskLoSet : OHCI1394_IRMultiChanMaskLoClear;
1431 i = channel;
1432 } else {
1433 reg = listen ? OHCI1394_IRMultiChanMaskHiSet : OHCI1394_IRMultiChanMaskHiClear;
1434 i = channel - 32;
1435 }
1436
1437 reg_write(recv->ohci, reg, (1 << i));
1438
1439 /* issue a dummy read to force all PCI writes to be posted immediately */
1440 mb();
1441 reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer);
1442 }
1443
1444 static void ohci_iso_recv_set_channel_mask(struct hpsb_iso *iso, u64 mask)
1445 {
1446 struct ohci_iso_recv *recv = iso->hostdata;
1447 int i;
1448
1449 for (i = 0; i < 64; i++) {
1450 if (mask & (1ULL << i)) {
1451 if (i < 32)
1452 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskLoSet, (1 << i));
1453 else
1454 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskHiSet, (1 << (i-32)));
1455 } else {
1456 if (i < 32)
1457 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskLoClear, (1 << i));
1458 else
1459 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskHiClear, (1 << (i-32)));
1460 }
1461 }
1462
1463 /* issue a dummy read to force all PCI writes to be posted immediately */
1464 mb();
1465 reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer);
1466 }
1467
1468 static int ohci_iso_recv_start(struct hpsb_iso *iso, int cycle, int tag_mask, int sync)
1469 {
1470 struct ohci_iso_recv *recv = iso->hostdata;
1471 struct ti_ohci *ohci = recv->ohci;
1472 u32 command, contextMatch;
1473
1474 reg_write(recv->ohci, recv->ContextControlClear, 0xFFFFFFFF);
1475 wmb();
1476
1477 /* always keep ISO headers */
1478 command = (1 << 30);
1479
1480 if (recv->dma_mode == BUFFER_FILL_MODE)
1481 command |= (1 << 31);
1482
1483 reg_write(recv->ohci, recv->ContextControlSet, command);
1484
1485 /* match on specified tags */
1486 contextMatch = tag_mask << 28;
1487
1488 if (iso->channel == -1) {
1489 /* enable multichannel reception */
1490 reg_write(recv->ohci, recv->ContextControlSet, (1 << 28));
1491 } else {
1492 /* listen on channel */
1493 contextMatch |= iso->channel;
1494 }
1495
1496 if (cycle != -1) {
1497 u32 seconds;
1498
1499 /* enable cycleMatch */
1500 reg_write(recv->ohci, recv->ContextControlSet, (1 << 29));
1501
1502 /* set starting cycle */
1503 cycle &= 0x1FFF;
1504
1505 /* 'cycle' is only mod 8000, but we also need two 'seconds' bits -
1506 just snarf them from the current time */
1507 seconds = reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer) >> 25;
1508
1509 /* advance one second to give some extra time for DMA to start */
1510 seconds += 1;
1511
1512 cycle |= (seconds & 3) << 13;
1513
1514 contextMatch |= cycle << 12;
1515 }
1516
1517 if (sync != -1) {
1518 /* set sync flag on first DMA descriptor */
1519 struct dma_cmd *cmd = &recv->block[recv->block_dma];
1520 cmd->control |= cpu_to_le32(DMA_CTL_WAIT);
1521
1522 /* match sync field */
1523 contextMatch |= (sync&0xf)<<8;
1524 }
1525
1526 reg_write(recv->ohci, recv->ContextMatch, contextMatch);
1527
1528 /* address of first descriptor block */
1529 command = dma_prog_region_offset_to_bus(&recv->prog,
1530 recv->block_dma * sizeof(struct dma_cmd));
1531 command |= 1; /* Z=1 */
1532
1533 reg_write(recv->ohci, recv->CommandPtr, command);
1534
1535 /* enable interrupts */
1536 reg_write(recv->ohci, OHCI1394_IsoRecvIntMaskSet, 1 << recv->task.context);
1537
1538 wmb();
1539
1540 /* run */
1541 reg_write(recv->ohci, recv->ContextControlSet, 0x8000);
1542
1543 /* issue a dummy read of the cycle timer register to force
1544 all PCI writes to be posted immediately */
1545 mb();
1546 reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer);
1547
1548 /* check RUN */
1549 if (!(reg_read(recv->ohci, recv->ContextControlSet) & 0x8000)) {
1550 PRINT(KERN_ERR,
1551 "Error starting IR DMA (ContextControl 0x%08x)\n",
1552 reg_read(recv->ohci, recv->ContextControlSet));
1553 return -1;
1554 }
1555
1556 return 0;
1557 }
1558
1559 static void ohci_iso_recv_release_block(struct ohci_iso_recv *recv, int block)
1560 {
1561 /* re-use the DMA descriptor for the block */
1562 /* by linking the previous descriptor to it */
1563
1564 int next_i = block;
1565 int prev_i = (next_i == 0) ? (recv->nblocks - 1) : (next_i - 1);
1566
1567 struct dma_cmd *next = &recv->block[next_i];
1568 struct dma_cmd *prev = &recv->block[prev_i];
1569
1570 /* 'next' becomes the new end of the DMA chain,
1571 so disable branch and enable interrupt */
1572 next->branchAddress = 0;
1573 next->control |= cpu_to_le32(3 << 20);
1574 next->status = cpu_to_le32(recv->buf_stride);
1575
1576 /* link prev to next */
1577 prev->branchAddress = cpu_to_le32(dma_prog_region_offset_to_bus(&recv->prog,
1578 sizeof(struct dma_cmd) * next_i)
1579 | 1); /* Z=1 */
1580
1581 /* disable interrupt on previous DMA descriptor, except at intervals */
1582 if ((prev_i % recv->block_irq_interval) == 0) {
1583 prev->control |= cpu_to_le32(3 << 20); /* enable interrupt */
1584 } else {
1585 prev->control &= cpu_to_le32(~(3<<20)); /* disable interrupt */
1586 }
1587 wmb();
1588
1589 /* wake up DMA in case it fell asleep */
1590 reg_write(recv->ohci, recv->ContextControlSet, (1 << 12));
1591 }
1592
1593 static void ohci_iso_recv_bufferfill_release(struct ohci_iso_recv *recv,
1594 struct hpsb_iso_packet_info *info)
1595 {
1596 int len;
1597
1598 /* release the memory where the packet was */
1599 len = info->len;
1600
1601 /* add the wasted space for padding to 4 bytes */
1602 if (len % 4)
1603 len += 4 - (len % 4);
1604
1605 /* add 8 bytes for the OHCI DMA data format overhead */
1606 len += 8;
1607
1608 recv->released_bytes += len;
1609
1610 /* have we released enough memory for one block? */
1611 while (recv->released_bytes > recv->buf_stride) {
1612 ohci_iso_recv_release_block(recv, recv->block_reader);
1613 recv->block_reader = (recv->block_reader + 1) % recv->nblocks;
1614 recv->released_bytes -= recv->buf_stride;
1615 }
1616 }
1617
1618 static inline void ohci_iso_recv_release(struct hpsb_iso *iso, struct hpsb_iso_packet_info *info)
1619 {
1620 struct ohci_iso_recv *recv = iso->hostdata;
1621 if (recv->dma_mode == BUFFER_FILL_MODE) {
1622 ohci_iso_recv_bufferfill_release(recv, info);
1623 } else {
1624 ohci_iso_recv_release_block(recv, info - iso->infos);
1625 }
1626 }
1627
1628 /* parse all packets from blocks that have been fully received */
1629 static void ohci_iso_recv_bufferfill_parse(struct hpsb_iso *iso, struct ohci_iso_recv *recv)
1630 {
1631 int wake = 0;
1632 int runaway = 0;
1633 struct ti_ohci *ohci = recv->ohci;
1634
1635 while (1) {
1636 /* we expect the next parsable packet to begin at recv->dma_offset */
1637 /* note: packet layout is as shown in section 10.6.1.1 of the OHCI spec */
1638
1639 unsigned int offset;
1640 unsigned short len, cycle;
1641 unsigned char channel, tag, sy;
1642
1643 unsigned char *p = iso->data_buf.kvirt;
1644
1645 unsigned int this_block = recv->dma_offset/recv->buf_stride;
1646
1647 /* don't loop indefinitely */
1648 if (runaway++ > 100000) {
1649 atomic_inc(&iso->overflows);
1650 PRINT(KERN_ERR,
1651 "IR DMA error - Runaway during buffer parsing!\n");
1652 break;
1653 }
1654
1655 /* stop parsing once we arrive at block_dma (i.e. don't get ahead of DMA) */
1656 if (this_block == recv->block_dma)
1657 break;
1658
1659 wake = 1;
1660
1661 /* parse data length, tag, channel, and sy */
1662
1663 /* note: we keep our own local copies of 'len' and 'offset'
1664 so the user can't mess with them by poking in the mmap area */
1665
1666 len = p[recv->dma_offset+2] | (p[recv->dma_offset+3] << 8);
1667
1668 if (len > 4096) {
1669 PRINT(KERN_ERR,
1670 "IR DMA error - bogus 'len' value %u\n", len);
1671 }
1672
1673 channel = p[recv->dma_offset+1] & 0x3F;
1674 tag = p[recv->dma_offset+1] >> 6;
1675 sy = p[recv->dma_offset+0] & 0xF;
1676
1677 /* advance to data payload */
1678 recv->dma_offset += 4;
1679
1680 /* check for wrap-around */
1681 if (recv->dma_offset >= recv->buf_stride*recv->nblocks) {
1682 recv->dma_offset -= recv->buf_stride*recv->nblocks;
1683 }
1684
1685 /* dma_offset now points to the first byte of the data payload */
1686 offset = recv->dma_offset;
1687
1688 /* advance to xferStatus/timeStamp */
1689 recv->dma_offset += len;
1690
1691 /* payload is padded to 4 bytes */
1692 if (len % 4) {
1693 recv->dma_offset += 4 - (len%4);
1694 }
1695
1696 /* check for wrap-around */
1697 if (recv->dma_offset >= recv->buf_stride*recv->nblocks) {
1698 /* uh oh, the packet data wraps from the last
1699 to the first DMA block - make the packet
1700 contiguous by copying its "tail" into the
1701 guard page */
1702
1703 int guard_off = recv->buf_stride*recv->nblocks;
1704 int tail_len = len - (guard_off - offset);
1705
1706 if (tail_len > 0 && tail_len < recv->buf_stride) {
1707 memcpy(iso->data_buf.kvirt + guard_off,
1708 iso->data_buf.kvirt,
1709 tail_len);
1710 }
1711
1712 recv->dma_offset -= recv->buf_stride*recv->nblocks;
1713 }
1714
1715 /* parse timestamp */
1716 cycle = p[recv->dma_offset+0] | (p[recv->dma_offset+1]<<8);
1717 cycle &= 0x1FFF;
1718
1719 /* advance to next packet */
1720 recv->dma_offset += 4;
1721
1722 /* check for wrap-around */
1723 if (recv->dma_offset >= recv->buf_stride*recv->nblocks) {
1724 recv->dma_offset -= recv->buf_stride*recv->nblocks;
1725 }
1726
1727 hpsb_iso_packet_received(iso, offset, len, cycle, channel, tag, sy);
1728 }
1729
1730 if (wake)
1731 hpsb_iso_wake(iso);
1732 }
1733
1734 static void ohci_iso_recv_bufferfill_task(struct hpsb_iso *iso, struct ohci_iso_recv *recv)
1735 {
1736 int loop;
1737 struct ti_ohci *ohci = recv->ohci;
1738
1739 /* loop over all blocks */
1740 for (loop = 0; loop < recv->nblocks; loop++) {
1741
1742 /* check block_dma to see if it's done */
1743 struct dma_cmd *im = &recv->block[recv->block_dma];
1744
1745 /* check the DMA descriptor for new writes to xferStatus */
1746 u16 xferstatus = le32_to_cpu(im->status) >> 16;
1747
1748 /* rescount is the number of bytes *remaining to be written* in the block */
1749 u16 rescount = le32_to_cpu(im->status) & 0xFFFF;
1750
1751 unsigned char event = xferstatus & 0x1F;
1752
1753 if (!event) {
1754 /* nothing has happened to this block yet */
1755 break;
1756 }
1757
1758 if (event != 0x11) {
1759 atomic_inc(&iso->overflows);
1760 PRINT(KERN_ERR,
1761 "IR DMA error - OHCI error code 0x%02x\n", event);
1762 }
1763
1764 if (rescount != 0) {
1765 /* the card is still writing to this block;
1766 we can't touch it until it's done */
1767 break;
1768 }
1769
1770 /* OK, the block is finished... */
1771
1772 /* sync our view of the block */
1773 dma_region_sync_for_cpu(&iso->data_buf, recv->block_dma*recv->buf_stride, recv->buf_stride);
1774
1775 /* reset the DMA descriptor */
1776 im->status = recv->buf_stride;
1777
1778 /* advance block_dma */
1779 recv->block_dma = (recv->block_dma + 1) % recv->nblocks;
1780
1781 if ((recv->block_dma+1) % recv->nblocks == recv->block_reader) {
1782 atomic_inc(&iso->overflows);
1783 DBGMSG("ISO reception overflow - "
1784 "ran out of DMA blocks");
1785 }
1786 }
1787
1788 /* parse any packets that have arrived */
1789 ohci_iso_recv_bufferfill_parse(iso, recv);
1790 }
1791
1792 static void ohci_iso_recv_packetperbuf_task(struct hpsb_iso *iso, struct ohci_iso_recv *recv)
1793 {
1794 int count;
1795 int wake = 0;
1796 struct ti_ohci *ohci = recv->ohci;
1797
1798 /* loop over the entire buffer */
1799 for (count = 0; count < recv->nblocks; count++) {
1800 u32 packet_len = 0;
1801
1802 /* pointer to the DMA descriptor */
1803 struct dma_cmd *il = ((struct dma_cmd*) recv->prog.kvirt) + iso->pkt_dma;
1804
1805 /* check the DMA descriptor for new writes to xferStatus */
1806 u16 xferstatus = le32_to_cpu(il->status) >> 16;
1807 u16 rescount = le32_to_cpu(il->status) & 0xFFFF;
1808
1809 unsigned char event = xferstatus & 0x1F;
1810
1811 if (!event) {
1812 /* this packet hasn't come in yet; we are done for now */
1813 goto out;
1814 }
1815
1816 if (event == 0x11) {
1817 /* packet received successfully! */
1818
1819 /* rescount is the number of bytes *remaining* in the packet buffer,
1820 after the packet was written */
1821 packet_len = recv->buf_stride - rescount;
1822
1823 } else if (event == 0x02) {
1824 PRINT(KERN_ERR, "IR DMA error - packet too long for buffer\n");
1825 } else if (event) {
1826 PRINT(KERN_ERR, "IR DMA error - OHCI error code 0x%02x\n", event);
1827 }
1828
1829 /* sync our view of the buffer */
1830 dma_region_sync_for_cpu(&iso->data_buf, iso->pkt_dma * recv->buf_stride, recv->buf_stride);
1831
1832 /* record the per-packet info */
1833 {
1834 /* iso header is 8 bytes ahead of the data payload */
1835 unsigned char *hdr;
1836
1837 unsigned int offset;
1838 unsigned short cycle;
1839 unsigned char channel, tag, sy;
1840
1841 offset = iso->pkt_dma * recv->buf_stride;
1842 hdr = iso->data_buf.kvirt + offset;
1843
1844 /* skip iso header */
1845 offset += 8;
1846 packet_len -= 8;
1847
1848 cycle = (hdr[0] | (hdr[1] << 8)) & 0x1FFF;
1849 channel = hdr[5] & 0x3F;
1850 tag = hdr[5] >> 6;
1851 sy = hdr[4] & 0xF;
1852
1853 hpsb_iso_packet_received(iso, offset, packet_len, cycle, channel, tag, sy);
1854 }
1855
1856 /* reset the DMA descriptor */
1857 il->status = recv->buf_stride;
1858
1859 wake = 1;
1860 recv->block_dma = iso->pkt_dma;
1861 }
1862
1863 out:
1864 if (wake)
1865 hpsb_iso_wake(iso);
1866 }
1867
1868 static void ohci_iso_recv_task(unsigned long data)
1869 {
1870 struct hpsb_iso *iso = (struct hpsb_iso*) data;
1871 struct ohci_iso_recv *recv = iso->hostdata;
1872
1873 if (recv->dma_mode == BUFFER_FILL_MODE)
1874 ohci_iso_recv_bufferfill_task(iso, recv);
1875 else
1876 ohci_iso_recv_packetperbuf_task(iso, recv);
1877 }
1878
1879 /***********************************
1880 * rawiso ISO transmission *
1881 ***********************************/
1882
1883 struct ohci_iso_xmit {
1884 struct ti_ohci *ohci;
1885 struct dma_prog_region prog;
1886 struct ohci1394_iso_tasklet task;
1887 int task_active;
1888
1889 u32 ContextControlSet;
1890 u32 ContextControlClear;
1891 u32 CommandPtr;
1892 };
1893
1894 /* transmission DMA program:
1895 one OUTPUT_MORE_IMMEDIATE for the IT header
1896 one OUTPUT_LAST for the buffer data */
1897
1898 struct iso_xmit_cmd {
1899 struct dma_cmd output_more_immediate;
1900 u8 iso_hdr[8];
1901 u32 unused[2];
1902 struct dma_cmd output_last;
1903 };
1904
1905 static int ohci_iso_xmit_init(struct hpsb_iso *iso);
1906 static int ohci_iso_xmit_start(struct hpsb_iso *iso, int cycle);
1907 static void ohci_iso_xmit_shutdown(struct hpsb_iso *iso);
1908 static void ohci_iso_xmit_task(unsigned long data);
1909
1910 static int ohci_iso_xmit_init(struct hpsb_iso *iso)
1911 {
1912 struct ohci_iso_xmit *xmit;
1913 unsigned int prog_size;
1914 int ctx;
1915 int ret = -ENOMEM;
1916
1917 xmit = kmalloc(sizeof(*xmit), SLAB_KERNEL);
1918 if (!xmit)
1919 return -ENOMEM;
1920
1921 iso->hostdata = xmit;
1922 xmit->ohci = iso->host->hostdata;
1923 xmit->task_active = 0;
1924
1925 dma_prog_region_init(&xmit->prog);
1926
1927 prog_size = sizeof(struct iso_xmit_cmd) * iso->buf_packets;
1928
1929 if (dma_prog_region_alloc(&xmit->prog, prog_size, xmit->ohci->dev))
1930 goto err;
1931
1932 ohci1394_init_iso_tasklet(&xmit->task, OHCI_ISO_TRANSMIT,
1933 ohci_iso_xmit_task, (unsigned long) iso);
1934
1935 if (ohci1394_register_iso_tasklet(xmit->ohci, &xmit->task) < 0) {
1936 ret = -EBUSY;
1937 goto err;
1938 }
1939
1940 xmit->task_active = 1;
1941
1942 /* xmit context registers are spaced 16 bytes apart */
1943 ctx = xmit->task.context;
1944 xmit->ContextControlSet = OHCI1394_IsoXmitContextControlSet + 16 * ctx;
1945 xmit->ContextControlClear = OHCI1394_IsoXmitContextControlClear + 16 * ctx;
1946 xmit->CommandPtr = OHCI1394_IsoXmitCommandPtr + 16 * ctx;
1947
1948 return 0;
1949
1950 err:
1951 ohci_iso_xmit_shutdown(iso);
1952 return ret;
1953 }
1954
1955 static void ohci_iso_xmit_stop(struct hpsb_iso *iso)
1956 {
1957 struct ohci_iso_xmit *xmit = iso->hostdata;
1958 struct ti_ohci *ohci = xmit->ohci;
1959
1960 /* disable interrupts */
1961 reg_write(xmit->ohci, OHCI1394_IsoXmitIntMaskClear, 1 << xmit->task.context);
1962
1963 /* halt DMA */
1964 if (ohci1394_stop_context(xmit->ohci, xmit->ContextControlClear, NULL)) {
1965 /* XXX the DMA context will lock up if you try to send too much data! */
1966 PRINT(KERN_ERR,
1967 "you probably exceeded the OHCI card's bandwidth limit - "
1968 "reload the module and reduce xmit bandwidth");
1969 }
1970 }
1971
1972 static void ohci_iso_xmit_shutdown(struct hpsb_iso *iso)
1973 {
1974 struct ohci_iso_xmit *xmit = iso->hostdata;
1975
1976 if (xmit->task_active) {
1977 ohci_iso_xmit_stop(iso);
1978 ohci1394_unregister_iso_tasklet(xmit->ohci, &xmit->task);
1979 xmit->task_active = 0;
1980 }
1981
1982 dma_prog_region_free(&xmit->prog);
1983 kfree(xmit);
1984 iso->hostdata = NULL;
1985 }
1986
1987 static void ohci_iso_xmit_task(unsigned long data)
1988 {
1989 struct hpsb_iso *iso = (struct hpsb_iso*) data;
1990 struct ohci_iso_xmit *xmit = iso->hostdata;
1991 struct ti_ohci *ohci = xmit->ohci;
1992 int wake = 0;
1993 int count;
1994
1995 /* check the whole buffer if necessary, starting at pkt_dma */
1996 for (count = 0; count < iso->buf_packets; count++) {
1997 int cycle;
1998
1999 /* DMA descriptor */
2000 struct iso_xmit_cmd *cmd = dma_region_i(&xmit->prog, struct iso_xmit_cmd, iso->pkt_dma);
2001
2002 /* check for new writes to xferStatus */
2003 u16 xferstatus = le32_to_cpu(cmd->output_last.status) >> 16;
2004 u8 event = xferstatus & 0x1F;
2005
2006 if (!event) {
2007 /* packet hasn't been sent yet; we are done for now */
2008 break;
2009 }
2010
2011 if (event != 0x11)
2012 PRINT(KERN_ERR,
2013 "IT DMA error - OHCI error code 0x%02x\n", event);
2014
2015 /* at least one packet went out, so wake up the writer */
2016 wake = 1;
2017
2018 /* parse cycle */
2019 cycle = le32_to_cpu(cmd->output_last.status) & 0x1FFF;
2020
2021 /* tell the subsystem the packet has gone out */
2022 hpsb_iso_packet_sent(iso, cycle, event != 0x11);
2023
2024 /* reset the DMA descriptor for next time */
2025 cmd->output_last.status = 0;
2026 }
2027
2028 if (wake)
2029 hpsb_iso_wake(iso);
2030 }
2031
2032 static int ohci_iso_xmit_queue(struct hpsb_iso *iso, struct hpsb_iso_packet_info *info)
2033 {
2034 struct ohci_iso_xmit *xmit = iso->hostdata;
2035 struct ti_ohci *ohci = xmit->ohci;
2036
2037 int next_i, prev_i;
2038 struct iso_xmit_cmd *next, *prev;
2039
2040 unsigned int offset;
2041 unsigned short len;
2042 unsigned char tag, sy;
2043
2044 /* check that the packet doesn't cross a page boundary
2045 (we could allow this if we added OUTPUT_MORE descriptor support) */
2046 if (cross_bound(info->offset, info->len)) {
2047 PRINT(KERN_ERR,
2048 "rawiso xmit: packet %u crosses a page boundary",
2049 iso->first_packet);
2050 return -EINVAL;
2051 }
2052
2053 offset = info->offset;
2054 len = info->len;
2055 tag = info->tag;
2056 sy = info->sy;
2057
2058 /* sync up the card's view of the buffer */
2059 dma_region_sync_for_device(&iso->data_buf, offset, len);
2060
2061 /* append first_packet to the DMA chain */
2062 /* by linking the previous descriptor to it */
2063 /* (next will become the new end of the DMA chain) */
2064
2065 next_i = iso->first_packet;
2066 prev_i = (next_i == 0) ? (iso->buf_packets - 1) : (next_i - 1);
2067
2068 next = dma_region_i(&xmit->prog, struct iso_xmit_cmd, next_i);
2069 prev = dma_region_i(&xmit->prog, struct iso_xmit_cmd, prev_i);
2070
2071 /* set up the OUTPUT_MORE_IMMEDIATE descriptor */
2072 memset(next, 0, sizeof(struct iso_xmit_cmd));
2073 next->output_more_immediate.control = cpu_to_le32(0x02000008);
2074
2075 /* ISO packet header is embedded in the OUTPUT_MORE_IMMEDIATE */
2076
2077 /* tcode = 0xA, and sy */
2078 next->iso_hdr[0] = 0xA0 | (sy & 0xF);
2079
2080 /* tag and channel number */
2081 next->iso_hdr[1] = (tag << 6) | (iso->channel & 0x3F);
2082
2083 /* transmission speed */
2084 next->iso_hdr[2] = iso->speed & 0x7;
2085
2086 /* payload size */
2087 next->iso_hdr[6] = len & 0xFF;
2088 next->iso_hdr[7] = len >> 8;
2089
2090 /* set up the OUTPUT_LAST */
2091 next->output_last.control = cpu_to_le32(1 << 28);
2092 next->output_last.control |= cpu_to_le32(1 << 27); /* update timeStamp */
2093 next->output_last.control |= cpu_to_le32(3 << 20); /* want interrupt */
2094 next->output_last.control |= cpu_to_le32(3 << 18); /* enable branch */
2095 next->output_last.control |= cpu_to_le32(len);
2096
2097 /* payload bus address */
2098 next->output_last.address = cpu_to_le32(dma_region_offset_to_bus(&iso->data_buf, offset));
2099
2100 /* leave branchAddress at zero for now */
2101
2102 /* re-write the previous DMA descriptor to chain to this one */
2103
2104 /* set prev branch address to point to next (Z=3) */
2105 prev->output_last.branchAddress = cpu_to_le32(
2106 dma_prog_region_offset_to_bus(&xmit->prog, sizeof(struct iso_xmit_cmd) * next_i) | 3);
2107
2108 /* disable interrupt, unless required by the IRQ interval */
2109 if (prev_i % iso->irq_interval) {
2110 prev->output_last.control &= cpu_to_le32(~(3 << 20)); /* no interrupt */
2111 } else {
2112 prev->output_last.control |= cpu_to_le32(3 << 20); /* enable interrupt */
2113 }
2114
2115 wmb();
2116
2117 /* wake DMA in case it is sleeping */
2118 reg_write(xmit->ohci, xmit->ContextControlSet, 1 << 12);
2119
2120 /* issue a dummy read of the cycle timer to force all PCI
2121 writes to be posted immediately */
2122 mb();
2123 reg_read(xmit->ohci, OHCI1394_IsochronousCycleTimer);
2124
2125 return 0;
2126 }
2127
2128 static int ohci_iso_xmit_start(struct hpsb_iso *iso, int cycle)
2129 {
2130 struct ohci_iso_xmit *xmit = iso->hostdata;
2131 struct ti_ohci *ohci = xmit->ohci;
2132
2133 /* clear out the control register */
2134 reg_write(xmit->ohci, xmit->ContextControlClear, 0xFFFFFFFF);
2135 wmb();
2136
2137 /* address and length of first descriptor block (Z=3) */
2138 reg_write(xmit->ohci, xmit->CommandPtr,
2139 dma_prog_region_offset_to_bus(&xmit->prog, iso->pkt_dma * sizeof(struct iso_xmit_cmd)) | 3);
2140
2141 /* cycle match */
2142 if (cycle != -1) {
2143 u32 start = cycle & 0x1FFF;
2144
2145 /* 'cycle' is only mod 8000, but we also need two 'seconds' bits -
2146 just snarf them from the current time */
2147 u32 seconds = reg_read(xmit->ohci, OHCI1394_IsochronousCycleTimer) >> 25;
2148
2149 /* advance one second to give some extra time for DMA to start */
2150 seconds += 1;
2151
2152 start |= (seconds & 3) << 13;
2153
2154 reg_write(xmit->ohci, xmit->ContextControlSet, 0x80000000 | (start << 16));
2155 }
2156
2157 /* enable interrupts */
2158 reg_write(xmit->ohci, OHCI1394_IsoXmitIntMaskSet, 1 << xmit->task.context);
2159
2160 /* run */
2161 reg_write(xmit->ohci, xmit->ContextControlSet, 0x8000);
2162 mb();
2163
2164 /* wait 100 usec to give the card time to go active */
2165 udelay(100);
2166
2167 /* check the RUN bit */
2168 if (!(reg_read(xmit->ohci, xmit->ContextControlSet) & 0x8000)) {
2169 PRINT(KERN_ERR, "Error starting IT DMA (ContextControl 0x%08x)\n",
2170 reg_read(xmit->ohci, xmit->ContextControlSet));
2171 return -1;
2172 }
2173
2174 return 0;
2175 }
2176
2177 static int ohci_isoctl(struct hpsb_iso *iso, enum isoctl_cmd cmd, unsigned long arg)
2178 {
2179
2180 switch(cmd) {
2181 case XMIT_INIT:
2182 return ohci_iso_xmit_init(iso);
2183 case XMIT_START:
2184 return ohci_iso_xmit_start(iso, arg);
2185 case XMIT_STOP:
2186 ohci_iso_xmit_stop(iso);
2187 return 0;
2188 case XMIT_QUEUE:
2189 return ohci_iso_xmit_queue(iso, (struct hpsb_iso_packet_info*) arg);
2190 case XMIT_SHUTDOWN:
2191 ohci_iso_xmit_shutdown(iso);
2192 return 0;
2193
2194 case RECV_INIT:
2195 return ohci_iso_recv_init(iso);
2196 case RECV_START: {
2197 int *args = (int*) arg;
2198 return ohci_iso_recv_start(iso, args[0], args[1], args[2]);
2199 }
2200 case RECV_STOP:
2201 ohci_iso_recv_stop(iso);
2202 return 0;
2203 case RECV_RELEASE:
2204 ohci_iso_recv_release(iso, (struct hpsb_iso_packet_info*) arg);
2205 return 0;
2206 case RECV_FLUSH:
2207 ohci_iso_recv_task((unsigned long) iso);
2208 return 0;
2209 case RECV_SHUTDOWN:
2210 ohci_iso_recv_shutdown(iso);
2211 return 0;
2212 case RECV_LISTEN_CHANNEL:
2213 ohci_iso_recv_change_channel(iso, arg, 1);
2214 return 0;
2215 case RECV_UNLISTEN_CHANNEL:
2216 ohci_iso_recv_change_channel(iso, arg, 0);
2217 return 0;
2218 case RECV_SET_CHANNEL_MASK:
2219 ohci_iso_recv_set_channel_mask(iso, *((u64*) arg));
2220 return 0;
2221
2222 default:
2223 PRINT_G(KERN_ERR, "ohci_isoctl cmd %d not implemented yet",
2224 cmd);
2225 break;
2226 }
2227 return -EINVAL;
2228 }
2229
2230 /***************************************
2231 * IEEE-1394 functionality section END *
2232 ***************************************/
2233
2234
2235 /********************************************************
2236 * Global stuff (interrupt handler, init/shutdown code) *
2237 ********************************************************/
2238
2239 static void dma_trm_reset(struct dma_trm_ctx *d)
2240 {
2241 unsigned long flags;
2242 LIST_HEAD(packet_list);
2243 struct ti_ohci *ohci = d->ohci;
2244 struct hpsb_packet *packet, *ptmp;
2245
2246 ohci1394_stop_context(ohci, d->ctrlClear, NULL);
2247
2248 /* Lock the context, reset it and release it. Move the packets
2249 * that were pending in the context to packet_list and free
2250 * them after releasing the lock. */
2251
2252 spin_lock_irqsave(&d->lock, flags);
2253
2254 list_splice(&d->fifo_list, &packet_list);
2255 list_splice(&d->pending_list, &packet_list);
2256 INIT_LIST_HEAD(&d->fifo_list);
2257 INIT_LIST_HEAD(&d->pending_list);
2258
2259 d->branchAddrPtr = NULL;
2260 d->sent_ind = d->prg_ind;
2261 d->free_prgs = d->num_desc;
2262
2263 spin_unlock_irqrestore(&d->lock, flags);
2264
2265 if (list_empty(&packet_list))
2266 return;
2267
2268 PRINT(KERN_INFO, "AT dma reset ctx=%d, aborting transmission", d->ctx);
2269
2270 /* Now process subsystem callbacks for the packets from this
2271 * context. */
2272 list_for_each_entry_safe(packet, ptmp, &packet_list, driver_list) {
2273 list_del_init(&packet->driver_list);
2274 hpsb_packet_sent(ohci->host, packet, ACKX_ABORTED);
2275 }
2276 }
2277
2278 static void ohci_schedule_iso_tasklets(struct ti_ohci *ohci,
2279 quadlet_t rx_event,
2280 quadlet_t tx_event)
2281 {
2282 struct ohci1394_iso_tasklet *t;
2283 unsigned long mask;
2284
2285 spin_lock(&ohci->iso_tasklet_list_lock);
2286
2287 list_for_each_entry(t, &ohci->iso_tasklet_list, link) {
2288 mask = 1 << t->context;
2289
2290 if (t->type == OHCI_ISO_TRANSMIT && tx_event & mask)
2291 tasklet_schedule(&t->tasklet);
2292 else if (rx_event & mask)
2293 tasklet_schedule(&t->tasklet);
2294 }
2295
2296 spin_unlock(&ohci->iso_tasklet_list_lock);
2297
2298 }
2299
2300 static irqreturn_t ohci_irq_handler(int irq, void *dev_id,
2301 struct pt_regs *regs_are_unused)
2302 {
2303 quadlet_t event, node_id;
2304 struct ti_ohci *ohci = (struct ti_ohci *)dev_id;
2305 struct hpsb_host *host = ohci->host;
2306 int phyid = -1, isroot = 0;
2307 unsigned long flags;
2308
2309 /* Read and clear the interrupt event register. Don't clear
2310 * the busReset event, though. This is done when we get the
2311 * selfIDComplete interrupt. */
2312 spin_lock_irqsave(&ohci->event_lock, flags);
2313 event = reg_read(ohci, OHCI1394_IntEventClear);
2314 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
2315 spin_unlock_irqrestore(&ohci->event_lock, flags);
2316
2317 if (!event)
2318 return IRQ_NONE;
2319
2320 /* If event is ~(u32)0 cardbus card was ejected. In this case
2321 * we just return, and clean up in the ohci1394_pci_remove
2322 * function. */
2323 if (event == ~(u32) 0) {
2324 DBGMSG("Device removed.");
2325 return IRQ_NONE;
2326 }
2327
2328 DBGMSG("IntEvent: %08x", event);
2329
2330 if (event & OHCI1394_unrecoverableError) {
2331 int ctx;
2332 PRINT(KERN_ERR, "Unrecoverable error!");
2333
2334 if (reg_read(ohci, OHCI1394_AsReqTrContextControlSet) & 0x800)
2335 PRINT(KERN_ERR, "Async Req Tx Context died: "
2336 "ctrl[%08x] cmdptr[%08x]",
2337 reg_read(ohci, OHCI1394_AsReqTrContextControlSet),
2338 reg_read(ohci, OHCI1394_AsReqTrCommandPtr));
2339
2340 if (reg_read(ohci, OHCI1394_AsRspTrContextControlSet) & 0x800)
2341 PRINT(KERN_ERR, "Async Rsp Tx Context died: "
2342 "ctrl[%08x] cmdptr[%08x]",
2343 reg_read(ohci, OHCI1394_AsRspTrContextControlSet),
2344 reg_read(ohci, OHCI1394_AsRspTrCommandPtr));
2345
2346 if (reg_read(ohci, OHCI1394_AsReqRcvContextControlSet) & 0x800)
2347 PRINT(KERN_ERR, "Async Req Rcv Context died: "
2348 "ctrl[%08x] cmdptr[%08x]",
2349 reg_read(ohci, OHCI1394_AsReqRcvContextControlSet),
2350 reg_read(ohci, OHCI1394_AsReqRcvCommandPtr));
2351
2352 if (reg_read(ohci, OHCI1394_AsRspRcvContextControlSet) & 0x800)
2353 PRINT(KERN_ERR, "Async Rsp Rcv Context died: "
2354 "ctrl[%08x] cmdptr[%08x]",
2355 reg_read(ohci, OHCI1394_AsRspRcvContextControlSet),
2356 reg_read(ohci, OHCI1394_AsRspRcvCommandPtr));
2357
2358 for (ctx = 0; ctx < ohci->nb_iso_xmit_ctx; ctx++) {
2359 if (reg_read(ohci, OHCI1394_IsoXmitContextControlSet + (16 * ctx)) & 0x800)
2360 PRINT(KERN_ERR, "Iso Xmit %d Context died: "
2361 "ctrl[%08x] cmdptr[%08x]", ctx,
2362 reg_read(ohci, OHCI1394_IsoXmitContextControlSet + (16 * ctx)),
2363 reg_read(ohci, OHCI1394_IsoXmitCommandPtr + (16 * ctx)));
2364 }
2365
2366 for (ctx = 0; ctx < ohci->nb_iso_rcv_ctx; ctx++) {
2367 if (reg_read(ohci, OHCI1394_IsoRcvContextControlSet + (32 * ctx)) & 0x800)
2368 PRINT(KERN_ERR, "Iso Recv %d Context died: "
2369 "ctrl[%08x] cmdptr[%08x] match[%08x]", ctx,
2370 reg_read(ohci, OHCI1394_IsoRcvContextControlSet + (32 * ctx)),
2371 reg_read(ohci, OHCI1394_IsoRcvCommandPtr + (32 * ctx)),
2372 reg_read(ohci, OHCI1394_IsoRcvContextMatch + (32 * ctx)));
2373 }
2374
2375 event &= ~OHCI1394_unrecoverableError;
2376 }
2377
2378 if (event & OHCI1394_cycleInconsistent) {
2379 /* We subscribe to the cycleInconsistent event only to
2380 * clear the corresponding event bit... otherwise,
2381 * isochronous cycleMatch DMA won't work. */
2382 DBGMSG("OHCI1394_cycleInconsistent");
2383 event &= ~OHCI1394_cycleInconsistent;
2384 }
2385
2386 if (event & OHCI1394_busReset) {
2387 /* The busReset event bit can't be cleared during the
2388 * selfID phase, so we disable busReset interrupts, to
2389 * avoid burying the cpu in interrupt requests. */
2390 spin_lock_irqsave(&ohci->event_lock, flags);
2391 reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_busReset);
2392
2393 if (ohci->check_busreset) {
2394 int loop_count = 0;
2395
2396 udelay(10);
2397
2398 while (reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
2399 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2400
2401 spin_unlock_irqrestore(&ohci->event_lock, flags);
2402 udelay(10);
2403 spin_lock_irqsave(&ohci->event_lock, flags);
2404
2405 /* The loop counter check is to prevent the driver
2406 * from remaining in this state forever. For the
2407 * initial bus reset, the loop continues for ever
2408 * and the system hangs, until some device is plugged-in
2409 * or out manually into a port! The forced reset seems
2410 * to solve this problem. This mainly effects nForce2. */
2411 if (loop_count > 10000) {
2412 ohci_devctl(host, RESET_BUS, LONG_RESET);
2413 DBGMSG("Detected bus-reset loop. Forced a bus reset!");
2414 loop_count = 0;
2415 }
2416
2417 loop_count++;
2418 }
2419 }
2420 spin_unlock_irqrestore(&ohci->event_lock, flags);
2421 if (!host->in_bus_reset) {
2422 DBGMSG("irq_handler: Bus reset requested");
2423
2424 /* Subsystem call */
2425 hpsb_bus_reset(ohci->host);
2426 }
2427 event &= ~OHCI1394_busReset;
2428 }
2429
2430 if (event & OHCI1394_reqTxComplete) {
2431 struct dma_trm_ctx *d = &ohci->at_req_context;
2432 DBGMSG("Got reqTxComplete interrupt "
2433 "status=0x%08X", reg_read(ohci, d->ctrlSet));
2434 if (reg_read(ohci, d->ctrlSet) & 0x800)
2435 ohci1394_stop_context(ohci, d->ctrlClear,
2436 "reqTxComplete");
2437 else
2438 dma_trm_tasklet((unsigned long)d);
2439 //tasklet_schedule(&d->task);
2440 event &= ~OHCI1394_reqTxComplete;
2441 }
2442 if (event & OHCI1394_respTxComplete) {
2443 struct dma_trm_ctx *d = &ohci->at_resp_context;
2444 DBGMSG("Got respTxComplete interrupt "
2445 "status=0x%08X", reg_read(ohci, d->ctrlSet));
2446 if (reg_read(ohci, d->ctrlSet) & 0x800)
2447 ohci1394_stop_context(ohci, d->ctrlClear,
2448 "respTxComplete");
2449 else
2450 tasklet_schedule(&d->task);
2451 event &= ~OHCI1394_respTxComplete;
2452 }
2453 if (event & OHCI1394_RQPkt) {
2454 struct dma_rcv_ctx *d = &ohci->ar_req_context;
2455 DBGMSG("Got RQPkt interrupt status=0x%08X",
2456 reg_read(ohci, d->ctrlSet));
2457 if (reg_read(ohci, d->ctrlSet) & 0x800)
2458 ohci1394_stop_context(ohci, d->ctrlClear, "RQPkt");
2459 else
2460 tasklet_schedule(&d->task);
2461 event &= ~OHCI1394_RQPkt;
2462 }
2463 if (event & OHCI1394_RSPkt) {
2464 struct dma_rcv_ctx *d = &ohci->ar_resp_context;
2465 DBGMSG("Got RSPkt interrupt status=0x%08X",
2466 reg_read(ohci, d->ctrlSet));
2467 if (reg_read(ohci, d->ctrlSet) & 0x800)
2468 ohci1394_stop_context(ohci, d->ctrlClear, "RSPkt");
2469 else
2470 tasklet_schedule(&d->task);
2471 event &= ~OHCI1394_RSPkt;
2472 }
2473 if (event & OHCI1394_isochRx) {
2474 quadlet_t rx_event;
2475
2476 rx_event = reg_read(ohci, OHCI1394_IsoRecvIntEventSet);
2477 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, rx_event);
2478 ohci_schedule_iso_tasklets(ohci, rx_event, 0);
2479 event &= ~OHCI1394_isochRx;
2480 }
2481 if (event & OHCI1394_isochTx) {
2482 quadlet_t tx_event;
2483
2484 tx_event = reg_read(ohci, OHCI1394_IsoXmitIntEventSet);
2485 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, tx_event);
2486 ohci_schedule_iso_tasklets(ohci, 0, tx_event);
2487 event &= ~OHCI1394_isochTx;
2488 }
2489 if (event & OHCI1394_selfIDComplete) {
2490 if (host->in_bus_reset) {
2491 node_id = reg_read(ohci, OHCI1394_NodeID);
2492
2493 if (!(node_id & 0x80000000)) {
2494 PRINT(KERN_ERR,
2495 "SelfID received, but NodeID invalid "
2496 "(probably new bus reset occurred): %08X",
2497 node_id);
2498 goto selfid_not_valid;
2499 }
2500
2501 phyid = node_id & 0x0000003f;
2502 isroot = (node_id & 0x40000000) != 0;
2503
2504 DBGMSG("SelfID interrupt received "
2505 "(phyid %d, %s)", phyid,
2506 (isroot ? "root" : "not root"));
2507
2508 handle_selfid(ohci, host, phyid, isroot);
2509
2510 /* Clear the bus reset event and re-enable the
2511 * busReset interrupt. */
2512 spin_lock_irqsave(&ohci->event_lock, flags);
2513 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2514 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
2515 spin_unlock_irqrestore(&ohci->event_lock, flags);
2516
2517 /* Accept Physical requests from all nodes. */
2518 reg_write(ohci,OHCI1394_AsReqFilterHiSet, 0xffffffff);
2519 reg_write(ohci,OHCI1394_AsReqFilterLoSet, 0xffffffff);
2520
2521 /* Turn on phys dma reception.
2522 *
2523 * TODO: Enable some sort of filtering management.
2524 */
2525 if (phys_dma) {
2526 reg_write(ohci,OHCI1394_PhyReqFilterHiSet, 0xffffffff);
2527 reg_write(ohci,OHCI1394_PhyReqFilterLoSet, 0xffffffff);
2528 reg_write(ohci,OHCI1394_PhyUpperBound, 0xffff0000);
2529 } else {
2530 reg_write(ohci,OHCI1394_PhyReqFilterHiSet, 0x00000000);
2531 reg_write(ohci,OHCI1394_PhyReqFilterLoSet, 0x00000000);
2532 }
2533
2534 DBGMSG("PhyReqFilter=%08x%08x",
2535 reg_read(ohci,OHCI1394_PhyReqFilterHiSet),
2536 reg_read(ohci,OHCI1394_PhyReqFilterLoSet));
2537
2538 hpsb_selfid_complete(host, phyid, isroot);
2539 } else
2540 PRINT(KERN_ERR,
2541 "SelfID received outside of bus reset sequence");
2542
2543 selfid_not_valid:
2544 event &= ~OHCI1394_selfIDComplete;
2545 }
2546
2547 /* Make sure we handle everything, just in case we accidentally
2548 * enabled an interrupt that we didn't write a handler for. */
2549 if (event)
2550 PRINT(KERN_ERR, "Unhandled interrupt(s) 0x%08x",
2551 event);
2552
2553 return IRQ_HANDLED;
2554 }
2555
2556 /* Put the buffer back into the dma context */
2557 static void insert_dma_buffer(struct dma_rcv_ctx *d, int idx)
2558 {
2559 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
2560 DBGMSG("Inserting dma buf ctx=%d idx=%d", d->ctx, idx);
2561
2562 d->prg_cpu[idx]->status = cpu_to_le32(d->buf_size);
2563 d->prg_cpu[idx]->branchAddress &= le32_to_cpu(0xfffffff0);
2564 idx = (idx + d->num_desc - 1 ) % d->num_desc;
2565 d->prg_cpu[idx]->branchAddress |= le32_to_cpu(0x00000001);
2566
2567 /* To avoid a race, ensure 1394 interface hardware sees the inserted
2568 * context program descriptors before it sees the wakeup bit set. */
2569 wmb();
2570
2571 /* wake up the dma context if necessary */
2572 if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
2573 PRINT(KERN_INFO,
2574 "Waking dma ctx=%d ... processing is probably too slow",
2575 d->ctx);
2576 }
2577
2578 /* do this always, to avoid race condition */
2579 reg_write(ohci, d->ctrlSet, 0x1000);
2580 }
2581
2582 #define cond_le32_to_cpu(data, noswap) \
2583 (noswap ? data : le32_to_cpu(data))
2584
2585 static const int TCODE_SIZE[16] = {20, 0, 16, -1, 16, 20, 20, 0,
2586 -1, 0, -1, 0, -1, -1, 16, -1};
2587
2588 /*
2589 * Determine the length of a packet in the buffer
2590 * Optimization suggested by Pascal Drolet <pascal.drolet@informission.ca>
2591 */
2592 static __inline__ int packet_length(struct dma_rcv_ctx *d, int idx, quadlet_t *buf_ptr,
2593 int offset, unsigned char tcode, int noswap)
2594 {
2595 int length = -1;
2596
2597 if (d->type == DMA_CTX_ASYNC_REQ || d->type == DMA_CTX_ASYNC_RESP) {
2598 length = TCODE_SIZE[tcode];
2599 if (length == 0) {
2600 if (offset + 12 >= d->buf_size) {
2601 length = (cond_le32_to_cpu(d->buf_cpu[(idx + 1) % d->num_desc]
2602 [3 - ((d->buf_size - offset) >> 2)], noswap) >> 16);
2603 } else {
2604 length = (cond_le32_to_cpu(buf_ptr[3], noswap) >> 16);
2605 }
2606 length += 20;
2607 }
2608 } else if (d->type == DMA_CTX_ISO) {
2609 /* Assumption: buffer fill mode with header/trailer */
2610 length = (cond_le32_to_cpu(buf_ptr[0], noswap) >> 16) + 8;
2611 }
2612
2613 if (length > 0 && length % 4)
2614 length += 4 - (length % 4);
2615
2616 return length;
2617 }
2618
2619 /* Tasklet that processes dma receive buffers */
2620 static void dma_rcv_tasklet (unsigned long data)
2621 {
2622 struct dma_rcv_ctx *d = (struct dma_rcv_ctx*)data;
2623 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
2624 unsigned int split_left, idx, offset, rescount;
2625 unsigned char tcode;
2626 int length, bytes_left, ack;
2627 unsigned long flags;
2628 quadlet_t *buf_ptr;
2629 char *split_ptr;
2630 char msg[256];
2631
2632 spin_lock_irqsave(&d->lock, flags);
2633
2634 idx = d->buf_ind;
2635 offset = d->buf_offset;
2636 buf_ptr = d->buf_cpu[idx] + offset/4;
2637
2638 rescount = le32_to_cpu(d->prg_cpu[idx]->status) & 0xffff;
2639 bytes_left = d->buf_size - rescount - offset;
2640
2641 while (bytes_left > 0) {
2642 tcode = (cond_le32_to_cpu(buf_ptr[0], ohci->no_swap_incoming) >> 4) & 0xf;
2643
2644 /* packet_length() will return < 4 for an error */
2645 length = packet_length(d, idx, buf_ptr, offset, tcode, ohci->no_swap_incoming);
2646
2647 if (length < 4) { /* something is wrong */
2648 sprintf(msg,"Unexpected tcode 0x%x(0x%08x) in AR ctx=%d, length=%d",
2649 tcode, cond_le32_to_cpu(buf_ptr[0], ohci->no_swap_incoming),
2650 d->ctx, length);
2651 ohci1394_stop_context(ohci, d->ctrlClear, msg);
2652 spin_unlock_irqrestore(&d->lock, flags);
2653 return;
2654 }
2655
2656 /* The first case is where we have a packet that crosses
2657 * over more than one descriptor. The next case is where
2658 * it's all in the first descriptor. */
2659 if ((offset + length) > d->buf_size) {
2660 DBGMSG("Split packet rcv'd");
2661 if (length > d->split_buf_size) {
2662 ohci1394_stop_context(ohci, d->ctrlClear,
2663 "Split packet size exceeded");
2664 d->buf_ind = idx;
2665 d->buf_offset = offset;
2666 spin_unlock_irqrestore(&d->lock, flags);
2667 return;
2668 }
2669
2670 if (le32_to_cpu(d->prg_cpu[(idx+1)%d->num_desc]->status)
2671 == d->buf_size) {
2672 /* Other part of packet not written yet.
2673 * this should never happen I think
2674 * anyway we'll get it on the next call. */
2675 PRINT(KERN_INFO,
2676 "Got only half a packet!");
2677 d->buf_ind = idx;
2678 d->buf_offset = offset;
2679 spin_unlock_irqrestore(&d->lock, flags);
2680 return;
2681 }
2682
2683 split_left = length;
2684 split_ptr = (char *)d->spb;
2685 memcpy(split_ptr,buf_ptr,d->buf_size-offset);
2686 split_left -= d->buf_size-offset;
2687 split_ptr += d->buf_size-offset;
2688 insert_dma_buffer(d, idx);
2689 idx = (idx+1) % d->num_desc;
2690 buf_ptr = d->buf_cpu[idx];
2691 offset=0;
2692
2693 while (split_left >= d->buf_size) {
2694 memcpy(split_ptr,buf_ptr,d->buf_size);
2695 split_ptr += d->buf_size;
2696 split_left -= d->buf_size;
2697 insert_dma_buffer(d, idx);
2698 idx = (idx+1) % d->num_desc;
2699 buf_ptr = d->buf_cpu[idx];
2700 }
2701
2702 if (split_left > 0) {
2703 memcpy(split_ptr, buf_ptr, split_left);
2704 offset = split_left;
2705 buf_ptr += offset/4;
2706 }
2707 } else {
2708 DBGMSG("Single packet rcv'd");
2709 memcpy(d->spb, buf_ptr, length);
2710 offset += length;
2711 buf_ptr += length/4;
2712 if (offset==d->buf_size) {
2713 insert_dma_buffer(d, idx);
2714 idx = (idx+1) % d->num_desc;
2715 buf_ptr = d->buf_cpu[idx];
2716 offset=0;
2717 }
2718 }
2719
2720 /* We get one phy packet to the async descriptor for each
2721 * bus reset. We always ignore it. */
2722 if (tcode != OHCI1394_TCODE_PHY) {
2723 if (!ohci->no_swap_incoming)
2724 packet_swab(d->spb, tcode);
2725 DBGMSG("Packet received from node"
2726 " %d ack=0x%02X spd=%d tcode=0x%X"
2727 " length=%d ctx=%d tlabel=%d",
2728 (d->spb[1]>>16)&0x3f,
2729 (cond_le32_to_cpu(d->spb[length/4-1], ohci->no_swap_incoming)>>16)&0x1f,
2730 (cond_le32_to_cpu(d->spb[length/4-1], ohci->no_swap_incoming)>>21)&0x3,
2731 tcode, length, d->ctx,
2732 (cond_le32_to_cpu(d->spb[0], ohci->no_swap_incoming)>>10)&0x3f);
2733
2734 ack = (((cond_le32_to_cpu(d->spb[length/4-1], ohci->no_swap_incoming)>>16)&0x1f)
2735 == 0x11) ? 1 : 0;
2736
2737 hpsb_packet_received(ohci->host, d->spb,
2738 length-4, ack);
2739 }
2740 #ifdef OHCI1394_DEBUG
2741 else
2742 PRINT (KERN_DEBUG, "Got phy packet ctx=%d ... discarded",
2743 d->ctx);
2744 #endif
2745
2746 rescount = le32_to_cpu(d->prg_cpu[idx]->status) & 0xffff;
2747
2748 bytes_left = d->buf_size - rescount - offset;
2749
2750 }
2751
2752 d->buf_ind = idx;
2753 d->buf_offset = offset;
2754
2755 spin_unlock_irqrestore(&d->lock, flags);
2756 }
2757
2758 /* Bottom half that processes sent packets */
2759 static void dma_trm_tasklet (unsigned long data)
2760 {
2761 struct dma_trm_ctx *d = (struct dma_trm_ctx*)data;
2762 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
2763 struct hpsb_packet *packet, *ptmp;
2764 unsigned long flags;
2765 u32 status, ack;
2766 size_t datasize;
2767
2768 spin_lock_irqsave(&d->lock, flags);
2769
2770 list_for_each_entry_safe(packet, ptmp, &d->fifo_list, driver_list) {
2771 datasize = packet->data_size;
2772 if (datasize && packet->type != hpsb_raw)
2773 status = le32_to_cpu(
2774 d->prg_cpu[d->sent_ind]->end.status) >> 16;
2775 else
2776 status = le32_to_cpu(
2777 d->prg_cpu[d->sent_ind]->begin.status) >> 16;
2778
2779 if (status == 0)
2780 /* this packet hasn't been sent yet*/
2781 break;
2782
2783 #ifdef OHCI1394_DEBUG
2784 if (datasize)
2785 if (((le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>4)&0xf) == 0xa)
2786 DBGMSG("Stream packet sent to channel %d tcode=0x%X "
2787 "ack=0x%X spd=%d dataLength=%d ctx=%d",
2788 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>8)&0x3f,
2789 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>4)&0xf,
2790 status&0x1f, (status>>5)&0x3,
2791 le32_to_cpu(d->prg_cpu[d->sent_ind]->data[1])>>16,
2792 d->ctx);
2793 else
2794 DBGMSG("Packet sent to node %d tcode=0x%X tLabel="
2795 "%d ack=0x%X spd=%d dataLength=%d ctx=%d",
2796 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[1])>>16)&0x3f,
2797 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>4)&0xf,
2798 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>10)&0x3f,
2799 status&0x1f, (status>>5)&0x3,
2800 le32_to_cpu(d->prg_cpu[d->sent_ind]->data[3])>>16,
2801 d->ctx);
2802 else
2803 DBGMSG("Packet sent to node %d tcode=0x%X tLabel="
2804 "%d ack=0x%X spd=%d data=0x%08X ctx=%d",
2805 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[1])
2806 >>16)&0x3f,
2807 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])
2808 >>4)&0xf,
2809 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])
2810 >>10)&0x3f,
2811 status&0x1f, (status>>5)&0x3,
2812 le32_to_cpu(d->prg_cpu[d->sent_ind]->data[3]),
2813 d->ctx);
2814 #endif
2815
2816 if (status & 0x10) {
2817 ack = status & 0xf;
2818 } else {
2819 switch (status & 0x1f) {
2820 case EVT_NO_STATUS: /* that should never happen */
2821 case EVT_RESERVED_A: /* that should never happen */
2822 case EVT_LONG_PACKET: /* that should never happen */
2823 PRINT(KERN_WARNING, "Received OHCI evt_* error 0x%x", status & 0x1f);
2824 ack = ACKX_SEND_ERROR;
2825 break;
2826 case EVT_MISSING_ACK:
2827 ack = ACKX_TIMEOUT;
2828 break;
2829 case EVT_UNDERRUN:
2830 ack = ACKX_SEND_ERROR;
2831 break;
2832 case EVT_OVERRUN: /* that should never happen */
2833 PRINT(KERN_WARNING, "Received OHCI evt_* error 0x%x", status & 0x1f);
2834 ack = ACKX_SEND_ERROR;
2835 break;
2836 case EVT_DESCRIPTOR_READ:
2837 case EVT_DATA_READ:
2838 case EVT_DATA_WRITE:
2839 ack = ACKX_SEND_ERROR;
2840 break;
2841 case EVT_BUS_RESET: /* that should never happen */
2842 PRINT(KERN_WARNING, "Received OHCI evt_* error 0x%x", status & 0x1f);
2843 ack = ACKX_SEND_ERROR;
2844 break;
2845 case EVT_TIMEOUT:
2846 ack = ACKX_TIMEOUT;
2847 break;
2848 case EVT_TCODE_ERR:
2849 ack = ACKX_SEND_ERROR;
2850 break;
2851 case EVT_RESERVED_B: /* that should never happen */
2852 case EVT_RESERVED_C: /* that should never happen */
2853 PRINT(KERN_WARNING, "Received OHCI evt_* error 0x%x", status & 0x1f);
2854 ack = ACKX_SEND_ERROR;
2855 break;
2856 case EVT_UNKNOWN:
2857 case EVT_FLUSHED:
2858 ack = ACKX_SEND_ERROR;
2859 break;
2860 default:
2861 PRINT(KERN_ERR, "Unhandled OHCI evt_* error 0x%x", status & 0x1f);
2862 ack = ACKX_SEND_ERROR;
2863 BUG();
2864 }
2865 }
2866
2867 list_del_init(&packet->driver_list);
2868 hpsb_packet_sent(ohci->host, packet, ack);
2869
2870 if (datasize) {
2871 pci_unmap_single(ohci->dev,
2872 cpu_to_le32(d->prg_cpu[d->sent_ind]->end.address),
2873 datasize, PCI_DMA_TODEVICE);
2874 OHCI_DMA_FREE("single Xmit data packet");
2875 }
2876
2877 d->sent_ind = (d->sent_ind+1)%d->num_desc;
2878 d->free_prgs++;
2879 }
2880
2881 dma_trm_flush(ohci, d);
2882
2883 spin_unlock_irqrestore(&d->lock, flags);
2884 }
2885
2886 static void stop_dma_rcv_ctx(struct dma_rcv_ctx *d)
2887 {
2888 if (d->ctrlClear) {
2889 ohci1394_stop_context(d->ohci, d->ctrlClear, NULL);
2890
2891 if (d->type == DMA_CTX_ISO) {
2892 /* disable interrupts */
2893 reg_write(d->ohci, OHCI1394_IsoRecvIntMaskClear, 1 << d->ctx);
2894 ohci1394_unregister_iso_tasklet(d->ohci, &d->ohci->ir_legacy_tasklet);
2895 } else {
2896 tasklet_kill(&d->task);
2897 }
2898 }
2899 }
2900
2901
2902 static void free_dma_rcv_ctx(struct dma_rcv_ctx *d)
2903 {
2904 int i;
2905 struct ti_ohci *ohci = d->ohci;
2906
2907 if (ohci == NULL)
2908 return;
2909
2910 DBGMSG("Freeing dma_rcv_ctx %d", d->ctx);
2911
2912 if (d->buf_cpu) {
2913 for (i=0; i<d->num_desc; i++)
2914 if (d->buf_cpu[i] && d->buf_bus[i]) {
2915 pci_free_consistent(
2916 ohci->dev, d->buf_size,
2917 d->buf_cpu[i], d->buf_bus[i]);
2918 OHCI_DMA_FREE("consistent dma_rcv buf[%d]", i);
2919 }
2920 kfree(d->buf_cpu);
2921 kfree(d->buf_bus);
2922 }
2923 if (d->prg_cpu) {
2924 for (i=0; i<d->num_desc; i++)
2925 if (d->prg_cpu[i] && d->prg_bus[i]) {
2926 pci_pool_free(d->prg_pool, d->prg_cpu[i], d->prg_bus[i]);
2927 OHCI_DMA_FREE("consistent dma_rcv prg[%d]", i);
2928 }
2929 pci_pool_destroy(d->prg_pool);
2930 OHCI_DMA_FREE("dma_rcv prg pool");
2931 kfree(d->prg_cpu);
2932 kfree(d->prg_bus);
2933 }
2934 kfree(d->spb);
2935
2936 /* Mark this context as freed. */
2937 d->ohci = NULL;
2938 }
2939
2940 static int
2941 alloc_dma_rcv_ctx(struct ti_ohci *ohci, struct dma_rcv_ctx *d,
2942 enum context_type type, int ctx, int num_desc,
2943 int buf_size, int split_buf_size, int context_base)
2944 {
2945 int i, len;
2946 static int num_allocs;
2947 static char pool_name[20];
2948
2949 d->ohci = ohci;
2950 d->type = type;
2951 d->ctx = ctx;
2952
2953 d->num_desc = num_desc;
2954 d->buf_size = buf_size;
2955 d->split_buf_size = split_buf_size;
2956
2957 d->ctrlSet = 0;
2958 d->ctrlClear = 0;
2959 d->cmdPtr = 0;
2960
2961 d->buf_cpu = kmalloc(d->num_desc * sizeof(quadlet_t*), GFP_ATOMIC);
2962 d->buf_bus = kmalloc(d->num_desc * sizeof(dma_addr_t), GFP_ATOMIC);
2963
2964 if (d->buf_cpu == NULL || d->buf_bus == NULL) {
2965 PRINT(KERN_ERR, "Failed to allocate dma buffer");
2966 free_dma_rcv_ctx(d);
2967 return -ENOMEM;
2968 }
2969 memset(d->buf_cpu, 0, d->num_desc * sizeof(quadlet_t*));
2970 memset(d->buf_bus, 0, d->num_desc * sizeof(dma_addr_t));
2971
2972 d->prg_cpu = kmalloc(d->num_desc * sizeof(struct dma_cmd*),
2973 GFP_ATOMIC);
2974 d->prg_bus = kmalloc(d->num_desc * sizeof(dma_addr_t), GFP_ATOMIC);
2975
2976 if (d->prg_cpu == NULL || d->prg_bus == NULL) {
2977 PRINT(KERN_ERR, "Failed to allocate dma prg");
2978 free_dma_rcv_ctx(d);
2979 return -ENOMEM;
2980 }
2981 memset(d->prg_cpu, 0, d->num_desc * sizeof(struct dma_cmd*));
2982 memset(d->prg_bus, 0, d->num_desc * sizeof(dma_addr_t));
2983
2984 d->spb = kmalloc(d->split_buf_size, GFP_ATOMIC);
2985
2986 if (d->spb == NULL) {
2987 PRINT(KERN_ERR, "Failed to allocate split buffer");
2988 free_dma_rcv_ctx(d);
2989 return -ENOMEM;
2990 }
2991
2992 len = sprintf(pool_name, "ohci1394_rcv_prg");
2993 sprintf(pool_name+len, "%d", num_allocs);
2994 d->prg_pool = pci_pool_create(pool_name, ohci->dev,
2995 sizeof(struct dma_cmd), 4, 0);
2996 if(d->prg_pool == NULL)
2997 {
2998 PRINT(KERN_ERR, "pci_pool_create failed for %s", pool_name);
2999 free_dma_rcv_ctx(d);
3000 return -ENOMEM;
3001 }
3002 num_allocs++;
3003
3004 OHCI_DMA_ALLOC("dma_rcv prg pool");
3005
3006 for (i=0; i<d->num_desc; i++) {
3007 d->buf_cpu[i] = pci_alloc_consistent(ohci->dev,
3008 d->buf_size,
3009 d->buf_bus+i);
3010 OHCI_DMA_ALLOC("consistent dma_rcv buf[%d]", i);
3011
3012 if (d->buf_cpu[i] != NULL) {
3013 memset(d->buf_cpu[i], 0, d->buf_size);
3014 } else {
3015 PRINT(KERN_ERR,
3016 "Failed to allocate dma buffer");
3017 free_dma_rcv_ctx(d);
3018 return -ENOMEM;
3019 }
3020
3021 d->prg_cpu[i] = pci_pool_alloc(d->prg_pool, SLAB_KERNEL, d->prg_bus+i);
3022 OHCI_DMA_ALLOC("pool dma_rcv prg[%d]", i);
3023
3024 if (d->prg_cpu[i] != NULL) {
3025 memset(d->prg_cpu[i], 0, sizeof(struct dma_cmd));
3026 } else {
3027 PRINT(KERN_ERR,
3028 "Failed to allocate dma prg");
3029 free_dma_rcv_ctx(d);
3030 return -ENOMEM;
3031 }
3032 }
3033
3034 spin_lock_init(&d->lock);
3035
3036 if (type == DMA_CTX_ISO) {
3037 ohci1394_init_iso_tasklet(&ohci->ir_legacy_tasklet,
3038 OHCI_ISO_MULTICHANNEL_RECEIVE,
3039 dma_rcv_tasklet, (unsigned long) d);
3040 } else {
3041 d->ctrlSet = context_base + OHCI1394_ContextControlSet;
3042 d->ctrlClear = context_base + OHCI1394_ContextControlClear;
3043 d->cmdPtr = context_base + OHCI1394_ContextCommandPtr;
3044
3045 tasklet_init (&d->task, dma_rcv_tasklet, (unsigned long) d);
3046 }
3047
3048 return 0;
3049 }
3050
3051 static void free_dma_trm_ctx(struct dma_trm_ctx *d)
3052 {
3053 int i;
3054 struct ti_ohci *ohci = d->ohci;
3055
3056 if (ohci == NULL)
3057 return;
3058
3059 DBGMSG("Freeing dma_trm_ctx %d", d->ctx);
3060
3061 if (d->prg_cpu) {
3062 for (i=0; i<d->num_desc; i++)
3063 if (d->prg_cpu[i] && d->prg_bus[i]) {
3064 pci_pool_free(d->prg_pool, d->prg_cpu[i], d->prg_bus[i]);
3065 OHCI_DMA_FREE("pool dma_trm prg[%d]", i);
3066 }
3067 pci_pool_destroy(d->prg_pool);
3068 OHCI_DMA_FREE("dma_trm prg pool");
3069 kfree(d->prg_cpu);
3070 kfree(d->prg_bus);
3071 }
3072
3073 /* Mark this context as freed. */
3074 d->ohci = NULL;
3075 }
3076
3077 static int
3078 alloc_dma_trm_ctx(struct ti_ohci *ohci, struct dma_trm_ctx *d,
3079 enum context_type type, int ctx, int num_desc,
3080 int context_base)
3081 {
3082 int i, len;
3083 static char pool_name[20];
3084 static int num_allocs=0;
3085
3086 d->ohci = ohci;
3087 d->type = type;
3088 d->ctx = ctx;
3089 d->num_desc = num_desc;
3090 d->ctrlSet = 0;
3091 d->ctrlClear = 0;
3092 d->cmdPtr = 0;
3093
3094 d->prg_cpu = kmalloc(d->num_desc * sizeof(struct at_dma_prg*),
3095 GFP_KERNEL);
3096 d->prg_bus = kmalloc(d->num_desc * sizeof(dma_addr_t), GFP_KERNEL);
3097
3098 if (d->prg_cpu == NULL || d->prg_bus == NULL) {
3099 PRINT(KERN_ERR, "Failed to allocate at dma prg");
3100 free_dma_trm_ctx(d);
3101 return -ENOMEM;
3102 }
3103 memset(d->prg_cpu, 0, d->num_desc * sizeof(struct at_dma_prg*));
3104 memset(d->prg_bus, 0, d->num_desc * sizeof(dma_addr_t));
3105
3106 len = sprintf(pool_name, "ohci1394_trm_prg");
3107 sprintf(pool_name+len, "%d", num_allocs);
3108 d->prg_pool = pci_pool_create(pool_name, ohci->dev,
3109 sizeof(struct at_dma_prg), 4, 0);
3110 if (d->prg_pool == NULL) {
3111 PRINT(KERN_ERR, "pci_pool_create failed for %s", pool_name);
3112 free_dma_trm_ctx(d);
3113 return -ENOMEM;
3114 }
3115 num_allocs++;
3116
3117 OHCI_DMA_ALLOC("dma_rcv prg pool");
3118
3119 for (i = 0; i < d->num_desc; i++) {
3120 d->prg_cpu[i] = pci_pool_alloc(d->prg_pool, SLAB_KERNEL, d->prg_bus+i);
3121 OHCI_DMA_ALLOC("pool dma_trm prg[%d]", i);
3122
3123 if (d->prg_cpu[i] != NULL) {
3124 memset(d->prg_cpu[i], 0, sizeof(struct at_dma_prg));
3125 } else {
3126 PRINT(KERN_ERR,
3127 "Failed to allocate at dma prg");
3128 free_dma_trm_ctx(d);
3129 return -ENOMEM;
3130 }
3131 }
3132
3133 spin_lock_init(&d->lock);
3134
3135 /* initialize tasklet */
3136 if (type == DMA_CTX_ISO) {
3137 ohci1394_init_iso_tasklet(&ohci->it_legacy_tasklet, OHCI_ISO_TRANSMIT,
3138 dma_trm_tasklet, (unsigned long) d);
3139 if (ohci1394_register_iso_tasklet(ohci,
3140 &ohci->it_legacy_tasklet) < 0) {
3141 PRINT(KERN_ERR, "No IT DMA context available");
3142 free_dma_trm_ctx(d);
3143 return -EBUSY;
3144 }
3145
3146 /* IT can be assigned to any context by register_iso_tasklet */
3147 d->ctx = ohci->it_legacy_tasklet.context;
3148 d->ctrlSet = OHCI1394_IsoXmitContextControlSet + 16 * d->ctx;
3149 d->ctrlClear = OHCI1394_IsoXmitContextControlClear + 16 * d->ctx;
3150 d->cmdPtr = OHCI1394_IsoXmitCommandPtr + 16 * d->ctx;
3151 } else {
3152 d->ctrlSet = context_base + OHCI1394_ContextControlSet;
3153 d->ctrlClear = context_base + OHCI1394_ContextControlClear;
3154 d->cmdPtr = context_base + OHCI1394_ContextCommandPtr;
3155 tasklet_init (&d->task, dma_trm_tasklet, (unsigned long)d);
3156 }
3157
3158 return 0;
3159 }
3160
3161 static void ohci_set_hw_config_rom(struct hpsb_host *host, quadlet_t *config_rom)
3162 {
3163 struct ti_ohci *ohci = host->hostdata;
3164
3165 reg_write(ohci, OHCI1394_ConfigROMhdr, be32_to_cpu(config_rom[0]));
3166 reg_write(ohci, OHCI1394_BusOptions, be32_to_cpu(config_rom[2]));
3167
3168 memcpy(ohci->csr_config_rom_cpu, config_rom, OHCI_CONFIG_ROM_LEN);
3169 }
3170
3171
3172 static quadlet_t ohci_hw_csr_reg(struct hpsb_host *host, int reg,
3173 quadlet_t data, quadlet_t compare)
3174 {
3175 struct ti_ohci *ohci = host->hostdata;
3176 int i;
3177
3178 reg_write(ohci, OHCI1394_CSRData, data);
3179 reg_write(ohci, OHCI1394_CSRCompareData, compare);
3180 reg_write(ohci, OHCI1394_CSRControl, reg & 0x3);
3181
3182 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
3183 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
3184 break;
3185
3186 mdelay(1);
3187 }
3188
3189 return reg_read(ohci, OHCI1394_CSRData);
3190 }
3191
3192 static struct hpsb_host_driver ohci1394_driver = {
3193 .owner = THIS_MODULE,
3194 .name = OHCI1394_DRIVER_NAME,
3195 .set_hw_config_rom = ohci_set_hw_config_rom,
3196 .transmit_packet = ohci_transmit,
3197 .devctl = ohci_devctl,
3198 .isoctl = ohci_isoctl,
3199 .hw_csr_reg = ohci_hw_csr_reg,
3200 };
3201
3202 \f
3203
3204 /***********************************
3205 * PCI Driver Interface functions *
3206 ***********************************/
3207
3208 #define FAIL(err, fmt, args...) \
3209 do { \
3210 PRINT_G(KERN_ERR, fmt , ## args); \
3211 ohci1394_pci_remove(dev); \
3212 return err; \
3213 } while (0)
3214
3215 static int __devinit ohci1394_pci_probe(struct pci_dev *dev,
3216 const struct pci_device_id *ent)
3217 {
3218 static int version_printed = 0;
3219
3220 struct hpsb_host *host;
3221 struct ti_ohci *ohci; /* shortcut to currently handled device */
3222 unsigned long ohci_base;
3223
3224 if (version_printed++ == 0)
3225 PRINT_G(KERN_INFO, "%s", version);
3226
3227 if (pci_enable_device(dev))
3228 FAIL(-ENXIO, "Failed to enable OHCI hardware");
3229 pci_set_master(dev);
3230
3231 host = hpsb_alloc_host(&ohci1394_driver, sizeof(struct ti_ohci), &dev->dev);
3232 if (!host) FAIL(-ENOMEM, "Failed to allocate host structure");
3233
3234 ohci = host->hostdata;
3235 ohci->dev = dev;
3236 ohci->host = host;
3237 ohci->init_state = OHCI_INIT_ALLOC_HOST;
3238 host->pdev = dev;
3239 pci_set_drvdata(dev, ohci);
3240
3241 /* We don't want hardware swapping */
3242 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3243
3244 /* Some oddball Apple controllers do not order the selfid
3245 * properly, so we make up for it here. */
3246 #ifndef __LITTLE_ENDIAN
3247 /* XXX: Need a better way to check this. I'm wondering if we can
3248 * read the values of the OHCI1394_PCI_HCI_Control and the
3249 * noByteSwapData registers to see if they were not cleared to
3250 * zero. Should this work? Obviously it's not defined what these
3251 * registers will read when they aren't supported. Bleh! */
3252 if (dev->vendor == PCI_VENDOR_ID_APPLE &&
3253 dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW) {
3254 ohci->no_swap_incoming = 1;
3255 ohci->selfid_swap = 0;
3256 } else
3257 ohci->selfid_swap = 1;
3258 #endif
3259
3260
3261 #ifndef PCI_DEVICE_ID_NVIDIA_NFORCE2_FW
3262 #define PCI_DEVICE_ID_NVIDIA_NFORCE2_FW 0x006e
3263 #endif
3264
3265 /* These chipsets require a bit of extra care when checking after
3266 * a busreset. */
3267 if ((dev->vendor == PCI_VENDOR_ID_APPLE &&
3268 dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW) ||
3269 (dev->vendor == PCI_VENDOR_ID_NVIDIA &&
3270 dev->device == PCI_DEVICE_ID_NVIDIA_NFORCE2_FW))
3271 ohci->check_busreset = 1;
3272
3273 /* We hardwire the MMIO length, since some CardBus adaptors
3274 * fail to report the right length. Anyway, the ohci spec
3275 * clearly says it's 2kb, so this shouldn't be a problem. */
3276 ohci_base = pci_resource_start(dev, 0);
3277 if (pci_resource_len(dev, 0) != OHCI1394_REGISTER_SIZE)
3278 PRINT(KERN_WARNING, "Unexpected PCI resource length of %lx!",
3279 pci_resource_len(dev, 0));
3280
3281 /* Seems PCMCIA handles this internally. Not sure why. Seems
3282 * pretty bogus to force a driver to special case this. */
3283 #ifndef PCMCIA
3284 if (!request_mem_region (ohci_base, OHCI1394_REGISTER_SIZE, OHCI1394_DRIVER_NAME))
3285 FAIL(-ENOMEM, "MMIO resource (0x%lx - 0x%lx) unavailable",
3286 ohci_base, ohci_base + OHCI1394_REGISTER_SIZE);
3287 #endif
3288 ohci->init_state = OHCI_INIT_HAVE_MEM_REGION;
3289
3290 ohci->registers = ioremap(ohci_base, OHCI1394_REGISTER_SIZE);
3291 if (ohci->registers == NULL)
3292 FAIL(-ENXIO, "Failed to remap registers - card not accessible");
3293 ohci->init_state = OHCI_INIT_HAVE_IOMAPPING;
3294 DBGMSG("Remapped memory spaces reg 0x%p", ohci->registers);
3295
3296 /* csr_config rom allocation */
3297 ohci->csr_config_rom_cpu =
3298 pci_alloc_consistent(ohci->dev, OHCI_CONFIG_ROM_LEN,
3299 &ohci->csr_config_rom_bus);
3300 OHCI_DMA_ALLOC("consistent csr_config_rom");
3301 if (ohci->csr_config_rom_cpu == NULL)
3302 FAIL(-ENOMEM, "Failed to allocate buffer config rom");
3303 ohci->init_state = OHCI_INIT_HAVE_CONFIG_ROM_BUFFER;
3304
3305 /* self-id dma buffer allocation */
3306 ohci->selfid_buf_cpu =
3307 pci_alloc_consistent(ohci->dev, OHCI1394_SI_DMA_BUF_SIZE,
3308 &ohci->selfid_buf_bus);
3309 OHCI_DMA_ALLOC("consistent selfid_buf");
3310
3311 if (ohci->selfid_buf_cpu == NULL)
3312 FAIL(-ENOMEM, "Failed to allocate DMA buffer for self-id packets");
3313 ohci->init_state = OHCI_INIT_HAVE_SELFID_BUFFER;
3314
3315 if ((unsigned long)ohci->selfid_buf_cpu & 0x1fff)
3316 PRINT(KERN_INFO, "SelfID buffer %p is not aligned on "
3317 "8Kb boundary... may cause problems on some CXD3222 chip",
3318 ohci->selfid_buf_cpu);
3319
3320 /* No self-id errors at startup */
3321 ohci->self_id_errors = 0;
3322
3323 ohci->init_state = OHCI_INIT_HAVE_TXRX_BUFFERS__MAYBE;
3324 /* AR DMA request context allocation */
3325 if (alloc_dma_rcv_ctx(ohci, &ohci->ar_req_context,
3326 DMA_CTX_ASYNC_REQ, 0, AR_REQ_NUM_DESC,
3327 AR_REQ_BUF_SIZE, AR_REQ_SPLIT_BUF_SIZE,
3328 OHCI1394_AsReqRcvContextBase) < 0)
3329 FAIL(-ENOMEM, "Failed to allocate AR Req context");
3330
3331 /* AR DMA response context allocation */
3332 if (alloc_dma_rcv_ctx(ohci, &ohci->ar_resp_context,
3333 DMA_CTX_ASYNC_RESP, 0, AR_RESP_NUM_DESC,
3334 AR_RESP_BUF_SIZE, AR_RESP_SPLIT_BUF_SIZE,
3335 OHCI1394_AsRspRcvContextBase) < 0)
3336 FAIL(-ENOMEM, "Failed to allocate AR Resp context");
3337
3338 /* AT DMA request context */
3339 if (alloc_dma_trm_ctx(ohci, &ohci->at_req_context,
3340 DMA_CTX_ASYNC_REQ, 0, AT_REQ_NUM_DESC,
3341 OHCI1394_AsReqTrContextBase) < 0)
3342 FAIL(-ENOMEM, "Failed to allocate AT Req context");
3343
3344 /* AT DMA response context */
3345 if (alloc_dma_trm_ctx(ohci, &ohci->at_resp_context,
3346 DMA_CTX_ASYNC_RESP, 1, AT_RESP_NUM_DESC,
3347 OHCI1394_AsRspTrContextBase) < 0)
3348 FAIL(-ENOMEM, "Failed to allocate AT Resp context");
3349
3350 /* Start off with a soft reset, to clear everything to a sane
3351 * state. */
3352 ohci_soft_reset(ohci);
3353
3354 /* Now enable LPS, which we need in order to start accessing
3355 * most of the registers. In fact, on some cards (ALI M5251),
3356 * accessing registers in the SClk domain without LPS enabled
3357 * will lock up the machine. Wait 50msec to make sure we have
3358 * full link enabled. */
3359 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS);
3360
3361 /* Disable and clear interrupts */
3362 reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
3363 reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
3364
3365 mdelay(50);
3366
3367 /* Determine the number of available IR and IT contexts. */
3368 ohci->nb_iso_rcv_ctx =
3369 get_nb_iso_ctx(ohci, OHCI1394_IsoRecvIntMaskSet);
3370 DBGMSG("%d iso receive contexts available",
3371 ohci->nb_iso_rcv_ctx);
3372
3373 ohci->nb_iso_xmit_ctx =
3374 get_nb_iso_ctx(ohci, OHCI1394_IsoXmitIntMaskSet);
3375 DBGMSG("%d iso transmit contexts available",
3376 ohci->nb_iso_xmit_ctx);
3377
3378 /* Set the usage bits for non-existent contexts so they can't
3379 * be allocated */
3380 ohci->ir_ctx_usage = ~0 << ohci->nb_iso_rcv_ctx;
3381 ohci->it_ctx_usage = ~0 << ohci->nb_iso_xmit_ctx;
3382
3383 INIT_LIST_HEAD(&ohci->iso_tasklet_list);
3384 spin_lock_init(&ohci->iso_tasklet_list_lock);
3385 ohci->ISO_channel_usage = 0;
3386 spin_lock_init(&ohci->IR_channel_lock);
3387
3388 /* Allocate the IR DMA context right here so we don't have
3389 * to do it in interrupt path - note that this doesn't
3390 * waste much memory and avoids the jugglery required to
3391 * allocate it in IRQ path. */
3392 if (alloc_dma_rcv_ctx(ohci, &ohci->ir_legacy_context,
3393 DMA_CTX_ISO, 0, IR_NUM_DESC,
3394 IR_BUF_SIZE, IR_SPLIT_BUF_SIZE,
3395 OHCI1394_IsoRcvContextBase) < 0) {
3396 FAIL(-ENOMEM, "Cannot allocate IR Legacy DMA context");
3397 }
3398
3399 /* We hopefully don't have to pre-allocate IT DMA like we did
3400 * for IR DMA above. Allocate it on-demand and mark inactive. */
3401 ohci->it_legacy_context.ohci = NULL;
3402
3403 if (request_irq(dev->irq, ohci_irq_handler, SA_SHIRQ,
3404 OHCI1394_DRIVER_NAME, ohci))
3405 FAIL(-ENOMEM, "Failed to allocate shared interrupt %d", dev->irq);
3406
3407 ohci->init_state = OHCI_INIT_HAVE_IRQ;
3408 ohci_initialize(ohci);
3409
3410 /* Set certain csr values */
3411 host->csr.guid_hi = reg_read(ohci, OHCI1394_GUIDHi);
3412 host->csr.guid_lo = reg_read(ohci, OHCI1394_GUIDLo);
3413 host->csr.cyc_clk_acc = 100; /* how do we determine clk accuracy? */
3414 host->csr.max_rec = (reg_read(ohci, OHCI1394_BusOptions) >> 12) & 0xf;
3415 host->csr.lnk_spd = reg_read(ohci, OHCI1394_BusOptions) & 0x7;
3416
3417 /* Tell the highlevel this host is ready */
3418 if (hpsb_add_host(host))
3419 FAIL(-ENOMEM, "Failed to register host with highlevel");
3420
3421 ohci->init_state = OHCI_INIT_DONE;
3422
3423 return 0;
3424 #undef FAIL
3425 }
3426
3427 static void ohci1394_pci_remove(struct pci_dev *pdev)
3428 {
3429 struct ti_ohci *ohci;
3430 struct device *dev;
3431
3432 ohci = pci_get_drvdata(pdev);
3433 if (!ohci)
3434 return;
3435
3436 dev = get_device(&ohci->host->device);
3437
3438 switch (ohci->init_state) {
3439 case OHCI_INIT_DONE:
3440 hpsb_remove_host(ohci->host);
3441
3442 /* Clear out BUS Options */
3443 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
3444 reg_write(ohci, OHCI1394_BusOptions,
3445 (reg_read(ohci, OHCI1394_BusOptions) & 0x0000f007) |
3446 0x00ff0000);
3447 memset(ohci->csr_config_rom_cpu, 0, OHCI_CONFIG_ROM_LEN);
3448
3449 case OHCI_INIT_HAVE_IRQ:
3450 /* Clear interrupt registers */
3451 reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
3452 reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
3453 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);
3454 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);
3455 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);
3456 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);
3457
3458 /* Disable IRM Contender */
3459 set_phy_reg(ohci, 4, ~0xc0 & get_phy_reg(ohci, 4));
3460
3461 /* Clear link control register */
3462 reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);
3463
3464 /* Let all other nodes know to ignore us */
3465 ohci_devctl(ohci->host, RESET_BUS, LONG_RESET_NO_FORCE_ROOT);
3466
3467 /* Soft reset before we start - this disables
3468 * interrupts and clears linkEnable and LPS. */
3469 ohci_soft_reset(ohci);
3470 free_irq(ohci->dev->irq, ohci);
3471
3472 case OHCI_INIT_HAVE_TXRX_BUFFERS__MAYBE:
3473 /* The ohci_soft_reset() stops all DMA contexts, so we
3474 * dont need to do this. */
3475 /* Free AR dma */
3476 free_dma_rcv_ctx(&ohci->ar_req_context);
3477 free_dma_rcv_ctx(&ohci->ar_resp_context);
3478
3479 /* Free AT dma */
3480 free_dma_trm_ctx(&ohci->at_req_context);
3481 free_dma_trm_ctx(&ohci->at_resp_context);
3482
3483 /* Free IR dma */
3484 free_dma_rcv_ctx(&ohci->ir_legacy_context);
3485
3486 /* Free IT dma */
3487 free_dma_trm_ctx(&ohci->it_legacy_context);
3488
3489 /* Free IR legacy dma */
3490 free_dma_rcv_ctx(&ohci->ir_legacy_context);
3491
3492
3493 case OHCI_INIT_HAVE_SELFID_BUFFER:
3494 pci_free_consistent(ohci->dev, OHCI1394_SI_DMA_BUF_SIZE,
3495 ohci->selfid_buf_cpu,
3496 ohci->selfid_buf_bus);
3497 OHCI_DMA_FREE("consistent selfid_buf");
3498
3499 case OHCI_INIT_HAVE_CONFIG_ROM_BUFFER:
3500 pci_free_consistent(ohci->dev, OHCI_CONFIG_ROM_LEN,
3501 ohci->csr_config_rom_cpu,
3502 ohci->csr_config_rom_bus);
3503 OHCI_DMA_FREE("consistent csr_config_rom");
3504
3505 case OHCI_INIT_HAVE_IOMAPPING:
3506 iounmap(ohci->registers);
3507
3508 case OHCI_INIT_HAVE_MEM_REGION:
3509 #ifndef PCMCIA
3510 release_mem_region(pci_resource_start(ohci->dev, 0),
3511 OHCI1394_REGISTER_SIZE);
3512 #endif
3513
3514 #ifdef CONFIG_PPC_PMAC
3515 /* On UniNorth, power down the cable and turn off the chip
3516 * clock when the module is removed to save power on
3517 * laptops. Turning it back ON is done by the arch code when
3518 * pci_enable_device() is called */
3519 {
3520 struct device_node* of_node;
3521
3522 of_node = pci_device_to_OF_node(ohci->dev);
3523 if (of_node) {
3524 pmac_call_feature(PMAC_FTR_1394_ENABLE, of_node, 0, 0);
3525 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, of_node, 0, 0);
3526 }
3527 }
3528 #endif /* CONFIG_PPC_PMAC */
3529
3530 case OHCI_INIT_ALLOC_HOST:
3531 pci_set_drvdata(ohci->dev, NULL);
3532 }
3533
3534 if (dev)
3535 put_device(dev);
3536 }
3537
3538
3539 static int ohci1394_pci_resume (struct pci_dev *pdev)
3540 {
3541 #ifdef CONFIG_PMAC_PBOOK
3542 {
3543 struct device_node *of_node;
3544
3545 /* Re-enable 1394 */
3546 of_node = pci_device_to_OF_node (pdev);
3547 if (of_node)
3548 pmac_call_feature (PMAC_FTR_1394_ENABLE, of_node, 0, 1);
3549 }
3550 #endif
3551
3552 pci_enable_device(pdev);
3553
3554 return 0;
3555 }
3556
3557
3558 static int ohci1394_pci_suspend (struct pci_dev *pdev, pm_message_t state)
3559 {
3560 #ifdef CONFIG_PMAC_PBOOK
3561 {
3562 struct device_node *of_node;
3563
3564 /* Disable 1394 */
3565 of_node = pci_device_to_OF_node (pdev);
3566 if (of_node)
3567 pmac_call_feature(PMAC_FTR_1394_ENABLE, of_node, 0, 0);
3568 }
3569 #endif
3570
3571 return 0;
3572 }
3573
3574
3575 #define PCI_CLASS_FIREWIRE_OHCI ((PCI_CLASS_SERIAL_FIREWIRE << 8) | 0x10)
3576
3577 static struct pci_device_id ohci1394_pci_tbl[] = {
3578 {
3579 .class = PCI_CLASS_FIREWIRE_OHCI,
3580 .class_mask = PCI_ANY_ID,
3581 .vendor = PCI_ANY_ID,
3582 .device = PCI_ANY_ID,
3583 .subvendor = PCI_ANY_ID,
3584 .subdevice = PCI_ANY_ID,
3585 },
3586 { 0, },
3587 };
3588
3589 MODULE_DEVICE_TABLE(pci, ohci1394_pci_tbl);
3590
3591 static struct pci_driver ohci1394_pci_driver = {
3592 .name = OHCI1394_DRIVER_NAME,
3593 .id_table = ohci1394_pci_tbl,
3594 .probe = ohci1394_pci_probe,
3595 .remove = ohci1394_pci_remove,
3596 .resume = ohci1394_pci_resume,
3597 .suspend = ohci1394_pci_suspend,
3598 };
3599
3600 \f
3601
3602 /***********************************
3603 * OHCI1394 Video Interface *
3604 ***********************************/
3605
3606 /* essentially the only purpose of this code is to allow another
3607 module to hook into ohci's interrupt handler */
3608
3609 int ohci1394_stop_context(struct ti_ohci *ohci, int reg, char *msg)
3610 {
3611 int i=0;
3612
3613 /* stop the channel program if it's still running */
3614 reg_write(ohci, reg, 0x8000);
3615
3616 /* Wait until it effectively stops */
3617 while (reg_read(ohci, reg) & 0x400) {
3618 i++;
3619 if (i>5000) {
3620 PRINT(KERN_ERR,
3621 "Runaway loop while stopping context: %s...", msg ? msg : "");
3622 return 1;
3623 }
3624
3625 mb();
3626 udelay(10);
3627 }
3628 if (msg) PRINT(KERN_ERR, "%s: dma prg stopped", msg);
3629 return 0;
3630 }
3631
3632 void ohci1394_init_iso_tasklet(struct ohci1394_iso_tasklet *tasklet, int type,
3633 void (*func)(unsigned long), unsigned long data)
3634 {
3635 tasklet_init(&tasklet->tasklet, func, data);
3636 tasklet->type = type;
3637 /* We init the tasklet->link field, so we can list_del() it
3638 * without worrying whether it was added to the list or not. */
3639 INIT_LIST_HEAD(&tasklet->link);
3640 }
3641
3642 int ohci1394_register_iso_tasklet(struct ti_ohci *ohci,
3643 struct ohci1394_iso_tasklet *tasklet)
3644 {
3645 unsigned long flags, *usage;
3646 int n, i, r = -EBUSY;
3647
3648 if (tasklet->type == OHCI_ISO_TRANSMIT) {
3649 n = ohci->nb_iso_xmit_ctx;
3650 usage = &ohci->it_ctx_usage;
3651 }
3652 else {
3653 n = ohci->nb_iso_rcv_ctx;
3654 usage = &ohci->ir_ctx_usage;
3655
3656 /* only one receive context can be multichannel (OHCI sec 10.4.1) */
3657 if (tasklet->type == OHCI_ISO_MULTICHANNEL_RECEIVE) {
3658 if (test_and_set_bit(0, &ohci->ir_multichannel_used)) {
3659 return r;
3660 }
3661 }
3662 }
3663
3664 spin_lock_irqsave(&ohci->iso_tasklet_list_lock, flags);
3665
3666 for (i = 0; i < n; i++)
3667 if (!test_and_set_bit(i, usage)) {
3668 tasklet->context = i;
3669 list_add_tail(&tasklet->link, &ohci->iso_tasklet_list);
3670 r = 0;
3671 break;
3672 }
3673
3674 spin_unlock_irqrestore(&ohci->iso_tasklet_list_lock, flags);
3675
3676 return r;
3677 }
3678
3679 void ohci1394_unregister_iso_tasklet(struct ti_ohci *ohci,
3680 struct ohci1394_iso_tasklet *tasklet)
3681 {
3682 unsigned long flags;
3683
3684 tasklet_kill(&tasklet->tasklet);
3685
3686 spin_lock_irqsave(&ohci->iso_tasklet_list_lock, flags);
3687
3688 if (tasklet->type == OHCI_ISO_TRANSMIT)
3689 clear_bit(tasklet->context, &ohci->it_ctx_usage);
3690 else {
3691 clear_bit(tasklet->context, &ohci->ir_ctx_usage);
3692
3693 if (tasklet->type == OHCI_ISO_MULTICHANNEL_RECEIVE) {
3694 clear_bit(0, &ohci->ir_multichannel_used);
3695 }
3696 }
3697
3698 list_del(&tasklet->link);
3699
3700 spin_unlock_irqrestore(&ohci->iso_tasklet_list_lock, flags);
3701 }
3702
3703 EXPORT_SYMBOL(ohci1394_stop_context);
3704 EXPORT_SYMBOL(ohci1394_init_iso_tasklet);
3705 EXPORT_SYMBOL(ohci1394_register_iso_tasklet);
3706 EXPORT_SYMBOL(ohci1394_unregister_iso_tasklet);
3707
3708
3709 /***********************************
3710 * General module initialization *
3711 ***********************************/
3712
3713 MODULE_AUTHOR("Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>");
3714 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE-1394 controllers");
3715 MODULE_LICENSE("GPL");
3716
3717 static void __exit ohci1394_cleanup (void)
3718 {
3719 pci_unregister_driver(&ohci1394_pci_driver);
3720 }
3721
3722 static int __init ohci1394_init(void)
3723 {
3724 return pci_register_driver(&ohci1394_pci_driver);
3725 }
3726
3727 module_init(ohci1394_init);
3728 module_exit(ohci1394_cleanup);
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